Commit Graph

37062 Commits

Author SHA1 Message Date
Rob Barnes a01ee36288 device/dram: Add method for converting MHz to MT/s
Add method for converting DDR4 speed in MHz to MT/s. Checks that MHz is
within a speed grade range.

BUG=b:167155849
TEST=ddr4-test unit test
BRANCH=Zork

Change-Id: I1433f028afb794fe3e397b03f5bd0565494c8130
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 03:24:50 +00:00
Lucas Chen fcd7d0518c zork/var/ezkinil: Fix Touchscreen doesn't work on v3.6x rework board
The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but
addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed.

BRANCH=zork
BUG=b:168580357
TEST=Check Touchscreen function work

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 02:04:25 +00:00
Ravi Kumar Bokka 9c0b8ef83c trogdor: invoke new watchdog function before qclib runs
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45212
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 00:44:18 +00:00
Ravi Kumar Bokka 6fde4c56b0 sc7180: report hardware watchdog reset after reboot
add WATCHDOG_TOMBSTONE in memlayout.ld

Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-16 00:44:09 +00:00
Felix Held 336ed66e35 soc/amd/stoneyridge/acpi/sb_pci0_fch: remove duplicate I/O range
This I/O region is already covered by the range declared right above the
deleted one.

Change-Id: I8b8ff3385bbba8e69101ee2c5a5cb39c8f996b94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 19:31:54 +00:00
Felix Held 4ed3116f33 soc/amd/picasso/acpi/sb_pci0_fch: remove duplicate I/O range reservation
This I/O region is already covered by the range declared right above the
deleted one.

TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork

Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 19:31:48 +00:00
Patrick Rudolph a1ef21301b nb/intel/ironlake/raminit: Work around compiler bug
This fixes commit e1d1fe454c
initialize 'reply.command'.

The compiler now optimized away the final condition, that checks
the result of heci message, resulting in a binary that always
calls die().

Fix that behaviour by using volatile.
Tested on Lenovo T410: Boots again into Linux.

Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-15 18:03:26 +00:00
Subrata Banik 292afef2fb soc/intel/alderlake/romstage: Do initial SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API

Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-15 15:13:50 +00:00
Subrata Banik eb17b475c8 mb/intel/jasperlake_rvp: Fix wrong comments for ECT
Disable -> Enable

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-15 15:13:06 +00:00
Jason Glenesk 201acca634 acpi: Correct sizes for ACPI data fields
Correct sizes of Count, Type, and Latency data field in _CST object to
integer, byte, word, respectively. Correct size of NumEntries data field
in _CSD object to integer.

BUG=b:155307433
TEST=Boot Morphius and dump SSDT _CST and _CSD objects. Confirm that
sizes written conform to ACPI_6_3_May16.pdf ACPI specification.
BRANCH=Zork

Change-Id: I356b46f2fa787e18442a66280b6545a3b525a08b
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45339
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 13:41:58 +00:00
Patrick Rudolph 11c1b94d03 soc/intel/common/block/cpu: Fix boot failure
This fixes commit 1b89f5e "Guard options with if-blocks".

The code no longer returns if SGX is disabled, but as the PRMRR
configuration is missing it runs into die().

Tested on Prodrive Hermes: Boots again into Linux.

Change-Id: I6d32ca32b1b53767b2db91305103cd532823a5ca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-15 09:17:58 +00:00
V Sowmya 186250f68e common/block/pmc: Add a check to program the PchPmPwrCycDur
This patch adds a check to avoid violating the PCH EDS recommendation
that the PchPmPwrCycDur will never be smaller than the the SLP_Sx
assertion widths.

This code was initially added for cannonlake and now moving it to common
code since the same check will be used to program the PchPmPwrCycDur
for Jasperlake and Tigerlake.

Change-Id: Ie7d5f54939c5eb1f885d303f75a04958b9d77f4d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 07:02:04 +00:00
Ren Kuo 98b0a98891 mb/google/dedede/var/magolor: Add touch screen devices
add the magolor touch screen ctrl devices:
1)elan 6915
2)elan 5012
3)raydium RM32680

BUG=b:166711761
BRANCH=None
TEST=build firmware and verify the touch functions on DUT

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 07:01:29 +00:00
Furquan Shaikh b0334e13ba mb/google/zork: Fix FPMCU_INT_L configuration
Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge
triggered. Also, we are using GEVENT for wake from fingerprint and
not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables
does not need to be set to indicate wake for the IRQ.

This change updates GPIO table to configure the pad as level triggered
and drops the wake attribute for irq_gpio in overridetree.

BUG=b:165612778
BRANCH=zork
TEST=Verified that fingerprint still works in S0 and to wake device
from S3.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-15 03:57:43 +00:00
Ravi Kumar Bokka 5ed3cb99ac chromeos: Provide common watchdog reboot support in romstage
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I2a1f1411e9d58a0738e0e8057f5b1ad049bf03e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 01:09:38 +00:00
Taniya Das 4236187dea sc7180: clock: Remove unwanted QUPv3 Frequency
As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.

Tested: Compile and boot up testing.

Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15 01:07:27 +00:00
Roja Rani Yarubandi dcf80ab025 sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency
with the lowest supported frequency from QUP clock table.
With this console logs were getting corrupted at qclib stage.

In ChromeOS coreboot, baudrate is configuarable using Kconfig.
QcLib should not assume the baudrate and reconfigure any UART
register once after the configuration is done in coreboot.

To fix the issue QcLib done the changes to not to reconfigure
any UART registers. Hence clock_configure_qup() is not required
in coreboot UART driver.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15 01:07:17 +00:00
Nico Huber 308540de80 nb/intel/ironlake: Reserve gap betwen TSEG and BGSM
There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.

TEST=Booted Thinkpad X201s, allocated resources are above TOLUD.

Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 20:15:06 +00:00
Nico Huber 08e8e47d03 nb/intel/ironlake: Use an `index` variable for resources
Change-Id: Ic587231b57c51db592c1647de138a67c55161e58
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 20:14:47 +00:00
Elyes HAOUAS 66039a5cb8 src/mainboard: Remove unused include <device/pnp_ops.h>
Change-Id: I278fb20aa176bb09f1ff135fdfd732f0096d3808
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:38:14 +00:00
Elyes HAOUAS 864d1cfeca mb/amd/olivehill/bootblock.c: Add missing <arch/io.h>
Change-Id: I75ea4fc71cf22e5ad547329db2451342cee528b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:36:58 +00:00
Elyes HAOUAS b4093dca8d src/superio: Remove unused <device/pnp_def.h>
Change-Id: I835e8786b84ec16889fd08f566328bc7a0a60c90
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:36:27 +00:00
Elyes HAOUAS 79a3de16a1 src/{device,include}: Use PNP_IDX_EN instead of magic number
Change-Id: I68590605e261ecaace9f3cea28cfa6ec3b913a8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:34:11 +00:00
Shelley Chen 475978875d drivers/elog: Remove ELOG_PRERAM config
This change is being done for the following reasons:
1.  The CONFIG_ELOG_PRERAM is unused.
2.  We need to pull in elog.c into romstage because we are pulling the
    mrc_cache_stash_data function into romstage.
3.  Furquan says that we can rely on the linker to optimize out the
    unused 4KiB buffer in the early stages of boot, which allows us to
    get rid of the ELOG_PRERAM config.

BUG=b:117884485, b:150502246
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a -v

Change-Id: Id76cabc38e41e9bf79e1580a530c871a4ecef4ec
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45303
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 18:23:23 +00:00
Josie Nordrum c3cc158408 lib/fmap: add ENV_SMM check to setup_preram_cache
Add check in setup_preram_cache to return if ENV_SMM is true.
This avoids false warning that post-RAM FMAP is accessed too early
caused by ENV_ROMSTAGE_OR_BEFORE evaluation in SMI handler.

BUG=b:167321319
BRANCH=None
TEST=None

Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I3a4c199c42ee556187d6c4277e8793a36e4d493b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14 16:01:42 +00:00
Subrata Banik 7ad46df850 soc/intel/common/block: Use pci_dev_request_bus_master for BM enabling
Enabling Bus Master isn't required by the hardware, so we shouldn't need
to enable it at all. However, some payloads do not set this bit before
attempting DMA transfers, which results in boot failures.

Replace static sata_final() implementation for BM enabling with generic
pci_dev_request_bus_master() function.

This allows the user to control through Kconfig whether Bus Master
should be enabled.

TEST=Able to boot to OS from SATA device on CML platform.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Icd086184fd6fa9c03c806c857f13fad5a9e78a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 12:07:04 +00:00
Subrata Banik 9fec889e82 soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h
Removed unused header files in chip.h

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-14 12:06:39 +00:00
Subrata Banik c9d598a581 soc/intel/jasperlake: Clean up iomap.h and systemagent.h
List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ief13406b0116ce0f0b7472e5b133b3fac06f6e27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-14 11:53:27 +00:00
Michael Niewöhner 8ca0b21060 soc/intel/cnl: Add ACPI support for PMC core OS driver
PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug
hooks to developers and end users to quickly figure out why their
platform is not entering a deeper idle state such as S0ix.

Include the common pmc.asl added in commit 957481c.

Test: PMC gets detected by Linux kernel module.

Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45318
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 11:51:02 +00:00
Masanori Ogino 33f64b5d78 crossgcc: Fix libcpp to address -Wformat-security
On some systems where the system compiler enables `-Wformat-security
-Werror=format-security` options by default, building libcpp fails
because the code passes a variable directly as a format string.

This change addresses this problem by patching the affected code.

Tested with the default compiler of Nixpkgs unstable, GCC 9.3.0 with the
options described above enabled by default.

Signed-off-by: Masanori Ogino <mogino@acm.org>
Change-Id: Ibf3c9e79ce10cd400c9f7ea40dd6de1ab81b50e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:11:59 +00:00
Idwer Vollering 3c5b803bdb util/cbfstool: extend includes in commonlib
Certain non-Linux OSes require an include file in different
places.

Build tested on Linux, FreeBSD.

Change-Id: Icd81c2a96c608589ce2ec8f4b883fd4e584776b1
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:10:53 +00:00
Elyes HAOUAS 563fc0889f src/include: Drop unneeded empty lines
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 07:09:41 +00:00
Raul E Rangel 7c79d8302b soc/amd/picasso: Move sd_emmc_config into emmc_config struct
I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.

BUG=b:159823235
TEST=Build test

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14 07:09:23 +00:00
Ravi Sarawadi 73cd3e704f mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
DP_HPD had been removed for EVT design as those events are through eSPI.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=b:162566436
TEST=Booted to kernel and verified no kernel HPD pins assertion message
on Delbin board.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-14 07:09:11 +00:00
John Su 47c4bf5571 mb/google/octopus/variants/fleex: Add G2Touch touchscreen support
BUG=b:167297664
BRANCH=octopus
TEST=build fleex, and check touchscreen can work

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980
Reviewed-by: Justin TerAvest <teravest@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:08:56 +00:00
Kangheui Won 5f027fa4c2 soc/amd/picasso: copy local info to transfer buf
We added transfer_info_struct to contain various information about
memory region we pass from PSP to x86 in commit 0c12abe462.

This should be at the start of transfer region but we only manipulated
it as local variable and didn't put data into the region, resulting
garbage data for transfer_info when x86 tries to read it.

Copy the content of local variable to beginning of _transfer_buffer
before requesting transfer to PSP so coreboot on x86 can access it.

BUG=b:159220781
BRANCH=zork
TEST=check transfer_info_struct is correctly populated on romstage

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:08:39 +00:00
Angel Pons 8840bcfa86 include/superio/hwm5_conf.h: Fix copy-pasted comments
Comments say `port`, but the actual function signature uses `base`.

Change-Id: I28a2f24a9701aec2fb990ca2f38e5f2794e15f0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45226
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:08:03 +00:00
Karthikeyan Ramasubramanian 410af46cd6 mb/google/dedede/var/boten: Add audio configuration
Add configuration for ALC5682 headphone jack and ALC1015 speaker
amplifier. Also turn on the HDA PCI device.

BUG=b:161667665
TEST=Build the boten board and verified the audio functionality.

Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:07:24 +00:00
Angel Pons 19b2599cb5 sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together
isn't useful. Make `ISLP` return a constant, so that IASL can fold it.

Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45048
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:07:12 +00:00
Angel Pons d9f1b04ec5 sb/intel/lynxpoint: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together
isn't useful. First of all, inline `pch_is_lp` to return a constant.
This allows the compiler to optimize out unused code, which results in
smaller executables. For the Asrock B85M Pro4, it's about 2.5 KiB less.

Subsequent commits will further split the southbridge code.

Change-Id: Iba904acf64096478d1b76ffd05a076f0203502f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45047
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:07:04 +00:00
Angel Pons 78c615c332 mb/ocp/deltalake: Drop redundant `select FSP_CAR`
This is selected by Xeon SP Kconfig already.

Change-Id: If1ef7f86b27d7be74912c9ad1f9c1efbda6233e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-09-14 07:06:40 +00:00
Jonathan Zhang 9366885a42 soc/intel/xeon_sp/cpx: display FSP_PREV_BOOT_ERR_SRC_HOB
Before MRC code execution, FSP interrogates EMCA MSR registers and other
registers to see if there are fatal errors happened during previous boot
session. If there are, error records are saved into
FSP_PREV_BOOT_ERR_SRC_HOB.

When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means
the HOB does not contain any valid error record.

TESTED=Injects MCE error through cscript, reboot into OS, check boot log:
0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION
        5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID
================ PREV_BOOT_ERR_SRC HOB DATA ================
hob: 0x75904d88, Length: 0x42
         MCBANK ERR INFO:
                 Segment: 0, Socket: 0, ApicId: 0x0
                 McBankNum: 0x3
                 McBankStatus: 0xfe00000000800400
                 McBankAddr: 0xf0ff
                 McBankMisc: 0xfffffff0
         MCBANK ERR INFO:
                 Segment: 0, Socket: 0, ApicId: 0x0
                 McBankNum: 0x4
                 McBankStatus: 0xfe00000000800400
                 McBankAddr: 0xfff0
                 McBankMisc: 0xfffffff0
0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00  B...............
0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00  ................
0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00  ................
0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00  ................
0x75904dc8: 00 00

Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:05:49 +00:00
Jonathan Zhang 7f4395f40e src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating
error status registered (such as MCA MSRs) to list fatal errors happened
during the previous boot session.

The header file supports 3 different error source types. CPX-SP FSP
supports only McBankType.

Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:05:41 +00:00
Jacob Garber 07201d7a0f coreinfo: Use SPDX license identifiers
- Remove copyright notices and add authors to AUTHORS
- Use SPDX license identifiers for all files
- Add coreinfo to the license header lint

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:05:27 +00:00
Caveh Jalali 3b616e4bde mb/google/volteer: Fix GPP_E12 definition
GPP_E12 should not be defined in the baseboard as its use is
determined by the variant. For legacy reasons, we still have GPP_E12
defined in early_gpio but should not. Malefor and volteer* have the
same GPP_E12 definition, but that is a misconfiguration. I think that
was a copy-paste that slipped through the reviews.

BUG=b:157597158
TEST=volteer2 boots to the OS

Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-14 07:04:45 +00:00
David Wu a545d30831 mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius
2. Apply the DPTF parameters received from the thermal team.

BUG=b:167523658
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:04:34 +00:00
Tim Wawrzynczak a5cb5649fb mb/google/volteer: Refactor baseboard devicetree
Clean up the DPTF section of the baseboard devicetree; this makes
overrides simpler, as not necessarily all of the fields need to be
overridden.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:04:28 +00:00
Sumeet R Pawnikar 426e07aaf2 mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20W
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.

BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system

Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:04:07 +00:00
Anil Kumar 033038fd48 soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

Bug=None
Branch=None
Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:03:47 +00:00
John Zhao 623da4bc5d mb/google/volteer: Add error handling
Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.

Found-by: Coverity CID 1432491
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:03:33 +00:00