Commit Graph

5011 Commits

Author SHA1 Message Date
Stefan Reinauer 95bf86be34 Remove some warnings. For code that is called from the mainboard romstage.c
files using prototypes is the way to go I think. It would make our life a lot
easier should we ever decide to move (some mainboards) over to not #include
all those .c files in romstage.c anymore.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 20:30:47 +00:00
Stefan Reinauer 2eac9d496d Remove some more warnings. The code is only used by functions protected by the
same preprocessor check

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 20:28:35 +00:00
Stefan Reinauer c8873ce2a0 get rid of some more warnings..
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 19:21:01 +00:00
Stefan Reinauer a8d11a2032 fix compilation of mtarvon
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 17:50:53 +00:00
Stefan Reinauer a2f6a9095c Doesn't need to be a warning.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 17:46:16 +00:00
Stefan Reinauer 9ec3d38130 drop extra pci access functions. these are exact copies of romcc_io.h.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 17:44:39 +00:00
Myles Watson ad894c5449 Get rid of a few more warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30 17:11:03 +00:00
Myles Watson 636d924425 Enable the cache before initializing the processor name, like model_10 does.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 15:00:18 +00:00
Patrick Georgi 9ebd65d77f More "prepare"-dependencies we don't need anymore
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 09:23:33 +00:00
Patrick Georgi 25fc5ffd92 Force mkdir before resolving any make rules.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 09:19:47 +00:00
Anders Jenbo 771b0e4228 Enable 440BX NB to use large memory modules
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 08:45:30 +00:00
Stefan Reinauer 14e2277962 Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 06:56:47 +00:00
Anders Jenbo 0e1e8065e3 Remove some additional white space to make it look nicer in nano
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 06:35:31 +00:00
Myles Watson b333718e90 I meant SSE. Reported by Dustin Harrison.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 13:33:23 +00:00
Myles Watson 03a5d802ff Enable SSE2 for ep80579. Reported by Dustin Harrison.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 13:27:35 +00:00
Zheng Bao 12fa159451 For the mainboard with AMD Family 10, if we make clean and make again,
it will fail. why?

After make clean, .c files created by iasl are still left in the build
folder, it will match the rule of
	$(obj)/%.o: $(obj)/%.c $(obj)/config.h
		@printf "    CC         $(subst $(obj)/,,$(@))\n"
		$(CC) -MMD $(CFLAGS) -c -o $@ $<
it will miss the rule which should be applied.
	define objs_asl_template
	       ....

So we move the .c file back to .hex (or other suffix? or delete?).
This patch will work after make distclean, otherwise nobody will rename
the .c.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 12:27:18 +00:00
Stefan Reinauer 607cdf62b6 fix a bug in pcibios check.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 12:08:51 +00:00
Patrick Georgi 79255fcdb3 Set success flag in cx700 int15 handler
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 06:59:07 +00:00
Stefan Reinauer d2759fff55 cx700 int15 handler rework. Int15 handler needs to provide the
correct ram clock to the vga bios or there be dragons.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 21:44:33 +00:00
Stefan Reinauer e08c29e0e7 a single place for the romstage stack for copy_and_run.
geode lx and amd opteron don't use this yet.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 21:43:29 +00:00
Stefan Reinauer 5f5436f935 drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h"
(which could at some time hold global post code definitions, too)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 20:42:02 +00:00
Rudolf Marek 53b0b50dc8 Fix the the build of r5494 on Asus A8V-E SE. The K8M890 and K8T890
were not treated separately until now. Fix it. Hope self ack is OK,
compiled tested locally.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 20:24:09 +00:00
Stefan Reinauer bcb8c97af9 try to unify timing initialization across those boards that need it...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 18:06:32 +00:00
Patrick Georgi 14b62da01d Only do complete VGA init if a VGABIOS was found and installed.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 18:05:42 +00:00
Rudolf Marek a3c10acaac Following patch changes the K8M890 VGA handling. It reverts the framebuffer size
to option based (similar what Uwe did) and also it uses GFXUMA to handle the
high_tables_start offset from memory top.

To satisfy the CMOS option users (Hi, libv!  ;)  I added also a possibility to do
that through CMOS.

Fixed printks to match the new style.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 15:21:18 +00:00
Stefan Reinauer 467a065384 no warnings days.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 14:37:18 +00:00
Stefan Reinauer d55e26f1b1 zero warnings days
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 13:54:30 +00:00
Zheng Bao 7d2a39631e Trivial. The comment also need to modify.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 11:57:21 +00:00
Zheng Bao b6128b6d05 The device number of SATA SB700 is 0x11, while the one of SB600 is 0x12.
We changed almost associated code when we ported but overlooked some.
Some legacy of SB600 are also fixed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 11:53:09 +00:00
Stefan Reinauer 4186d8e6ea these cpus are explicitly supported by model_6bx
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-24 23:16:23 +00:00
Stefan Reinauer 714e2a1ac1 drop all duplicate copies of vgabios.c in favor
of devices/oprom/x86.c.

We have some tests on hardware. Moving RAMBASE to
1MB needs to wait a bit until C7 cache_as_ram.inc
has been adapted to cache that area or things will
become incredibly slow (1.5s boot time instead of 0.5)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-24 23:15:23 +00:00
Stefan Reinauer 0704058327 print the known cbfs types in cbfstool "usage"
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-24 21:24:06 +00:00
Zheng Bao 3173d8c94a Trivial. Fix a space to tab.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-24 07:56:32 +00:00
Rudolf Marek 7ba3c4fa09 Attached patch adds support for tinybootblock on VT8237* to decode whole flash
independent of strapping, making larger flashes work. We cannot walk anything
else than PCI bus 0 because HT is not setup yet.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 20:58:13 +00:00
Stefan Reinauer 116ec61844 zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 19:16:30 +00:00
Zheng Bao 1ad9f29886 AMD Tilapia board support as a demonstration of an AMD Fam10 DDR3 board.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 17:37:41 +00:00
Zheng Bao eedf7a646c AMD Socket ASB2 and AM3 support.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 17:35:37 +00:00
Zheng Bao eb75f652d3 DDR3 support for AMD Fam10.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 17:32:48 +00:00
Patrick Georgi fe6c2cda6e Make USE_OPTION_TABLE user visible, so it can be edited.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 08:03:14 +00:00
Bernhard M. Wiedermann 676939620a Fix AHCI mode on i82801gx. Fixes SATA hotplug on iBASE:MB899.
Signed-off-by: Bernhard M. Wiedermann <corebootbmw@lsmod.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 22:47:29 +00:00
Stefan Reinauer f75b19ac85 via epia-m now works with default x86.c instead of its own copy of vgabios.c.
Allows to drop quite a bunch of nasty code

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 18:15:32 +00:00
Stefan Reinauer 64d3baf982 zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 13:18:09 +00:00
Stefan Reinauer 4292685f5a None of the cs5536 settings in devicetree.cb were ever used and nobody noticed.
Fix it!

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 10:44:08 +00:00
Stefan Reinauer ba09695b58 fix compilation remaining geode boards
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 09:22:15 +00:00
Stefan Reinauer 4e169f9030 fix ARRAY_SIZE issue.
the gx2+5536 issue is still open, and it reveils a serious problem with the
code that was hidden under a bunch of warnings until now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 00:52:42 +00:00
Stefan Reinauer f94a97be72 oops, sorry for the last commit. This commit changes the code to distinguish
between having VSA functionality in the code, and adding a VSA image to the
ROM.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21 20:55:38 +00:00
Myles Watson 6c705110f6 Move the prototype for run_vsa.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21 20:36:09 +00:00
Stefan Reinauer 9839cbd53f * clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
  on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
  to life)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21 20:06:10 +00:00
Patrick Georgi cf036d1266 Optimize distclean and configuration.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21 06:36:20 +00:00
Pat Erley ca3548e79f This patch adds:
ICH6 Southbridge,
 82915 Series Northbridge,
 P4 6xx Series CPU

to inteltool

Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630 
installed.

Signed-off-by: Pat Erley <pat-lkml@erley.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21 06:23:19 +00:00