Commit Graph

19074 Commits

Author SHA1 Message Date
Werner Zeh 77ba882c67 siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 ms
Due to different LCD panel requirements the delay between LVDS becomes
active and the backlight is switched on needs to be increased to 500 ms.

Change-Id: I09029624469aef412141c7b46224d48557ba4af1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16875
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-05 09:30:19 +02:00
Simon Glass 52669fc4dc rockchip: spi: Set rxd sample delay when using high speed
At higher SPI bus speeds the SPI RX value is not available in time for
sampling at the normal time. Add a delay to ensure that we read the
correct data.

The value of 40ns is chosen arbitrarily. In my testing I can use a sample
delay of 1 even at 24MHz. But since it is not necessary, I have left that
case alone. It kicks in at 25MHz and up.

BUG=chrome-os-partner:56556
BRANCH=none
TEST=boot on gru and see no change at current speed

Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7
Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381311
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16707
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-04 21:39:51 +02:00
Julius Werner 7feb86b26b google/gru: Ensure correct pull resistors for special-function pins
Several of the special function pins we're using in firmware have a
pre-assigned pull-up or pull-down on power-on reset. We don't want those
to interfere with any of the signaling we're trying to do on those pins,
so this patch disables them.

Also do some house-cleaning to group the bootblock code better, and
change the setup code for all SPI and I2C buses to first initialize the
controller and then mux the pins... I assume this might be a little
safer (in case the controller peripheral has some pins in a weird state
before it gets fully initialized, we don't want to mux it through too
early).

BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.

Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560
Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/382532
Reviewed-on: https://review.coreboot.org/16711
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 21:20:44 +02:00
Julius Werner f7d519c1c7 rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ
This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock to always run at
the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our
previous tests and validation with this bug, we should probably increase
the value of the constant (that had not actually been used) to the value
that we had been incorrectly using instead (which also makes effective
SPI read times faster).

BRANCH=None
BUG=chrome-os-partner:56556
TEST=Booted Kevin.

Change-Id: Ibeb08f5fe5e984a74e3f57e60c62d4bfb644b6ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06e605a5fcb9bdf13a3d301112380633b892fd4e
Original-Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381031
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/16703
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 21:19:35 +02:00
Simon Glass 584dbf2e3a gru: Increase SPI speed to 33MHz
Increase the SPI bus speed to speed up boot time. The maximum supported
speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed,
given the clock parents.

BUG=chrome-os-partner:56556
BRANCH=none
TEST=boot on gru and see that things still work correctly. Total time
spent on reading from SPI reduces from 185ms to 141ms.

Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf
Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381313
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16708
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04 21:18:21 +02:00
Julius Werner 2768a119ce rockchip: Remove pulls for gpio_output(), clean up code
Output GPIOs should never have a pull-up or pull-down resistor attached
since they're actively driven. Since some GPIOs get initialized with a
pull at power-on reset, we should explicitly overwrite that setting.
Most other platforms do this on gpio_output, but Rockchip hadn't yet.

Also, shuffle some code around to make things cleaner and allow for
easier code reuse.

BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.

Change-Id: I1425d074ea1e90f4484e1e84a8002b057192c5f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: df5b236bfd58b172435043c1cb792b917a4ec4ab
Original-Change-Id: I044266d71ef8bd0518316ff72d829d1ca1e30f35
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/382531
Original-Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-on: https://review.coreboot.org/16710
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 21:17:37 +02:00
Douglas Anderson 1eb69b4a64 google/gru: Init the PWM pinmux after setting up the PWM
If we setup the PWM _after_ the pinmux then there's a period of time
when we're driving the PWM incorrectly.  Let's setup the regulator and
_then_ configure the pinmux.

This fixes no known bugs, but it is more correct and probably makes the
signals look better at bootup.

BRANCH=None
BUG=None
TEST=scope

Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1
Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381592
Original-Reviewed-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16700
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 21:16:34 +02:00
Julius Werner a02e4a0428 rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419
As far as I know, the Cortex-A53 cores in RK3399 are of a newer revision
that is not affected by ARM erratum 843419. If it was, the workaround
would also need to be enabled in libpayload and Chrome OS userspace,
which it currently isn't. I assume this was just incorrectly copied over
from another SoC and we can safely remove it.

BRANCH=None
BUG=chrome-os-partner:56700
TEST=Booted Kevin.

Change-Id: I5b1534c954a6d985499b481738723cabbdc07253
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4891cc866583532ee3dcb1a5ad5b81670eb0743d
Original-Change-Id: Iadb57428f8727ce0e563204723644e2c79e3007c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376363
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16702
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04 21:14:52 +02:00
Elyes HAOUAS ffcc07dbad mainboard/siemens/sitemp_g1p1: Use tabs for indents
Change-Id: Ia5ea2198cdc93822723a4fe5440d574d76cb4de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16847
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 19:17:53 +02:00
Elyes HAOUAS 7db506c3dd src/northbridge: Remove unnecessary whitespace
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 19:15:55 +02:00
Martin Roth fb190ed764 util/release: Update genrelnotes.script to the latest version
Internal changes:
- Fix shellcheck issues.
- Add some help text and update section header text.
- Reorder sections to try to get better estimates of what the commits
were mainly touching.
- Start making the script slightly less coreboot-centric.
- Don't print git errors.

Changes in output:
- Find new and deleted CPUs, SOCs, northbridges, southbridges, and SIOs.
- Show new users.
- Show before and after commit count for all authors.

Change-Id: I9858436f9458b2859a91273a525901df34796df4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16848
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-04 19:10:52 +02:00
Arthur Heymans 58afca4a1a nb/gm45: allow use of 352M preallocated ram for igd
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family"
mention the possibility of having 352M ram preallocated for the
integrated graphic device. This only worked fine if the amount of ram in
the system was 3GB or less. When 4G or more is installed, memory is
remapped to create a 1GB large pci mmio hole which is not enough and
creates conflicts when 352M vram is used.

This patch increases the pci mmio hole size on Lenovo x200 to allow
352M vram to work.

TEST: build and flash on target with 4GB ram or more, use nvramtool to
set gfx_uma_size to 352M and reboot.

Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16831
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 19:03:28 +02:00
Elyes HAOUAS 5e0242b0ec src/cpu: Remove whitespace after sizeof
Change-Id: I30b911a8444529653c8ea4a736a902143fe7ab20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16864
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-04 14:32:38 +02:00
Elyes HAOUAS 0d4b11a4f8 src/northbridge: Remove whitespace after sizeof
Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16863
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-10-04 14:31:53 +02:00
Elyes HAOUAS 18cd8a64a4 src/southbridge: Remove unnecessary semicolon
Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 14:30:52 +02:00
Elyes HAOUAS 5c22825c19 mainboard/amd/torpedo: Improve code formatting
Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 14:30:04 +02:00
Elyes HAOUAS 738a3b043e src/mainboard: Remove unnecessary semicolon
Change-Id: Iab0c7c470a3105b5df7b6b74aebdd1329e7f93ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16859
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-10-04 14:29:40 +02:00
Kyösti Mälkki 38ab6f2839 samsung/lumpy: Swap SPD assignments
On-board memory is on channel 1.
This fixes native raminit with 4GiB SO-DIMM installed.

Change-Id: If1b94e050d7e8d0dbd349c0415a182730aa5fa90
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/16845
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04 14:28:14 +02:00
Martin Roth a7d0027083 Revert "util/lint/kconfig_lint: change warning levels and text"
This reverts commit dfdb0733a6a71b11d15006dafc13841e84fab7cd.

Change-Id: I91bf5e42f4ac241f544742ce161bae651f9f9947
Reviewed-on: https://review.coreboot.org/16868
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-10-03 23:13:09 +02:00
Martin Roth 6d6c00a502 google/gale: Remove #ifdef of Kconfig bool symbol
Kconfig symbols of type bool are ALWAYS defined, so this code was
always being included and run, which isn't what the author wanted.

Change to use IS_ENABLED(), and a regular if() instead of an #ifdef.

Change-Id: I72623fa27e47980c602135f4b73f371c7f50139b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-03 22:53:44 +02:00
Martin Roth 8bc8be4d0e util/lint/kconfig_lint: change warning levels and text
- Add an exception for MAINBOARD_POWER_ON_AFTER_POWER_FAIL when checking
- With those exceptions set, we don't have anymore #define or #ifdef
warnings, so turn them to errors so no more can be pushed.
- Change the definition of an unused symbol from a warning to a note.
There are times when unused symbols are expected.
- Upgrade the warning for loading Kconfig files multiple times from
a warning to an error.

Change-Id: I6dcb06d4f0b099d5ccaf7643e72dd790719bdf58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16840
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-03 22:05:54 +02:00
Martin Roth fa95625867 util/lint/kconfig_lint: Check default types
The type of the default value wasn't being checked to make sure that it
matched the type of the Kconfig symbol.

This makes sure that the symbol is being set to either a reasonable
looking value or to another Kconfig symbol.

Change-Id: Ia01bd2d8b387f319d29f0a005d55cb8e20cd3853
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-03 22:05:37 +02:00
Martin Roth 3d6db6f0fa google/gale/Kconfig: Change wording of Kconfig option
Everybody knows WHAT they're supposed to do with options, so the text
"Pick this" or "Select to" are redundant.

Change-Id: I327c5be755373e99ca0738593bd78e1084d4d492
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-03 22:05:10 +02:00
Elyes HAOUAS 74295c1fb1 mainboard/packardbell/ms2290: Use tabs for indents
Change-Id: I1559a2541a93a9969ac68708a04f0468790feb69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16844
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02 19:09:45 +02:00
Elyes HAOUAS e5f3611ce3 mainboard/via/vt8454c: Improve code formatting
Change-Id: Ida10672380f6dffec0daf0073f25f6badfcd83eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16843
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02 19:09:28 +02:00
Elyes HAOUAS 5b005196ea mainboard/apple/macbookair4_2: Use tabs for indents
Change-Id: I2714553e2521f8178538755e3cfadec5c1fc6b12
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16842
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02 19:09:07 +02:00
Martin Roth c59cc22e57 vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex
The AGESA_BINARY_PI_LOCATION Kconfig symbol was declared as a string.
Change it to a hex value.

Change-Id: Ifd87b6c8dfcdf950aea9b15a6fea45bb72e8b4e9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16835
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02 19:08:33 +02:00
Martin Roth 3b87812f00 Kconfig: Update default hex values to start with 0x
Kconfig hex values don't need to be in quotes, and should start with
'0x'.  If the default value isn't set this way, Kconfig will add the
0x to the start, and the entry can be added unnecessarily to the
defconfig since it's "different" than what was set by the default.

A check for this has been added to the Kconfig lint tool.

Change-Id: I86f37340682771700011b6285e4b4af41b7e9968
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16834
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02 19:08:15 +02:00
Furquan Shaikh cc3365a039 TPM2: Fill in empty tlcl_resume function in TPM2 tlcl
On resume, TPM2_Starup(STATE) command needs to be sent to the TPM. This
ensures that TPM restores the state saved at last Shutdown(STATE).

Since tlcl_resume and tlcl_startup both use the same sequence for
sending startup command with different arguments, add a common function
that can be used by both.

BUG=chrome-os-partner:58043
BRANCH=None
TEST=Verified that on resume coreboot no longer complains about index
read for 0x1007. Return value is 0 as expected.

Change-Id: Ib8640acc9cc9cdb3ba5d40e0ccee5ca7d67fa645
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16832
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-02 19:07:29 +02:00
Arthur Heymans 5db043f0d6 apple/imac52: add mainboard
Add Imac5,2 based on macbook2,1 port.

Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02 19:06:55 +02:00
Nico Huber a90c7859d9 mb/kontron/ktqm77: Let suspend LED flash slowly in S3/S4
Change-Id: Idb37abea01831631aadba66ecd42bc7df03aa857
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16727
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 22:30:55 +02:00
Nico Huber bbda950e13 sio/winbond/w83627dhg: Add ACPI function to control suspend LED
Change-Id: Ie2062672233141b6f34625e59cbb50238be0b5fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 22:30:38 +02:00
Teo Boon Tiong 2fc06c8203 soc/intel/skylake: Add config option for Skylake-H Sku support
Change-Id: Ia9c1c065f20bf2b37afc7485ef8df3abd35e2f14
Reviewed-on: https://review.coreboot.org/16607
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 22:30:02 +02:00
Teo Boon Tiong f95daa510d superio/nuvoton: Add back Nuvoton NCT6776 support
Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776),
removing the code as no other mainboard uses it.

The board Intel Saddle Brook uses this device, so add the
code back with minor adaptations.

Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/16519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 22:29:18 +02:00
Martin Roth 3674c8240d soc/intel/apollolake: Try to update BSP microcode from cbfs
The microcode for the BSP gets loaded early from the fit table, but in
case we have newer microcode in cbfs, try to load it again from cbfs.

BUG=chrome-os-partner:53013
TEST=Boot and verify that microcode tries to load into the BSP.

Change-Id: Ifd6c78d7b0eec333b79e0fe5cb6a81981b078f5d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16829
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-01 22:28:57 +02:00
Antonello Dettori 6b63990602 southbridge/broadcom/bcm5785: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/broadcom/bcm5785.

Change-Id: I091b07439ff918efa52cf8f8270484131fd0cec5
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16690
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 17:39:54 +02:00
Antonello Dettori ca159f0fb3 northbridge/via/cn700: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/via/cn700.

Change-Id: Ib7761697daad3c459f3568e5158f925199bcd919
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16689
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 17:39:33 +02:00
Antonello Dettori 76e8c00be6 cpu/amd/model_fxx: transition away from device_t
Replace the use of the old device_t definition inside
cpu/amd/model_fxx.

Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16437
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 17:39:05 +02:00
Antonello Dettori 97c460a2d1 biostar/am1ml: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/biostar/am1ml.

Change-Id: Iba2fff5617c62152355b54e446517ad36108aa31
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16688
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-01 17:38:50 +02:00
Sumeet Pawnikar 62a193899c mainboard/google/reef: Update DPTF policy temp. values for CPU
This patch increases the CPU specific passive temp. trip point
and critical temp. trip point value for DPTF policy.

BUG=chrome-os-partner:57903
TEST=Built, booted on reef and verified this passive and
critical temp. trip points with heavy workload.

Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16766
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
2016-10-01 17:38:16 +02:00
Aaron Durbin c6452bb8c5 mainboard/google/reef: unconditionally set MAINBOARD_FAMILY
For all mainboard variants use the "Google_Reef" family by default
which is populated in SMBIOS tables. A variant can provide their own
value if needed, but "Google_Reef" can reside as the family without
having to add conditions for each variant when MAINBOARD_FAMILY
have to be overridden.

BUG=chrome-os-partner:56677

Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16813
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-10-01 17:37:43 +02:00
Elyes HAOUAS 08449eb583 mainboard/amd/serengeti_cheetah: Use tabs for indents
Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16817
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-01 09:11:10 +02:00
Elyes HAOUAS 75b2237473 mainboard/*/*/*/usb.asl: Use tabs for indents
Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16824
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:38:34 +02:00
Elyes HAOUAS 728273eebf mainboard/gigabyte/m57sli/romstage.c: Use tabs for indents
Change-Id: Ib439e5d96543790d17934bd477af62d39a5958b6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16815
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:35:47 +02:00
Elyes HAOUAS b4d8257dff mainboard/jetway/j7f2: Use tabs for indents
Change-Id: Id97981a05ce4af371c765c6950ed504557b0a584
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:35:24 +02:00
Elyes HAOUAS c3d490cc24 mainboard/winent/mb6047: Use tabs for indents
Change-Id: Iaf5ad440cfc2bbe08ea9f6c545e5e314645c8893
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16823
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:35:03 +02:00
Elyes HAOUAS bbcb8bc971 mainboard/kontron/ktqm77: Use tabs for indents
Change-Id: I3040dc9a2534a77087805ee61c4f91d1bdb4d509
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16822
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:34:45 +02:00
Elyes HAOUAS 075ff736f6 mainboard/digitallogic/msm800sev: Use tabs for indents
Change-Id: I39ad6606869f059b2ef0c45d6741b844b3791655
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16821
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:34:28 +02:00
Elyes HAOUAS dae8fe747c mainboard/gigabyte/ga-b75m-d3v: Use tabs for indents
Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16816
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:33:51 +02:00
Elyes HAOUAS cb6b120e93 mainboard/gigabyte/ga-b75m-d3h: Use tabs for indents
Change-Id: I038e5cea654d1760ddb2c403c651d8f75e021251
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:33:28 +02:00