Commit Graph

8200 Commits

Author SHA1 Message Date
Steven Sherk d9de6c4f0e Add new superio device
- Added in new support for Nuvoton NCT5104D LPC device.

Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3072
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12 00:37:34 +02:00
Paul Menzel 6a1210901d AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment
Reading the paste of code in a message to the mailing list [1],
a typo was spotted and found in one more place.

    $ git grep egnoring
    src/southbridge/amd/rs780/cmn.c:                         * egnoring the reversal case
    src/southbridge/amd/sr5650/sr5650.c:                     * egnoring the reversal case

These typos are there since when the code was committed and are
now corrected.

[1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html

Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3062
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11 22:04:20 +02:00
Mike Loptien 573a1d6fa8 Persimmon/Fam14/SB800 DSDT: Split into common areas
Split the Persimmon DSDT into common code areas.
For example, split the Southbridge specific code into
the Southbridge directory and CPU specific code into
the CPU directory.  Also adding the superio.asl file
to the Persimmon DSDT tree. This file is empty for
the moment but will be necessary in the future.  I have
also emptied the thermal.asl file in the mainboard
directory because it does not seem to perform as
intended (fan control does not change when it is
brought back into the code base) and it has been
inside a '#if 0' statement for a long time.  Removing
it until it is decided that it is actually necessary.

This change was verified in three different ways:
	1. Visual comparison of the compiled DSDT pulled from the
	Persimmon after booting into Linux using the ACPI tools
	acpidump, acpixtract, and iasl.  The comparison was done
	between the DSDT before and after doing the split work.

	This test is somewhat difficult considering the expanse
	of the changes.  Blocks of code have been moved, and
	others changed.

	2. Linux logs were dumped before and after the DSDT split.
	Logs dumped and compared include dmesg and lspci -tv.
	Neither log changed significantly between the two compare
	points.

	3. The test suite FWTS was run on the Coreboot build both
	before and after doing the DSDT split with the command
	'sudo fwts -b -P -u'.  The flag -b specifies all batch jobs,
	-P specifies all power tests, and -u specifies utilities.
	Interactive jobs were not run as most of them consist of
	laptop checks.  Again, there were no significant changes
	between the two endpoints.

These tests lead me to believe that there was no change in
the functionality of the ACPI tables apart from what is
known and expected.

This patch is the first of a series of patches to split the DSDT.
The ASRock patch was merged before this one and breaks the ASROCK
E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
Please be aware of this dependency when pulling these patches.
Other patches that depend on this patch are
'AMD Fam14: Split out the AMD Fam14 DSDT'
(http://review.coreboot.org/#/c/3051/)
and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
(http://review.coreboot.org/#/c/3052/)

Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11 21:48:27 +02:00
Paul Menzel 109a710743 libpayload: storage.c: Fix typo in st*orage in comment
Reading commit »libpayload: New AHCI, ATA and ATAPI drivers«
(1f6bd94f) [1], the spelling error was found and is now fixed.

[1] http://review.coreboot.org/1622

Change-Id: Id418bcb99c1a9a400a49fc04078e465bd0908074
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3071
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-11 18:09:20 +02:00
Gabe Black 1a5c9cd33b Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage.
We need these to be inputs so they can be read when populating the coreboot
tables. It seems like a good idea to do this early to ensure that the input
gate capacitance has had a chance to charge, and if we decide to use
actually use that information during the ROM stage to do earlier RW
firmware selection.

It is not guarded by a ChromeOS config variable because those lines are
always intended to be input GPIOs, regardless of whether we're running
ChromeOS or not.

Change-Id: Id76008931b5081253737c6676980a1bdb476ac09
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3067
Tested-by: build bot (Jenkins)
2013-04-11 04:13:49 +02:00
Gabe Black fe3b024a44 Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number.
Change-Id: I34097f878291367b28962048190e11ccaacfc514
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3066
Tested-by: build bot (Jenkins)
2013-04-11 04:13:28 +02:00
Gabe Black 514f202939 ARM: Unmask aborts very early in the bootblock.
It's better to recognize aborts when they occur than to mask them to
discover them later without knowing where they actually came from.

Change-Id: Ic8f5321415f411afac94b5ef9dd440790df6d82c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3065
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-11 04:12:16 +02:00
Mike Loptien 8d80a3fb9f ASRock DSDT: Split the ASRock DSDT
This is the same split as was done on the Persimmon.

Change-Id: I25bd63f23417b7926232f07eaaa7917170af9d60
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3050
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-11 00:53:17 +02:00
Ronald G. Minnich b48605da20 Exynos5250: Use new chip settings for the cpu
Properly use the chip settings when configuring the CPU,
at this point being purely graphics.

Change-Id: I9bc2d32c1037653837937b314e4041abc0024835
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3054
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-11 00:11:51 +02:00
Patrick Georgi 1fde22c54c siemens/sitemp_g1p1: Make ACPI report the right mmconf region
ACPI reported the entire space between top-of-memory and some
(relatively) arbitrary limit as useful for MMIO. Unfortunately
the HyperTransport configuration disagreed. Make them match up.

Other boards are not affected since they don't report any region
for that purpose at all (it seems).

Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:40:49 +02:00
Ronald G. Minnich 7576f2515e GOOGLE/SNOW: add edp support to ramstage
Add basic edp support to the ramstage. Not working.

Change-Id: I15086e03417edca7426c214e67b51719d8ed9341
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3055
Tested-by: build bot (Jenkins)
2013-04-10 17:37:25 +02:00
David Hendricks 765ff76d8f [2/2] tps65090: re-factor for coreboot
This does basic re-factoring to fit the driver into coreboot.

Change-Id: Id5f8c12a73ec37ddd545d50b3e8e9b3012657db1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3061
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:34:19 +02:00
David Hendricks 6e877ec63e [1/2] initial import of TI TPS65090
This imports TPS65090 PMIC from u-boot and adds/updates Makefiles
and Kconfig files. The follow-up patch will re-factor the code.

Change-Id: Ic9e43b9665ddf7f55feae8fa17fbf3d2d5f4756d
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3060
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:33:13 +02:00
Ronald G. Minnich 767edfc542 GOOGLE/SNOW: clean up the device tree
This is a simpler device tree that is also more correct,
and has graphics settings as well.

Change-Id: I342d8be7dddb76e6992876c73f5c625c926977d3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3053
Tested-by: build bot (Jenkins)
2013-04-10 17:31:05 +02:00
Ronald G. Minnich 798f6649a9 exynos5-common: Enable fimd_bypass and minor cleanup
Basic cleanup, this code still does not work.

Change-Id: I84ed9f08fd04cd8eb74cd860e0775d8c602f42d6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3049
Tested-by: build bot (Jenkins)
2013-04-10 17:30:30 +02:00
David Hendricks 086b369dfc armv7: replace read/write macros with inlines
This enables type checking for safety as to help prevent errors like
http://review.coreboot.org/#/c/3038/ . Now compilation fails if the
wrong type is passed into readb/readw/readl/writeb/writew/writel
or other macros in io.h.

This also deprecates readw/writew. The previous definition was 16-bits
which is incorrect since wordsize on ARMv7 is 32-bits and there was
only 1 instance of writew (#if 0'd anyway). Going forward we should
always use read{8,16,32} and write{8,16,32} where N specifies the
exact length rather than relying on ambiguous definition of wordsize.

Since many macros relied on __raw_*, which were basically the same
(minus data memory barrier instructions), this patch also gets rid
of __raw_*. There were parts of the code which ended up using these
macros consecutively, for example:
	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);

In such cases the safe versions of readl() and writel() should be
used anyway.

Note: This also fixes two dubious casts as to avoid breaking
compilation.

Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3045
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 00:04:57 +02:00
David Hendricks b959fbb87a exynos5: Re-factor I2C code
This re-factors the Exynos5 I2C code to be simpler and use the
new API, and updates users accordingly.

- i2c_read() and i2c_write() functions updated to take bus number
  as an argument.

- Get rid of the EEPROM_ADDR_OVERFLOW stuff in i2c_read() and
  i2c_write(). If a chip needs special handling we should take care
  of it elsewhere, not in every low-level i2c driver.

- All the confusing bus config functions eliminated. No more
  i2c_set_early_config() or i2c_set_bus() or i2c_get_bus(). All this
  is handled automatically when the caller does a transaction and
  specifies the desired bus number.

- i2c_probe() eliminated. We're not a command-line utility.

- Let the compiler place static variables automatically. We don't need
  any of this fancy manual data placement.

- Remove dead code while we're at it. This stuff was ported early on
  and much of it was left commented out in case we needed it. Some
  also includes nested macros which caused gcc to complain.

- Clean up #includes (no more common.h, woohoo!), replace debug() with
  printk().

Change-Id: I8e1f974ea4c6c7db9f33b77bbc4fb16008ed0d2a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3044
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 00:01:02 +02:00
David Hendricks cfb73607be replace device/i2c.h with simpler version
The existing header was imported along with the Exynos code and left
mostly unchanged. This is the first patch in a series intended to
replace the imported u-boot I2C API with a much simpler and cleaner
interface:

- We only need to expose i2c_read() and i2c_write() in our public API.
  Everything else is board/chip-dependent and should remain hidden
  away.

- i2c_read and i2c_write functions will take bus number as an arg
  and we'll eliminate i2c_get_bus and i2c_set_bus. Those are prone to
  error and end up cluttering the code since the user needs to save
  the old bus number, set the new one, do the read/write, and restore
  the old value (3 added steps to do a simple transaction).

- Stop setting default values for board-specific things like SPD
  and RTC bus numbers (as if we always have an SPD or RTC on I2C).

- Death to all the trivial inline wrappers. And in case there was any
  doubt, we really don't care about the MPC8xx. Though if we did then
  we would not pollute the public API with its idiosyncrasies.

Change-Id: I4410a3c82ed5a6b2e80e3d8c0163464a9ca7c3b0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3043
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09 23:59:34 +02:00
Jens Rottmann 4026b034f1 FrontRunner/Toucan-AF: boards will be renamed to fit ADLINK scheme
Originally developed by LiPPERT and after the acquisition marketed as
'LiPPERT by ADLINK', the plan is now to streamline both boards into the
ADLINK naming scheme.  But AFAIK a few have already been sold and as of
this writing the website still advertises the old names.  And in any case
the veteran LX products will continue to be sold by ADLINK under their
original names.

So create CONFIG_VENDOR_ADLINK, currently only telling users to look under
LiPPERT (however any future boards will be added here).

Further add an explanation to CONFIG_VENDOR_LIPPERT, and in the Mainboard
model selection show both names.

Change-Id: Iaafa88533ef4cce33243293c3d55754e7e93d003
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/3046
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09 23:56:14 +02:00
Vladimir Serbinenko f4a0d019fa util/cbmem: Don't output trailing garbage for cbmemc
Current code outputs the whole cbmemc buffer even if only part of
it is really used. Fix it to output only the used part and notify
the user if the buffer was too small for the required data.

Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2991
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09 23:52:36 +02:00
Stefan Reinauer 33e83caff5 cbfstool: completely initialize input and output streams
The LZMA glue code in cbfstool was recently rewritten from C++
to plain C code in:

        commit aa3f7ba36e
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Thu Mar 28 16:51:45 2013 -0700

            cbfstool: Replace C++ code with C code

            Reviewed-on: http://review.coreboot.org/3010

In the progress of doing so, the stream position for the
input stream and output stream was not reset properly. This
would cause LZMA producing corrupt data when running the
compression function multiple times.

Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3040
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 21:36:37 +02:00
Stefan Reinauer bb2cc71480 Fix read_option invocation in uart8250mem.c
read_option was unified between ramstage and romstage a while ago.
However, it seems some invocations were not fixed accordingly.
This patch switches uart8250mem.c to use the new scheme.

Change-Id: I03cef4f6ee9188a6412c61d7ed34fbaff808a32b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3033
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 21:36:01 +02:00
Stefan Reinauer 84463efb94 Fix compilation when coverage debugging is enabled
With CONFIG_DEBUG_COVERAGE enabled, the build currently fails with

src/lib/gcov-glue.c: In function 'fseek':
src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format]
src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format]

Change-Id: Iddaa601748c210d9dad06ae9dab2a3deaa635b2c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3032
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 21:35:26 +02:00
Gabe Black 9e8af58263 libpayload: Handle multifunction bridge devices better.
This change modifies the code in libpayload that scans the PCI hierarchy for
USB controllers. Previously, if a devices primary function (function 0) was a
bridge, then none of the other functions, if any, would be looked at. If one
of the other functions was a bridge, that wouldn't be handled either. The new
version looks at each function that's present no matter what, and if it
discovers that it's a bridge it scans the other side.

Change-Id: I37f269a4fe505fd32d9594e2daf17ddd78609c15
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2517
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-08 20:27:46 +02:00
David Hendricks 6d0fe9cad0 armv7: specify condition code for msr instruction
This adds condition codes when using the msr instruction. Although
described as "optional" in the Cortex-A series programmer's guide,
our experience with using the msr instruction in the payload suggests
that the condition code is not optional and that this only worked
in coreboot (and u-boot) because the processor comes up in SVC32 mode.

(credit to Gabe Black for finding this, I'm only uploading the patch)

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b
Reviewed-on: http://review.coreboot.org/3037
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 18:31:08 +02:00
David Hendricks c7e5d79842 exynos5250: add missing address-of operator in UART driver
This adds a missing address-of operator. This was a subtle bug that
didn't seem to cause problems at first since the serial console
appeared to work. However it caused an imprecise external abort which
became apparent later on when aborts were unmasked in the kernel via
the CPSR_A bit.

(credit goes to Gabe Black for finding this)
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I80a33b147d92d559fa8fefbe7d5642235deb9aea
Reviewed-on: http://review.coreboot.org/3038
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 18:30:03 +02:00
Stefan Tauner 0c8b7d1ac2 inteltool: remove unused file descriptor variable and ifdefs
Change-Id: I6a119b1f362f481914377e8d14c713159f895130
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3030
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 18:17:59 +02:00
David Hendricks db9eaf4cb2 snow/exynos5250: move board-specific power stuff to mainboard dir
This moves highly board-specific code out from the Exynos5250
power_init() into Snow's romstage.c. There's no reason the CPU-
specific code should care about which PMIC we are using and
which bus it is on.

Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3034
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 18:16:06 +02:00
Ronald G. Minnich 161ccc76ea exynos5250: add a chip.h file for the display register settings
Display hardware is part of this SOC, and we need to be able
to set certain variables in devicetree.cb. This chip file
contains the initial things we think we need to set.

Change-Id: I16f2d4228c87116dbeb53a3c9f3f359a6444f552
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3031
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-04-06 08:17:46 +02:00
Aaron Durbin 6ccb1abfd4 mtrr: add rom caching comment about hyperthreads
Explicitly call out the effects of hyperthreads running the
MTRR code and its impact on the enablement of ROM caching.

Change-Id: I14b8f3fdc112340b8f483f2e554c5680576a8a7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3018
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 21:57:38 +02:00
Stefan Tauner 0dc775e894 inteltool: use inttypes for prints in memory.c
This fixes at least one warning on my machine where "llx" is replaced by PRIx64.

Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:21:35 +02:00
Ronald G. Minnich ce801b55fa exynos5-common: get rid of displayport trial code
This was a first pass at display port support, we have
realized that it was ultimately a bad path. The display
hardware is intimately tied into a specific cpu and
mainboard combination, and the code has to be elsewhere.

The devicetree formatting is ugly, but it matters not:
it's changing soon.

Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:17:35 +02:00
Paul Menzel 5f3754e66d inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
Cppcheck [1], a static code analysis tool, warns about the
following.

    $ cppcheck --version
    Cppcheck 1.59
    $ cppcheck --enable=all .
    […]
    Checking cpu.c...
    [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
    [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
    […]

And indeed, `core` is an unsigned integer and `man 3 printf` tells
the following about conversion specifiers.

       d, i   The int argument is converted to signed decimal notation. […]

       o, u, x, X
              The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or  unsigned  hexadecimal  (x  and  X)
              notation.

So use `u` and Cppcheck does not complain anymore.

[1] http://cppcheck.sourceforge.net/

Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:17:03 +02:00
Paul Menzel 72ef8881a3 libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line
Nico Huber spotted [1], that commit (4d6ab4e2) [1] updating
superiotools’s `README` with the Git command line

    superiotool: Update README with Git repository URL and directory location

missed, that after `git clone` one sitll has to change into
the cloned directory.

So prepend the path with `coreboot/` to fix that. The same error
happened in the commit (e1ea5151) for libpayload [2]

    libpayload: Update README with Git repository URL and directory location

and is fixed in this patch too.

[1] http://review.coreboot.org/#/c/3019/
[2] http://review.coreboot.org/2228

Change-Id: Ib6e8b678af6276556a40ccfd52ae35ca7e674455
Reported-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3021
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04 17:22:15 +02:00
Paul Menzel 3402a7fa70 inteltool: Cast to `intptr_t` instead of `uint64_t`
When building inteltool under x86-32, the following warnings are
shown.

    $ gcc --version
    gcc-4.7.real (Debian 4.7.2-15) 4.7.2
    Copyright (C) 2012 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    $ make
    […]
    amb.c: In function ‘amb_read_config32’:
    amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config16’:
    amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config8’:
    amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    […]

Nico Huber commented the following [1].

    I don't see those warnings because I build for x86-64. I guess
    they could be fixed by casting to `ptrdiff_t` (from stddef.h)
    instead of `uint64_t`.

And indeed, using `ptrdiff_t` fixes the warning. But as Stefan
Reinauer commented in [2], `intptr_t` is more appropriate as this
is just a pointer and no pointer difference.

So `intptr_t` is taken, which fixes these issues warned about too.

These warnings were introduced in commit »inteltool: Add support for
dumping AMB registers« (4b7b320f) [3].

[1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG
[2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c
[3] http://review.coreboot.org/525

Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3002
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04 14:24:25 +02:00
Kyösti Mälkki 190011e47c AMD: Drop six copies of wrmsr_amd and rdmsr_amd
Based on comments in cpu/x86/msr.h for wrmsr/rdmsr, and for symmetry,
I have added __attribute__((always_inline)) for these.

Change-Id: Ia0a34c15241f9fbc8c78763386028ddcbe6690b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2898
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-04 04:52:18 +02:00
Paul Menzel 4d6ab4e2ae superiotool: Update README with Git repository URL and directory location
Change-Id: I36d980cea5ca9cc67262dba809441091757e1fb5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3019
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-04 04:50:00 +02:00
Paul Menzel 5b5cf3d610 AMD GX1: Remove useless copied header file `northbridge.h`
This was there since the beginning

    commit d24d6993b6
    Author: arch import user (historical) <svn@openbios.org>
    Date:   Wed Jul 6 17:06:46 2005 +0000

        Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
        Creator:  Hamish Guthrie <hamish@prodigi.ch>

        Added AMD GX1 northbridge and cs5530 Southbridge

but blindly copied from Intel 440 BX and is not used anywhere.

Thanks to Idwer Vollering for spotting this.

Change-Id: I38b3d3feb25966c3aa382994d323e59c3f3c9e6c
Reported-by: Idwer Vollering
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3020
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2013-04-04 03:26:58 +02:00
Stefan Reinauer 3c156dd98c lynxpoint: Cosmetic cleanup
src/southbridge/intel/lynxpoint/pmutil.c was committed with two
things that needed fixing.

Change-Id: Ib83343a75840aa29847b607b0275971eb8140f12
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3003
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-03 23:07:12 +02:00
Jens Rottmann 27a1be9169 Partially revert "AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`"
Commit 5d741567 added a prototype to broadcom.c to fix a warning.  This part
is fine.

It also changed mainboard.c to #include broadcom.c.  But broadcom.c is
already in Makefile.inc, now building will fail because the linker gets
broadcom_init() twice.

Undo the change to mainboard.c but keep the change to broadcom.c.

Change-Id: Ieccc098f477ffacccf4174056998034a220a9744
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/3012
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-03 19:29:30 +02:00
Aaron Durbin c6f27226a8 sandybridge: enable ROM caching
If ROM caching is selected the sandybridge chipset code will
will enable ROM caching after all other CPU threads are brought
up.

Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-03 19:26:25 +02:00
Aaron Durbin 23f50166c6 haswell: enable ROM caching
If ROM caching is selected the haswell CPU initialization code
will enable ROM caching after all other CPU threads are brought
up.

Change-Id: I75424bb75174bfeca001468c3272e6375e925122
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-03 19:26:05 +02:00
Aaron Durbin 13cc952a13 haswell: keep ROM cache enabled
The MP code on haswell was mirroring the BSPs MTRRs. In addition it
was cleaning up the ROM cache so that the MTRR register values were
the same once the OS was booted. Since the hyperthread sibling of
the BSP was going through this path the ROM cache was getting torn
down once the hyperthread was brought up.

That said, there was no differnce in observed boot time keeping the
ROM cache enabled.

Change-Id: I2a59988fcfeea9291202c961636ea761c2538837
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3008
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-03 19:25:42 +02:00
Aaron Durbin 0f0fe100cb haswell: use new interface to disable rom caching
The haswell code was using the old assumption of which MTRR
was used for the ROM cache. Now that there is an API for doing
this use it as the old assumption is no longer valid.

Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-03 19:25:17 +02:00
Paul Menzel d46161e9ea intel/microcode.h: Fix typo in comment: micr*o*code
Introduced in commit »intel microcode: split up microcode loading
stages« (98ffb426) [1].

[1] http://review.coreboot.org/2778

Change-Id: I626508b10f3998b43aaabd49853090b36f5d3eb0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2992
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-04-03 19:19:09 +02:00
Siyuan Wang 64a7ed6dfa Add PXE ROM selection to Kconfig menu
Adding a pxe rom manually is inconvenient.
With this patch, PXE ROM can be added automatically by selecting PXE_ROM in Kconfig.
I have tested this patch on AMD Parmer and Thatcher with iPXE.
iPXE would be a boot device in Seabios when pressing F12.
iPXE works well with coreboot and Seabios.

Change-Id: I2c4fc73fd9ae6c979f0af2290d410935f600e2c8
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3013
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-03 18:01:44 +02:00
Paul Menzel b81754beca ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors
Now that the ASRock E350M1 builds without any warnings, remove the
config option `WARNINGS_ARE_ERRORS` set to no by default from
the file `Kconfig` so warnings are treated as errors to prevent
code from being added in the future introducing warnings.

Change-Id: Idfecfb1434158969334a4b37972b5fc6fd76e72a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3014
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-03 17:20:03 +02:00
Paul Menzel a8db717d4a inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
When buidling inteltool with GCC, the following warning is printed.

    $ make
    […]
    gcc -O2 -g -Wall -W   -c -o memory.o memory.c
    memory.c: In function ‘print_mchbar’:
    memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat]
    […]

This was introduced in commit »inteltool: Add support for H65 Express
chipset« (c7fc4422) [1].

Address this warning, by using `%llx` instead of `%lx`.

[1] http://review.coreboot.org/1258

Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2994
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-03 11:13:29 +02:00
Stefan Reinauer aa3f7ba36e cbfstool: Replace C++ code with C code
cbfstool was using a C++ wrapper around the C written LZMA functions.
And a C wrapper around those C++ functions. Drop the mess and rewrite
the functions to be all C.

Change-Id: Ieb6645a42f19efcc857be323ed8bdfcd9f48ee7c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3010
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-03 02:35:28 +02:00
Stefan Reinauer 60a4a73fcd cbfstool: fix --machine
The help text says --machine, but the code
actually checked for --arch. Fix it!

Change-Id: Ib9bbf758b82ef070550348e897419513495f154b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3009
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-02 20:27:10 +02:00