Commit Graph

26449 Commits

Author SHA1 Message Date
Patrick Rudolph 39315985e8 Documentation: Fix markdown inline code
recommonmark doesn't know about inline code, while all other software generating
documentation is able to handle it.
Add support for inline code by adding a wrapper class around the recommonmark
parser that converts code to docutils literal blocks.

Fixes invisible inline code in current documentation.

Change-Id: I0269d15a685ed0c0241be8c8acfade0e58363845
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-22 12:02:28 +00:00
Patrick Rudolph 7187758038 Documentation: Fix markdown highlighting
Fix some code blocks that use invalid Markdown syntax.

Change-Id: I8cfe63b2c21ae93923f88bbf7ef4cfb8dccdb5ef
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-22 12:02:15 +00:00
Lijian Zhao 3b43c01bba mb/google/poppy/var/nocturne: Change IMX319 sensor link freq
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the
changes from kernel driver. IMX319 has two PLLs and it can be configured
either single or dual. Previous driver implemente dual PLL mode, however
image sensor vendor prefer single PLL mode and calculate the pixel rate
became easier. So the kernel driver changed to use single pll, coreboot
change will match that.

Bug=b:116082248

Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28736
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22 08:46:36 +00:00
Peter Lemenkov 6dc7748551 mb/lenovo/*/romstage: No need to specify board's model in comments
This is a cosmetic one. It just removes some board names from comments
since these functions sometimes are very similar, so no need to add
extra difference between them.

Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-22 08:44:08 +00:00
Nico Huber 9df62b04ff mainboard/: Select MISSING_BOARD_RESET appropriately
We didn't have a hard_reset() implementation for these boards. So
select the board_reset() stub for them.

Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29170
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22 08:40:55 +00:00
Nico Huber e20dd19dde amdfam10: Convert to `board_reset()`
And here comes the mess...

This just renames do_hard_reset() to do_board_reset() and keeps current
behaviour. As these are never called from chipset or board code but only
from common code, it's likely that their implementations are untested
and not what we actually want. Also note, that sometimes implementations
for rom- and ramstage differ considerably.

Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29058
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22 08:40:28 +00:00
Nico Huber f4181052af sb/amd/*/hudson: Use CF9 reset
Implement board_reset() as "system reset".

Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29057
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22 08:38:35 +00:00
Nico Huber 3e1b3b1f4f sb/amd/cimx/sb[89]00: Use CF9 reset
Implement board_reset() as "system reset".

Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29056
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22 08:37:45 +00:00
Nico Huber 68dd00d634 nb/via/vx900: Use CF9 reset
Implement board_reset() as "system reset".

Change-Id: I2b68a23cdf244884104d4ed54e19d3ab347c3a3e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29055
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22 08:36:38 +00:00
Patrick Rudolph f677d17ab3 intel: Use CF9 reset (part 2)
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22 08:35:32 +00:00
Patrick Rudolph 45022ae056 intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22 08:35:25 +00:00
Nico Huber 33fcaf91ff arch/x86: Implement common CF9 reset
It's very common across many x86 silicon vendors, so place it in
`arch/x86/`.

Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22 08:35:08 +00:00
Nico Huber 73c11194b0 soc/amd: Implement common reset API
Add an `amdblocks` internal API and rename
  soft_reset() => warm_reset()
  hard_reset() => cold_reset()
as these terms are commonly used in the surrounding code.

On Stoney Ridge, make board_reset() call cold_reset() to keep
current behaviour of common code calling hard_reset(). But add
a TODO if this is intended.

Note: Stoney Ridge is using CF9 for the actual reset but the
configuration for a cold reset doesn't use the usual full reset
bit but some other mechanism.

Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-22 08:34:56 +00:00
Nico Huber 8ba7023cf8 soc/samsung/exynos5250: Convert to `board_reset()`
Change-Id: I2f69d9f01ac5f7e28dd98e704f3280bf62b9ce58
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22 08:34:45 +00:00
Nico Huber 96d3378dde soc/mediatek: Convert to `board_reset()`
Note, MT8183 didn't select HAVE_HARD_RESET before. So it might still
need an update.

Change-Id: Ic850f2775ada5e6e543ffb92aaa033b9209596f5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22 08:34:37 +00:00
Nico Huber c6fe265f68 soc/imgtech/pistachio: Convert to `board_reset()`
Change-Id: If8fc29c46e2cbc69f94ea8b6dc414a93d82ffb28
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22 08:34:33 +00:00
Nico Huber 496fb23c5d soc/rockchip/rk3399: Convert to `board_reset()`
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22 08:34:27 +00:00
Nico Huber e8791361b5 reset: Convert individual boards to `board_reset()`
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22 08:34:19 +00:00
Nico Huber 4f32b64e4f reset: Provide new single-function reset API
board_reset() replaces the existing common reset API. There is no common
distinction between reset types across platforms, hence, common code
could never decide which one to call.

Currently only hard_reset() is used by common code. We replace these
calls and provide a fall-back to the current hard_reset() implemen-
tation. The fall-back will be removed along with hard_reset() after the
transition of all boards.

Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22 08:34:00 +00:00
Furquan Shaikh 076ce2f4d9 mb/google/octopus: Preserve MRC training data across firmware update
This change udpates FMAP to wrap MRC training data in RW_PRESERVE
section so that we don't lose the data when performing full firmware
updates on octopus.

BUG=b:117882029
TEST=Verified that chromeos-firmwareupdate doing full firmware update
preserves training data on octopus.

Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-19 09:25:23 +00:00
Peter Lemenkov 93faff84cb soc/lowrisc: Remove the remains of a LowRISC soc
Looks like we've got a race condition between commit ce8763fb with
Change-Id I4e3e715106a1a94381a563dc4a56781c35883c2d ("mb/lowrisc: Remove
the Nexys4DDR port") and commit 2e38dbe5 with Change-Id
I5524732f6eb3841e43afd176644119b03b5e5e27 ("riscv: update mtime
initialization"). Let's fix it.

Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29165
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-19 09:24:59 +00:00
David Wu 80496f0967 mb/google/fizz: Provide nhlt variant API
Move current NHLT configuration implementation to baseboard so that
variants can leverage it or provide their own configuration.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot

Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19 09:24:18 +00:00
David Wu eaab80efaf mb/google/fizz: Provide cros_gpio variant API
Add support for ChromeOS GPIO ACPI table information by providing weak

implementation from the baseboard.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot

Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19 09:24:05 +00:00
David Wu d1be92ce07 mb/google/fizz: Add variant API for gpio
Provide API for gpio table functionality. Default weak
implementations are provided from the baseboard.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot

Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19 09:23:49 +00:00
David Wu aceaa71531 mb/google/fizz: Provide baseboard and variant concepts
In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:

variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers

New boards would then add themselves under their board name within
"variants" directory.

This is purely an organizational change.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514

Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19 09:23:23 +00:00
Raul E Rangel 8f45bf2be7 google/grunt: Remove unused MRC regions from FMAP
I didn't change the offsets of all the other regions because I didn't
want to cause all dogfood devices to lose their corp enrollment.

BUG=b:117797131, b:117798830
BRANCH=none
TEST=Ran autotest and made sure the tests were skipped
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache                                      [  PASSED  ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache                                        TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal [  PASSED  ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal   TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.

Change-Id: I5cdbf4139dde80fe6e9d0045139a97841b03bc42
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/29171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-19 09:22:54 +00:00
Elyes HAOUAS 4fe0cbac97 nb/intel/nehalem: Remove unneeded whitespace
Change-Id: I942a054144e05a3722c3743e445a879e86021dd4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-19 09:20:34 +00:00
Elyes HAOUAS d50cf23e43 {cpu,drivers}/amd: Replace MTRR addresses with macros
Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29173
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-19 09:20:22 +00:00
praveen hodagatta pranesh 253cd5a7e6 mb/intel/coffeelake_rvp: Add HDA controller driver support for coffee lake
this patch adds following changes
- Select config to initialize codecs in common HDA driver.
- Add audio verb table for coffee lake RVP11 & RVP8.

BUG: None
TEST: boot to yocto linux and windows os on CFL RVP11 & RVP8. verified audio
      playback and record functionality over anolog audio jack & HDMI display.

Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19 09:15:26 +00:00
praveen hodagatta pranesh dc4fceb59a soc/intel/cannonlake: Enable HDA driver support
This patch selects common HDA driver and adds audio controller device id
to enable audio on coffee lake platforms.

BUG= None
TEST= boot to yocto linux and windows os on CFL RVP11 & RVP8, verified audio
      functionalities.

Change-Id: I4a60a4d7d8babcd0c14664a304ca81d47c668a6c
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29145
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-19 09:15:18 +00:00
Peter Lemenkov 4ebf9d359d mb/lenovo/*/romstage: Remove explicit power-on defaults
Change-Id: Ib359e4039f87bb87faac040f24f70cc0988c0ea8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-19 08:42:06 +00:00
Fehér Roland Ádám d5a8155f1b util/inteltool: Fix LynxPoint (non-LP) GPIO register map
The GPIO register dumper code for the LynxPoint family PCH chips
(Intel 8 Series and C220 Series) was incorrectly using a
shortened version of the LynxPoint-LP GPIO register map.
Switched to the correct register map for the affected chipsets.

Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f
Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com>
Reviewed-on: https://review.coreboot.org/29167
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 19:42:11 +00:00
Elyes HAOUAS 967b84d5ea src/mainboard: Remove unneeded whitespace
Change-Id: Ibf23f49e7864c611a3cb32a91891b6023a692e1d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18 17:17:58 +00:00
Elyes HAOUAS 0b5b44e004 libpayload/curses/PDCurses/doc/intro.txt: Remove unneeded whitespace
Change-Id: Ib5a0f193d54d1b6f2431f7b801678f2a983c7941
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28432
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 17:17:35 +00:00
Elyes HAOUAS 62e61c76b7 mb/google/glados/variants/sentry: Remove unnneded whitespace
Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28703
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 17:17:27 +00:00
Michał Żygowski 7d89a452d5 minnowmax: allow both 1333 and 1066 MHz memory SKUs
The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds.
Use frequency as a proxy to determine SKU. The E3805, E3815,
E3825, and E3826 are all <= 1460MHz while the E3827 and E3845
are 1750MHz and 1910MHz, respectively. This will allow to boot
quad-core Minnowboard Turbot especially.

Change-Id: I5e57dd419b443dfa742c8812cec87274af557728
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27989
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 16:28:37 +00:00
Joel Kitching 9937a063d4 tpm/tspi: clean up tpm_setup function flow
Introduce two helper functions for more readable code.
Use epilogue function instead of goto for error handling.

BUG=None
TEST=None

Change-Id: Ibea44880683a301e82ee2ba049003c36fcb44eba
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-18 16:22:40 +00:00
Elyes HAOUAS 660389ef9e cpu/x86/smm: Fix non-local header treated as local
Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18 16:22:12 +00:00
Elyes HAOUAS 38f1d13a75 src/{sb/intel,mb/google/auron}: Don't use device_t
Use of device_t is deprecated.

Change-Id: I564319506870f75eab58cce535d4e3535a64a993
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18 16:22:03 +00:00
Duncan Laurie 32ca3cd246 ec/google/chromeec: Use common MEC interface
Switch to using the common MEC interface instead of the
Chrome EC specific code.

Tested on a Chell chromebook that has a MEC based Chrome EC
to ensure that the EC interface is still functional.

Change-Id: Idf26e62c2843993c2df2ab8ef157b263a71a97c9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18 15:01:40 +00:00
Duncan Laurie 26cf00ab49 ec/google/common: Add a common MEC interface
In order to re-use the MEC interface code in the Chrome EC driver
move it to a common directory within the ec/google directory.

The Chrome EC driver itself is changed to use this interface in the
next commit, and future commits will introduce a new EC that also
uses this interface.

Change-Id: I13516b5e4c4c49f53bb998366284a26703142e2a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18 15:01:27 +00:00
Huayang Duan c2ef1029fa mediatek/mt8183: Add EMI init for DDR driver init
Add EMI config to initialize memory.

BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>

Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea
Reviewed-on: https://review.coreboot.org/28835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18 15:01:02 +00:00
Tristan Shieh 91a580308c mediatek/mt8183: Add register definitions of DRAM controller
Add register definitions of DRAM controller.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I8b51486deab856a783b87f0b2812a991d4111020
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18 15:00:39 +00:00
Elyes HAOUAS 2c5652d72b mb: Fix non-local header treated as local
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18 12:51:50 +00:00
Elyes HAOUAS 39db144743 mb: Replace MSR addresses with macros
Change-Id: I020431ba8eb61f5ce256088b919c049985331d64
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18 12:51:39 +00:00
Elyes HAOUAS 400ce55566 cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18 12:51:26 +00:00
Julius Werner e64a585374 console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOS
CB:26053 changed coreboot's default loglevel from SPEW to DEBUG. This
may be the most reasonable choice for most users that are mostly
interested in the UART console. However, on Chrome OS devices the UART
is disabled for production configurations anyway, and instead they rely
heavily on the CBMEM console for remote debugging and bug reports. For
these kinds of cases more info is almost always better, and you can't
easily reproduce a remotely filed bug if you notice that you need some
info that is only provided by BIOS_SPEW. On the other hand, the cost of
logging extra info to the CBMEM console is pretty negligible.

Therefore, let's bump the loglevel for CONFIG_CHROMEOS in particular
back up to the maximum. (Unfortunately, it seems that you can't 'select'
a choice option from another option, so this has to go in the
console/Kconfig file.)

Change-Id: I50724e3f7f8f57fdbc5846f21babc71798b21b65
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18 12:50:41 +00:00
Richard Spiegel 6205221a73 soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40
Register 0x40 of miscellaneous MMIO is double defined, with different names,
which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only
bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO
registers.

BUG=b:117818431
TEST=Build grunt.

Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18 12:49:43 +00:00
Richard Spiegel e7e01116e7 soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIG
SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the
first definition are unused. Remove first definition and its associated
bits and shifts.

BUG=b:117818430
TEST=Build grunt.

Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-18 12:49:26 +00:00
Richard Spiegel d5f23cecd9 soc/amd/stoneyridge: Remove double definition for wideio
WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the
definitions within MMIO definitions, as wideio is not related to MMIO.

BUG=b:117814228
TEST=Build grunt.

Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18 12:48:50 +00:00