Commit Graph

26449 Commits

Author SHA1 Message Date
Subrata Banik 46caf09598 soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.

Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:10:00 +00:00
Subrata Banik 1f33a0c799 soc/intel/common/pch: Select Kconfig for ITSS polarity configuration
This patch selects Kconfig for Intel Core Platform in order to ensure
proper ITSS IPCx programming.

Change-Id: I81e75e17ceb23c364b78300c3950144be1580700
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:09:46 +00:00
Chris Zhou 3087bf5283 mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timings
After adjustment on Liara EVT
H1: 392.03 KHz
TP: 397.87 KHz
TS: 397.71 KHz

BUG=b:116309237
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
     measure by scope

Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-09 14:33:22 +00:00
Philipp Hug 56dceb2e1a payloads: Only show supported payloads in menuconfig
Some payloads don't depend on their supported platforms, which makes
them visible in menuconfig even if they are not supported (yet).

Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-09 11:29:52 +00:00
Nico Huber e3c05c4a3f util/cbmem/Makefile: Remove .dependencies on `clean`
Change-Id: Ic122b3eaed54e29bbb3e11de84822169c81c04eb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-09 07:08:18 +00:00
Angel Pons fa6ff60c8c util/superiotool/smsc.c: Add some register dumps
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.

The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.

Datasheets used:
 - SCH311X: DS00001872A
 - SCH5127: DS00002081A

Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-08 17:54:27 +00:00
Akshu Agrawal dd14029457 mainboard/google/kahlee: Set PSPP setting to BalancedHigh
Setting default PSPP setting to BalancedLow was causing audio
playback issue in most of the units. With BalancedLow either there
was no sound or noise on playback.
Switching to BalancedHigh as default option.

BUG=b:116553085, b:112020107
TEST=Test playback and hear proper audio.

Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28967
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 17:22:57 +00:00
Nico Huber d44221f9c8 Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.

Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.

Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08 16:57:27 +00:00
Subrata Banik 834543c0c7 soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferenced
This patch fixes KW issue due to pointer being NULL and will be dereferenced

Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28948
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 14:49:18 +00:00
Pan Sheng-Liang f7cc469139 mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Bobba
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 3 for DVT.

BUG=b:115697578
TEST=verified it in Bobba EVT board which rework ram id.

Change-Id: I0fb457d8772f5038e5d90188d7682956ddfad46b
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 14:45:46 +00:00
Patrick Georgi 9360feaf51 smmstore: Add a key/val store facility in flash, mediated through SMM
It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.

Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:46:30 +00:00
Elyes HAOUAS 88607a4b10 src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:46:16 +00:00
Nick Vaccaro d9169f826a mb/google/poppy/variant/nocturne: correct wifi wake register
Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.

BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.

Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:45:39 +00:00
Nick Vaccaro 82aa8f8d7b mb/google/poppy/variant/nocturne: Disable WAKE# signal
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled.  This change disables WAKE#.

BUG=b:117284700
TEST=none

Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08 09:45:36 +00:00
Elyes HAOUAS ef20ecc92b nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address
Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-08 09:44:56 +00:00
Patrick Rudolph 6f027ff28a Documentation: Improve elgon documentation
* Convert PNG to JPG and reduce image quality.
* Mark flash IC and USB serial connector.
* Mark SPI programming header.
* Add programming header pinout.

Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-08 08:45:17 +00:00
Patrick Rudolph 17856b720b util/intelvbttool: Rewrite tool
* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout

Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.

The required arguments have been changed:

./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]

SOURCECMD set the VBT source. Supported:
 inlegacy  : Legacy BIOS area at phys. memory 0xc0000
 invbt     : Read raw Intel VBT file
 inoprom   : Read VBT from Intel Option ROM file

DESTCMD set the VBT destination. Supported:
 outdump   : Print VBT in human readable form
 outvbt    : Write raw Intel VBT file
 patchoprom: Patch existing Intel Option ROM

Any combination of SOURCECMD and DESTCMD is possible.

Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-08 02:33:06 +00:00
Jonathan Neuschäfer fd29ff3555 Documentation/mb/sifive: Fix dead links
SiFive's website was reorganized, which broke our links to PDF files.
Update these links to the current ones, obtained by browsing
https://sifive.com/documentation/.

Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:32:11 +00:00
Jonathan Neuschäfer 50b74b2a27 arch/riscv: Update comment about mstatus initialization
coreboot does not set up virtual memory anymore.

Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:30:32 +00:00
Jonathan Neuschäfer 5fba1ea5bc mb/emulation/*-riscv: Remove "UCB" from RISC-V board names
RISC-V is not a project of the University of California, Berkeley,
anymore; it stands on its own feet now.

Remove the "UCB" component from the RISC-V mainboards in the "emulation"
directory, and don't set MAINBOARD_VENDOR to UCB, either.

Change-Id: I301d9d0091a714e62375052e5af06a9197876688
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:30:18 +00:00
Furquan Shaikh 6bedbd6116 soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.

Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06 00:18:25 +00:00
Furquan Shaikh 2c343386df mb/google/poppy/var/ampton: Get rid of min board id for DRAM in CBI
All ampton boards should have the DRAM info configured in CBI and so
DRAM_PART_NUM_ALWAYS_IN_CBI is already selected for ampton. This
change gets rid of the redundant minimum board id value for Ampton.

BUG=b:117071184

Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06 00:09:01 +00:00
Furquan Shaikh 1f878fc67a mb/google/octopus/variants/fleex: Disable I2C0 in devicetree
Fleex does not have any device on I2C0 and hence this change disables
I2C0 device (16.0) in devicetree and gets rid of the I2C tuning
parameters for I2C0.

BUG=b:115600671

Change-Id: Ib799eae05b667cee2272bbd37f0ca44b7cec66cd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06 00:08:04 +00:00
Furquan Shaikh 778065146c mb/google/octopus: Disable I2C3 in devicetree
I2C3 is connected to the debug header and won't be required unless
connecting the debugger. This change disables I2C3 device (16.3) in
devicetree.

Change-Id: I650fa040075119a21864c83d8470dd2155c9edb9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-10-06 00:03:35 +00:00
Furquan Shaikh 999b916015 mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD
This change uses the generic device driver to provide DMIC properties
in ACPI table to the OS driver.

BUG=b:112888584

Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06 00:03:18 +00:00
Furquan Shaikh 6fb0448187 drivers/generic: Add support for providing DSD properties
This change adds support in generic device driver to add properties to
DSD table. This driver can be used by all generic devices that do not
need any special handling other than simply adding device properties
to be used by OS.

BUG=b:112888584

Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28796
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06 00:02:12 +00:00
Furquan Shaikh 84f2c63590 soc/intel/common/block/hda: Enable static scanning of devices under HDA
This change sets scan_bus operation for HDA to scan_static_bus to
allow enumeration of static devices under HDA.

BUG=b:112888584
TEST=Verified that devices added under HDA get enumerated on Nocturne.

Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06 00:01:20 +00:00
Furquan Shaikh 31bff01a72 soc/intel/.../hda: Add and use config for initialization of HDA codecs
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for
initialization of HDA codecs only. This prevents adding of any static
devices under the HDA device node. However, there can be boards which
want to add devices under HDA node (e.g. nocturne that wants to
provide DMIC properties to OS) without performing any codec
initialization using the HDA. This change:

1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can
be set explicitly by the boards that want to perform codec
initialization.

2. Uses newly added config option is used to guard the initialization
functions for the codec. Rest of the device operations can still be
used by all the other boards without having to use HDA codec
initialization.

3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in
kblrvp which is the only board enabling HDA codec initialization
using common block code.

4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC.

Above changes need to be bundled and pushed in as a single change in
order to avoid breaking existing users.

BUG=b:112888584

Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-06 00:01:07 +00:00
Angel Pons 3b6bddafe7 Documentation/mainboard/gigabyte/ga-h61m-s2pv: Expand page
Uniformize the Yes/No in the tables, expand the internal programming
section and explain how to patch a defective flash descriptor.

Change-Id: I972bb8948c29ce0eba46daa92ce6b6052db7b063
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05 21:14:54 +00:00
Pratik Prajapati 645064a59e soc/intel/skylake: check for NULL with if condition
This patch removes assert() and checks if the dev is NULL with "if"
condition only.

Found-by: klockwork

Change-Id: Icd2c8490c8bda14ecd752437d463a7110fe40aea
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/28888
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05 20:32:24 +00:00
Pan Sheng-Liang 4f6eccdcac mb/google/octopus: adjust Bobba I2C CLK under 400KHz
Need to tune I2C bus 0/6/7 clock frequency under the 400KHz for
digitizer, touchpad, and touchscreen.

Bug=b:117126484
TEST=flash coreboot to the DUT and measure I2C bus 0/6/7 clock
frequency whether can <400KHz

Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28907
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05 16:36:35 +00:00
Joel Kitching f97ff0cd50 tpm2/tlcl_send_startup: correct TPM2_Startup error logic
BUG=b:114018226
TEST=compile coreboot

Change-Id: Iffad582d5c19252dde1c9dc97fc7fd145944a3b3
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-05 03:47:22 +00:00
Patrick Georgi 7aa44522f2 3rdparty/fsp: update to current master
This includes the SplitFspBin.py script.

Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05 03:29:25 +00:00
Patrick Rudolph eec0d9b8dc LinuxBoot/arm64: Remove firmware from defconfig
The extra firmware is not part of upstream kernel.
Fixes build error if the firmware is not present.

Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-05 03:27:39 +00:00
Patrick Rudolph fca506d579 drivers/spi/winbond: Add new chip
The W25Q128J is a QSPI flash chip, without ~HOLD and ~WP.
Add the device id to make coreboot boot from it.

Change-Id: I623fdf7d7e30eb28259bec6294785ad873f1f503
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-05 03:25:15 +00:00
Angel Pons cc335c7567 src/lib/edid.c: Replace #if 1 with something useful
Since `#if 1` is rather useless, and the code inside it is just several
`printk(BIOS_SPEW)`, using `if (console_log_level(BIOS_SPEW))` instead
seems more reasonable.

Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-05 01:45:46 +00:00
Seunghwan Kim 00b539452b mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE sku
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber
test, but the root cause is unclear.

Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal
reset issue, so we would apply it until find root cause of this issue.

BUG=b:117130599
BRANCH=poppy
TEST=Built and passed on reliability test with modified coreboot

Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05 01:40:38 +00:00
Elyes HAOUAS 4e6b7907de src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-10-05 01:38:15 +00:00
Caveh Jalali 19c0ae540e atlas: control touchscreen power using ACPI
This adds the ACPI controls for power sequencing the touchscreen.

The initial setting is to keep the touchscreen powered off and in
reset.  When linux is ready to talk to the touchscreen, it powers it
on and releases reset via ACPI.

BUG=b:110286344
TEST=verified touchscreen is functional in chromeos

Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05 01:37:51 +00:00
Marshall Dawson 5fdd201c17 amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL
TEST=Build Grunt
BUG=b:77602074

Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05 01:37:29 +00:00
Marshall Dawson 33d4f73eef amd/stoneyridge: Remove unused registers from ASL
Remove AcpiMmio and PCI config registers that are not used.

TEST=build Grunt
BUG=b:77602074

Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05 01:36:56 +00:00
Marshall Dawson 0425b0a4bb amd/stoneyridge: Remove SATA D0 on suspend
Remove the step of setting the SATA controller to S0 as the system is
entering S3.  This had been duplicated from AMD's FchCarrizo.asl file,
but upon closer inspection, the conditions for this step to run cannot
be met.  This does not affect Grunt's behavior, as the SATA controller
is disabled.

TEST=Suspend and resume Grunt
BUG=b:77602074

Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05 01:36:44 +00:00
Martin Roth 0b9896f328 mb/google/kahlee: Don't set stapm parameters
Setting the stapm parameters is causing S3 resume failures and
performance issues.  Removing these settings until more testing is
done and the issues are solved.

BUG=b:117252463, b:116870267
TEST=boot grunt

Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-04 22:07:34 +00:00
Angel Pons a5072af67d util/autoport: Use romstage.c instead of early_southbridge.c
Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.

Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04 18:20:16 +00:00
Daisuke Nojiri 2b59c610d0 cbfstool: Clear entry being removed in all cases
Currently, an entry being removed is cleared only if the next entry
is also null or deleted.

This patch ensures the entry being removed is cleared regardless of
the next entry type.

BUG=chromium:889716
BRANCH=none
TEST=Run cbfstool bios.bin remove -n ecrw.
Verify bios.bin has 0xFF in the space of the removed entry.
TEST=Run cbfstool bios.bin remove -n fallback/payload (located at the end).
Verify fallback/payload is removed.
TEST=Run sign_official_build.sh on recovery_image.bin. Extract
firmware contents from chromeos-firmwareupdate in the resigned image.
Run 'futility vbutil_firmware --verify' for vblock_A's and FW_MAIN_A
extracted from bios.bin. See the bug for details.

Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04 17:16:41 +00:00
Kevin Chiu 0fa007be13 google/grunt: Correctly extract OEM string from CBFS
In CBFS layout:
oem.bin size is 10 bytes.

In cbfs_boot_load_file, buffer size will need to be larger
than decompressed_size, otherwise CBFS data can not be
extracted into buffer.

Then we need to check buffer whether it's empty string separately.

BUG=b:79874904
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I4f1bbb690ecca515ac920f5058ee19b5bfd8fa5e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:25:53 +00:00
Raul E Rangel 59e923d757 libpayload/x86/exception: Add ability to ignore unknown interrupts
This will make enabling the APIC safer by ignoring unknown interrupts
and not halting the system. Once all interrupt sources have been found
and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired.

BUG=b:116777191
TEST=Booted grunt, halted the kernel, and pushed the power button while
in S5. Verified that depthcharge logged the unknown exception.

APIC Init Started
APIC Configured
Ignoring interrupt vector 39

Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:25:17 +00:00
Raul E Rangel 44d89f526d libpayload/x86/exception.c: Remove exception_install_hook
Not used by x86 code anymore.

BUG=b:116777191
TEST=Validated that depthcharge can be built.

Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:54 +00:00
Raul E Rangel ad37763a5f libpayload/apic: Register a spurious interrupt vector
We should have a spurious interrupt vector just incase we get one. The
handler doesn't need to do anything.

BUG=b:116777191
TEST=Booted depthcharge on grunt and inspected the register. I can't
generate a spurious interrupt, so I can't validate that the handler gets
called.

Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:44 +00:00
Raul E Rangel b025de0ddb libpayload/apic: Only ACK interrupts triggered by the APIC
Only set end of interrupt (EOI) when the APIC In-Service vector matches
the interrupt vector. This makes it so we don't EOI a non APIC
interrupt.

BUG=b:116777191
TEST=Booted grunt with APIC enabled and verified depthcharge still
works.

Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:20 +00:00