Commit Graph

4157 Commits

Author SHA1 Message Date
Elyes HAOUAS 8297fa1e20 util: Remove old reference to ROMCC
Change-Id: Ia1a37db8341281102ae8ae9c03f1ce76d8d126eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39075
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 14:23:32 +00:00
Jacob Garber c44d1e2c7c xcompile: Use GCC wrappers for ar, nm
When compiling with GCC, use the special wrappers around ar and nm that
provide the path to the plugin they need to understand LTO object files.
These wrappers forward all other functionality to the underlying
programs, so they should otherwise be equivalent.

Change-Id: Ibdae4faabf67bf6a4bb8c38970f6189646ee74b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38290
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 14:12:17 +00:00
Elyes HAOUAS 2119d0ba43 treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 14:10:00 +00:00
Angel Pons 4684dc0c63 util/inteltool: Add missing entry for WPT-LP Premium
Tested on a laptop with an i7-5500U processor, the device is now found.

Change-Id: I49ddec862520d0d5492d78fec89efd841c141790
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-24 12:48:09 +00:00
Evgeny Zinoviev 8c4c370030 util/ifdtool: Mention MeDisable in help text
The -M option of ifdtool sets not only AltMeDisable bit, but also
MeDisable bit in ICH0 and MCH0 straps. Make it obvious and mention
in the help message.

Change-Id: I9dba2fa6509a9c833f72414367944bc606671e7b
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-24 12:47:09 +00:00
Paul Fagerburg 291a014e15 util/mainboard/google: deduplicate create_coreboot_variant.sh
create_coreboot_variant.sh and kconfig.py have moved to the chromium
repo, in src/platform/dev/contrib/variant (see crrev.com/c/2052338),
so remove them from the coreboot repo.

BUG=b:149410618
BRANCH=None
TEST=N/A

Cq-Depend: chromium:2052338
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ie27f68bfd978be5e2b1a2f0789d574749825f6fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-21 16:55:58 +00:00
Patrick Georgi cbc5b99ac9 util/lint: Allow non-option carrying named choices
named choices can be overridden with a default later-on:

choice FOO
  config A
  config B
  config C
endchoice

...

if BOARD_FOO
choice FOO
  default A
endchoice
endif

Reflect that.

Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29813
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-19 15:13:37 +00:00
Patrick Georgi 900a254475 util/amdfwtool: Improve comment's grammar
Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-18 15:33:43 +00:00
Elyes HAOUAS 6dc9d0352e treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.

Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 20:11:24 +00:00
Angel Pons 9c26605353 util/autoport: Fix typo
Also reflow the paragraph in which the typo was hiding a bit.

Change-Id: I2fea01fe23af21c2540fa90154ce29af3e74776b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-17 15:59:07 +00:00
Elyes HAOUAS 99e54fece3 util: Fix typos
Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 15:53:49 +00:00
Arthur Heymans 96f18a01da util/k8resdump: Remove util
AMD K8 support was dropped.

Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 15:45:46 +00:00
Paul Menzel 141020a80a autoport: Remove space in example code
The coreboot coding style does not insert a space between the function
and argument list.

Change-Id: I740f6c7f513e4f2715c793f61c9d9835c55c9dce
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 15:44:14 +00:00
Patrick Georgi 3404247115 util/docker: Use more stable URL
The pgeorgi namespace is my own and things could change without notice
there. To overcome this issue, encapsulate is now maintained on
review.coreboot.org/encapsulate.git and mirrored over to github, so
let's use that.

Change-Id: I12e43f61f693a6b0392b84dd56ede665a1a2129a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38899
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17 15:40:17 +00:00
Elyes HAOUAS 65718760fa crossgcc: Upgrade IASL to version 20200110
Changes:
  20200110: https://acpica.org/node/176
  20191213: https://acpica.org/node/175
  20191018: https://acpica.org/node/174
  20190816: https://acpica.org/node/172

Change-Id: Ifaa0d1c79802872c1a822c1108d2a50bc60c8fd8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38347
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12 19:48:58 +00:00
Paul Fagerburg e967cfa409 util/mainboard/google: add support for Zork
Update the create_coreboot_variant.sh and kconfig.py to support the
zork baseboard. Full template files will be added in a later CL.

BUG=b:148161697, b:148281637
BRANCH=None
TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the
changes staged are correct.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-09 19:30:18 +00:00
T Michael Turney 540b8ecc1e trogdor: update python scripts for python3
Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-09 19:27:00 +00:00
Marcello Sylvester Bauer 6f9a77851b util/ifdtool: Support modification of single Flash Descriptor
Add the capability to update the Flash Descriptor directly instead
of raising a Segmentation Fault. In this way it will be possible to
add a Kconfig options to modify the ifd descriptor at build-time.

Change-Id: Id3db09291af2bd2e759c283e316afd5da1fb4ca7
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-09 19:22:42 +00:00
Ronald G. Minnich 466ca2c1ad Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.

To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.

MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.

Some devices must be scanned in all cases, such as 0:0.0.

To indicate which devices we must scan, we add a new mandatory
keyword to sconfig

It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.

We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.

Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.

TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch

Before CL:
Total Boot time: ~685ms

After CL:
Total Boot time: ~615ms

Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-02-08 18:57:36 +00:00
T Michael Turney bcd62f5737 trogdor: support mbn_version 6 with python build scripts
Developer/Reviewer, be aware of this patch from Mistral:
 https://review.coreboot.org/c/coreboot/+/33425/18

Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-07 23:11:45 +00:00
Wim Vervoorn 01bfa53f77 util/docker/coreboot-sdk: Add packages required to build LinuxBoot
Add golang and libelf-dev so LinuxBoot can be built from the
coreboot-sdk docker container.

BUG=N/A
TEST=build

Change-Id: I7a156fc24a6040d73467e06c16139bf298a29740
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38751
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-07 16:42:18 +00:00
ashk a547584445 trogdor: Add T32 scripts for full boot chain
Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-06 01:46:17 +00:00
Jacob Garber 84c7d2dfea xcompile: Disable null pointer optimizations
According to the C standard, accessing the NULL pointer (memory at
address zero) is undefined behaviour, and so GCC is allowed to optimize
it out. Of course, accessing this memory location is sometimes
necessary, so this optimization can be disabled using
-fno-delete-null-pointer-checks. This is already done in coreboot, but
adding it to xcompile will also disable it for all the payloads. For
example, coreinfo compiled with LTO libpayload crashes when this flag
isn't set, presumably because the compiler is optimizing something out
that it shouldn't.

Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-03 16:46:00 +00:00
Johanna Schander 0174ea78bf util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
This GPIO dumping was implemented using the

Document Number: 341080-001
Intel® 495 Series Chipset Family On-Package Platform Controller Hub
Volume 1 of 2

datasheet. The GPIO community ports can be found in table 36-1, while
the community and pin descriptions are taken from
linux/pinctrl/intel/pinctrl-icelake.c .
This commit was tested on the late 2019 Razer Blade Stealth with 1065G7
and Chipset 495 PCH and the output manually compared against
linux/pinctrl-intel.

Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-02-01 19:51:51 +00:00
Patrick Georgi a58e503442 util/cbfstool/lzma: Make clang-11+'s indentation checker happy
Newest clang compilers warn about "misleading indentation", and because
warnings-are-errors in our builds, that breaks the build.

The lzma code base is vendored in, so we might just have to update it,
but that's a bigger effort than just removing a couple of spaces (the
coding style of the file is horrible, but I will only change it as much
as the compilers ask for).

BUG=chromium:1039526

Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-01 19:51:31 +00:00
Wim Vervoorn 60510733ae util/docker/Makefile: Correct help output
The help output suggests clean-docker should be used to remove the
docker coreboot containers and images. The Makefile actually supports
the docker-clean target.

Corrected the help output to reflect the actual Makefile target.

BUG=N/A
TEST=build

Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-01 19:49:03 +00:00
Julius Werner d6900a96e0 cbfstool: Set deprecated _BSD_SOURCE and _SVID_SOURCE macros
In glibc feature control macros, _DEFAULT_SOURCE is the shorthand to
tell glibc to enable "all the default stuff", meaning POSIX, BSD and
System V interfaces. However, this macro is somewhat recent and older
glibc versions (e.g. 2.12) are still occasionally in use that don't
recognize it yet. For the benefits of users with these versions, let's
also enable the deprecated _BSD_SOURCE and _SVID_SOURCE macros which
essentially achieve the same thing. We must continue to define
_DEFAULT_SOURCE so that newer glibc versions don't throw a deprecation
warning.

This patch should make BSD-style byteswap macros like le32toh()
available on these older glibc versions.

Change-Id: I019bbcf738a1bcdccd7b299bdde29cd4d4ded134
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-01-31 20:36:40 +00:00
Felix Held b729d8b6e3 util/lint: enforce SPDX license headers in src/superio
Change-Id: Iae8d4f0470f75b47e53c50790f06902acb9a24cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-30 13:55:41 +00:00
Patrick Georgi 220c2092ae util/*: more typo fixes
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f $(find util -name '*.[ch]')

Change-Id: I059071fd3a2edb41c72fc57fccbb520bd2ebb757
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-30 13:47:49 +00:00
Patrick Georgi 5c65d00ef2 util/msrtool: Fix formatting issues reported by checkpatch
Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30 13:01:50 +00:00
Patrick Georgi fbbef02f06 util/msrtool: Fix typos
The Intel docs also call it "Scalable Bus Speed", so the typo is on us.

Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/msrtool/*.c

Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30 13:01:11 +00:00
Patrick Georgi 01cfecc883 util/cbfstool: Fix typos
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/cbfstool/*.c

Change-Id: I13a27407bf2bad4b9fadcec8cdbd5889068f13cf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38633
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30 13:01:00 +00:00
Patrick Georgi 805b291830 util/lint: Update spelling.txt from lintian data set
commit 1191c09201b43aab55333a70d056d0c355abe329 at
https://salsa.debian.org/agx/lintian/tree/master/data/spelling provides
a much more comprehensive collection of misspellings, so merge it in.

While at it, also sort the file for future easier merging which is the
main reason that some lines appear to be removed: they're merely moved.

For sorting, I adapted their make rule:

	make -f - sort-spelling.txt <<'EOF'
	.RECIPEPREFIX=%
	sort-%: %
	%csplit --prefix $<- $< '/^$$/'
	%LC_ALL=en_US sort -u $<-01 | cat $<-00 - > $<
	%rm -f $<-0[01]
	EOF

Change-Id: I939e3a8820c88d0e639bd29b46a86b72bce1a098
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38632
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30 12:59:19 +00:00
Peter Lemenkov 71a7ca786e autoport: Don't add useless whitespace in comments
Change-Id: Ie6c94c0627743f9e965347ecfd28f1b0441178ad
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38516
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28 18:38:06 +00:00
Julius Werner 98eeb96135 commonlib: Add commonlib/bsd
This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.

Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).

Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.

Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-28 06:36:13 +00:00
Angel Pons d8eadffc7b superiotool: add IT8772F register dump
Values as per "IT8772E Preliminary Specification V0.4 (For F Version)".
Some values are unclear on this document, but is the only one I have.

Change-Id: I6d74984f453c47d6ec71963a7dcab961a22a5964
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-22 17:22:50 +00:00
Idwer Vollering a682fc81ae util/amdfwtool: guard typedef aliases
Build tested on Ubuntu 18 LTS, FreeBSD.

Change-Id: Ida2c1f36aba7469d69dbb12ee6afce4a181bd6b7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20 14:43:31 +00:00
Idwer Vollering 724753d472 util/cbmem: simplify include lines in Makefile
Change-Id: I3d0ab7dacb5facb7dd14dd471cd0fb9f06bf0e37
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20 14:40:27 +00:00
Patrick Georgi 186c2f9abc util/nvramtool: Create nvramtool object directories earlier
The existing rule created a potential race condition between creating
the directory and putting files in there, so use our existing
infrastructure for directory creation instead.

Change-Id: If52a9f558c7d9ce85f71ba53232594699c9d357a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37798
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 14:31:29 +00:00
Wim Vervoorn 05bc9b38a3 util/ifdtool: Correct region resize handling
When regions are resized they are always aligned to the top of the
region. For the BIOS region this is correct. The other regions however
should be aligned to the bottom of the region.

Update the region handling to only align BIOS region to top of region.

BUG=N/A
TEST=verified image resize

Change-Id: Ied0e763b5335f5f124fc00de38e5db1a4d0f6785
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-20 10:49:12 +00:00
Paul Menzel 56258ff92b autoport: Improve formatting of EC ASL code
Change-Id: I7fe3e798346e760eebb357f20e55ee1a71a1e31a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-16 13:21:56 +00:00
Paul Menzel 607ee30403 autoport: Use HTTPS URLs
Update the two flashrom URLs to use HTTPS. All other URLs are already
using HTTPS.

Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15 14:24:19 +00:00
Elyes HAOUAS 40f539f8c4 crossgcc: Upgrade cmake to version 3.16.2
Change-Id: I2012f0adcb348a3ea6c50c361a49a0a600d3db3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-01-14 17:59:51 +00:00
Elyes HAOUAS eda12901fa util/crossgcc: Add comment on IASL version
Change-Id: I81c6f4134610bcd35e173cdb002ef821788b0538
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-01-14 17:59:33 +00:00
Jonathan A. Kollasch a1114f608b autoport: Add Xeon E3-1200 v2 memory controller ID
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-14 17:02:30 +00:00
Martin Roth dfd89fc85b util/lint: Enforce SPDX licenses only in src/acpi directory
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-13 10:03:07 +00:00
Johanna Schander 4ddbbd84d9 util/inteltool: Add MCHBAR dumping support for Ice Lake U systems
According to intels datasheet

Document Number: 341078-001
10th Generation Intel® Core™ Processor Families
Volume 2 of 2

we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs.
The difference is that on ICL the MCHBAR address is definited by
the bits 38:16 instead of 38:15 giving the constraint that it has
to be 64kbit instead of 32kbit aligned. (Section 3.1.13)

Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-10 15:14:02 +00:00
Patrick Rudolph a48e8f52d8 Make: Add supermicro/smcbiosinfo to tools
Build the smcbiosinfo tool with other tools.

Fixes possible race condition on jenkins.

Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-08 16:24:04 +00:00
Angel Pons 6779d2352c util/autoport: correct build errors of produced files
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-08 14:25:23 +00:00
Marshall Dawson 2dd3b5c0f8 util/amdfwtool: Add instances for APCB backup
Match each of the possible APCB items with a corresponding backup APCB.
A missing backup copy can prevent the system from booting.

Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-06 23:27:36 +00:00
Patrick Rudolph 9e877ec60d util/supermicro: Add and use new tool smcbiosinfo
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.

Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.

You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID

Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.

Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works

No further validation is done on the firmware.

Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06 10:56:09 +00:00
Nico Huber e67f539de4 abuild: Allow proper build tests with USE_AMD_BLOBS=y
Properly build test AMD ports that rely on blobs, too.

Change-Id: Ia82f38d0e57f463ee33844c7afebb9dd602cef05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-05 23:54:48 +00:00
Martin Roth e348eba641 util/lint: Update license header text for SPDX headers.
In preparation to update to SPDX license headers, add identifiers
for the licenses seen in the coreboot project and create a command
line parameter allowing only SPDX license identifiers to be detected.

Here are example locations of these licenses:
Apache-2.0 - src/soc/sifive
BSD-3-Clause - Throughout coreboot & libpayload source
GPL-2.0-only - Throughout coreboot source
GPL-2.0-or-later - Throughout coreboot source
GPL-3.0-only - util/amdtools
GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat]
ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others
MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/
X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-01-02 14:48:48 +00:00
Johanna Schander d756c27a54 util/inteltool: Add chip detection for IceLake chips
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29 21:13:17 +00:00
Patrick Georgi 0acfe1c8cd util/testing: Remove romcc from testing
Change-Id: If90193dc7c85133b10082c68a6cec6c1b0b35ffb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37958
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-28 09:45:12 +00:00
Martin Roth 92bc83674b util/docker/coreboot-sdk: Add libcurl4 requirements for em100
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia1cd7e12f12cb6d26a10fd358a3b32c31ce1c834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-12-27 17:09:41 +00:00
Paul Fagerburg 1fe7dcb047 util/mainboard/google: add support for Volteer
create_coreboot_variant.sh now supports the Volteer baseboard in
addition to Hatch. The shell script and supporting python code are
moved up one level, while retaining the ${BASE}/template/* file
structure for each supported baseboard.

kconfig.py has to add slightly different text to Kconfig.name
depending on which baseboard is selected.

BRANCH=None
BUG=b:146646594
TEST=Create variants of Hatch and Volteer, check that the staged
commits are correct.

$ ./create_coreboot_variant.sh hatch sushi b:12345
src/mainboard/google/hatch/Kconfig and Kconfig.name will have new
sections for SUSHI. src/mainboard/google/hatch/variants/sushi
will have a copy of util/mainboard/google/hatch/template

$ ./create_coreboot_variant.sh volteer ripto b:12345
src/mainboard/google/volteer/Kconfig and Kconfig.name will have new
sections for RIPTO. src/mainboard/google/volteer/variants/ripto
will have a copy of util/mainboard/google/volteer/template

Also run the script with an existing board name to verify that you
can't create a variant that already exists.

Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-27 09:03:48 +00:00
Arthur Heymans 945b698f82 util/romcc: Drop romcc support
Finally all boards use a GCC compiled bootblock!

Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 09:00:16 +00:00
Idwer Vollering 7abc037da4 util/superiotool: alter Makefile to build the binary on FreeBSD
Change-Id: Ia96bee18abcdf278ae9178471cd4af2de454facf
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-26 22:06:18 +00:00
Patrick Rudolph e69798b5ae util/pgtblgen: Fix qemu on KVM
Running the x86_64 qemu mainboard target with '-accel kvm' results in hang,
as the 'D' and 'A' bits needs to be set in read only page tables.

Tested on QEMU Q35: Boots into payload with '-accel kvm'.

Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:39:26 +00:00
Elyes HAOUAS a87a741b41 crossgcc: Upgrade Python to version 3.8.1
Change-Id: I2867d62d2e6f5ca1e97ce52ecc45a794b4831686
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20 17:51:49 +00:00
Jeremy Compostella 31e2188c38 ifwitool: Introduce a use the Second Logical Boot Partition option
The ApolloLake SoC allows two Logical Boot Partitions. This patch
introduces a '-s' optional parameter to select the second Logical
Boot Partition.

Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37660
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17 13:14:07 +00:00
Nico Huber 591dbfe295 util/cbfstool: Further reduce warnings for lz4 code
If the compiler fails to inline all the FORCE_INLINE functions, it will
complain.

Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37734
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16 09:43:17 +00:00
Nico Huber 9efc7fc540 Revert "crossgcc: Upgrade acpica to version 20191018"
This reverts commit 547de69de7.

Merged out of order before CB:36317. The conflicting use of
_ADR and _HID needs to be properly addressed before we can
bump the IASL version.

Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37713
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-14 15:37:53 +00:00
Julius Werner 3833f0ffdb cbfstool: Bump C version to C11
cbfstool depends on vboot headers, and vboot expects to be able to use
modern C features like _Static_assert(). It just so happens that it
doesn't do that in any headers included from cbfstool right now, but
that may change. Let's switch cbfstool to a newer version to prevent
that from becoming a problem.

Change-Id: I884e1bdf4ec21487ddb1bca57ef5dc2104cf8e0e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-12 20:59:41 +00:00
Paul Fagerburg 149d523c9a util/hatch: remove GBB_HWID, clean up user-visible output
* GBB_HWID is no longer used in Hatch Kconfig, so remove the code
that creates the GBB_HWID and adds it to the Kconfig section
* Add more information in the usage message when the cmdline params
are incorrect.
* Remove messages that tell the user what to do, because the top-level
program that invokes this script will handle those commands, and so
this script telling the user what to do is noise (and possibly harmful)
* Add more information to the commit message that the script prepares
for the user.
* Bump script version number.

BRANCH=None
BUG=b:140261109
TEST=Create the "sushi" variant of the "hatch" baseboard:
`util/mainboard/google/hatch/create_coreboot_variant.sh sushi`
Inspect the files in src/mainboard/google/hatch/variants/sushi

Change-Id: I04e949aedce61ed7fc7df681b72c3cfef31b5513
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-12-12 15:08:55 +00:00
Patrick Georgi a73317e5cf Documentation: enable ditaa integration
For prettier diagrams: http://ditaa.sourceforge.net/

Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12 08:18:49 +00:00
Elyes HAOUAS c79efa822d util/lint: Update spelling.txt to latest linux version
Change-Id: Ife90b61d04e32f307a688d81922bdcf6fa57cfc9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37572
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:45:07 +00:00
Patrick Rudolph bc2204edd2 util/pgtblgen: Fix typo
Change-Id: I638eda3040c7225aa4a8b492c8dc78b0e2effba1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37369
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 19:25:15 +00:00
Elyes HAOUAS 547de69de7 crossgcc: Upgrade acpica to version 20191018
Changes: https://acpica.org/node/174

Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-29 22:19:04 +00:00
Patrick Georgi c4b7ad4db5 util/release: Don't try to remove a file named like a long string
Change-Id: I81fcb58720fb20ac4f57e31e9f991f5009aba568
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-28 10:48:25 +00:00
Patrick Georgi 3e8ef1028d util/kconfig: Move coreboot specific changes into Makefile.inc
This eases maintenance of our kconfig fork.

Change-Id: Ia4bc0bf22e66457356b9f8fcbea9412792495bca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-27 23:27:29 +00:00
Elyes HAOUAS 3ba84c5950 crossgcc: Upgrade LLVM to version 9.0.0
Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:41:17 +00:00
Elyes HAOUAS 18315db8e0 crossgcc: Upgrade CMake to 3.16.0
Change-Id: Ib564217c4fdcb609fd6dfd4cb71288dd54ffe4bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:29:00 +00:00
Elyes HAOUAS a2fbddfabc crossgcc: Upgrade Expat to version 2.2.9
Changes: https://github.com/libexpat/libexpat/blob/R_2_2_9/expat/Changes

Change-Id: I591e4ed186bc8d46ff64161eddc488b640cad5fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:23:36 +00:00
Elyes HAOUAS 33847db3ce crossgcc: Upgrade Python to version 3.8.0
Change-Id: I1265e7df4d6c04aa1ccf0c65dc87e62bec5a4a35
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:23:08 +00:00
Elyes HAOUAS 2368681c83 crossgcc: Upgrade GDB to version 8.3.1
Change-Id: I380ba8678b22483b0d9c5fc558c0e08fd38778e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:22:48 +00:00
Elyes HAOUAS 18ecdbfeb8 crossgcc: Update binutils to version 2.33.1
Change-Id: I3bb6055383aa72153fffc70adc9cc446e5a0612e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36013
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 13:22:08 +00:00
Patrick Georgi a4f5954159 util/release: Add amd_blobs to blob list
Change-Id: I4417c733b3915ad74d81d2e1e0904da06eea300e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36956
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26 16:04:12 +00:00
Bill XIE c61d415701 util/sconfig: Fix illogical override rule for resource
The old logic only uses the type to identify resources, which makes a
resource in override tree overriding the first resource with the same
type (but possibly different index) in base tree, and resources with
same type (but again different index) in override tree overriding each
other.

Resources had better be identified with both their type and index.

Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37109
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26 09:11:54 +00:00
rkanabar d64b04609d util/ifdtool: Add Jasperlake platform support under IFDv2
Change-Id: I4963ab249a8e0b31c014e92edf1e0a4a4f638084
Signed-off-by: rkanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37111
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25 05:14:52 +00:00
Douglas Anderson 1bdfe8c280 qualcomm: qgpt: Fixes for python3
* Binary strings should be joined with a binary string
* Binary files should be opened in binary mode.
* Division that wants truncation should make it explicit.

I have tested that these changes let me compile.

Change-Id: I7c41b80688a9c6bdb3c66561ff531311cc7ebb13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23 10:54:46 +00:00
Patrick Georgi 436296b9bd util/release: Don't wildly rename Makefiles
Even with four cloc invocations it's faster than doing the rename
dance and messes up the tree less. It also opens up using cloc's git
mode to work on a git tree instead of a checkout.

Change-Id: I3ad8fc6802ecedb332359d00b28ea61c33ed2ea0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22 21:50:47 +00:00
Patrick Georgi 1916d68ee3 util/release: Convert board IDs into human readable names
Change-Id: Ie323112d27d228849cca7894b9ebd3f4dedd2d9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22 21:50:24 +00:00
Patrick Georgi d653e491e1 util/release: always remove temporary files
Change-Id: I8e6ff5bc72618e782ed472878bd6ea294be1b5ca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22 21:50:03 +00:00
Patrick Georgi 85678b8419 util/release: Refactor blobs list
We had two _very_ long lines containing arguments that enumerate the
paths where blobs are stored: Now there's a variable containing them.

Change-Id: I501b27158d00ba00d1c9b9e2f00a17a8b9c3f682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36955
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22 21:47:40 +00:00
Patrick Georgi 54cabb977d util/release: Try reusing the local checkout for cloning
git clone allows using a local repo as reference which reduces the
required network traffic.

Change-Id: I64722cd5dbdfc0c2bcd935715cffdb99b773711c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36954
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22 21:47:33 +00:00
Patrick Georgi d198e2e553 util/release: Make signing with GPG 2 easier
GPG 2 expects the GPG_TTY variable to be configured so
that it can properly ask for the passphrase. If it's
not already set, do so.

Change-Id: I7e145a492c9eceda40cc1a1e04452a78852042d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36953
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22 21:47:18 +00:00
Patrick Georgi 9ea4c8a71e util/xcompile: Only use -Wno-address-of-packed-member if supported
I thought gcc ignores -Wno-* stuff that it doesn't know about, but
apparently not.

Change-Id: If265a7bcdcfb5e83cc06b1f914dd6bab964eaca6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-22 10:35:59 +00:00
Julius Werner f96d9051c2 Remove MIPS architecture
The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.

Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 10:10:48 +00:00
Julius Werner 63c444a69b Remove imgtec/pistachio SoC
After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).

Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 10:10:44 +00:00
Paul Menzel e61b4c360e util/chromeos: Indent code blocks instead of using ```
This uses less lines, is the original Markdown syntax, and for short
blocks better readable.

Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19 13:28:25 +00:00
Arthur Heymans 593172c7c3 util/docker/Makefile: Add documentation docker image targets
Run
- make -C util/docker doc.coreboot.org to build the docker image
- make -C util/docker docker-build-docs to build the documentation
- make -C docker-livehtml-docs to serve autoupdated documentation over
  http://0.0.0.0:8000

Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36104
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19 13:00:38 +00:00
Elyes HAOUAS ceb7e68c48 xcompile: Explicitly disable warning address-of-packed-member
With GCC 9.x has a new warning *address-of-packed-member*.

> -Waddress-of-packed-member
>
>     Warn when the address of packed member of struct or union is
>     taken, which usually results in an unaligned pointer value.
>     This is enabled by default.

This results in the build errors below, for example, with GCC 9.2 from
Debian Sid/unstable.

    src/southbridge/intel/common/spi.c: In function 'spi_init':
    src/southbridge/intel/common/spi.c:298:19: error: taking address of packed member of 'struct ich7_spi_regs' may result in an unaligned pointer value [-Werror=address-of-packed-member]
      298 |   cntlr->optype = &ich7_spi->optype;
          |                   ^~~~~~~~~~~~~~~~~

Therefore, explicitly disable the warning.

Change-Id: I01d0dcdd0f8252ab65b91f40bb5f5c5e8177a293
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36940
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19 11:23:22 +00:00
Julius Werner cefe89ee79 lib/fmap: Add optional pre-RAM cache
This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.

In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.

Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).

Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-14 03:30:11 +00:00
Bill XIE 675cb9152e util/autoport: Stop generate empty h8_mainboard_init_dock().
CB:36385 makes dock init in ramstage fully mainboard-specific, so
keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes
unnecessary and problematic.

Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-12 18:22:34 +00:00
Arthur Heymans 55f01326cc util/lint/kconfig_lint: Handle glob prefix and suffix
Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-06 14:01:00 +00:00
Patrick Rudolph b1ef725f39 cpu/qemu-x86: Add x86_64 bootblock support
Add support for x86_64 bootblock on qemu.

Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.

Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.

Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.

The code can be easily ported to real hardware bootblock.

Tested on qemu q35.

Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:58:58 +00:00
Ravi Sarawadi 7d9d63b79f util/ifdtool: Add Tigerlake platform support under IFDv2
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3f9672053dcf0a4462ef6ab718af4f18fcfa7e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-10-31 05:38:51 +00:00
Paul Fagerburg f1ca63ca40 automation: add GPIOs and version number, change branch name
* Add defines for GPIO_MEM_CONFIG_0:3 in the template file, so
that code that relies on these defines can compile. Because they
are preprocessor symbols, there is no way to define them as
__weak in the baseboard header and allow the variant to override
as needed, so they need to be defined here and changed if needed.
* Add a version number for the script and an "auto-generated by"
line in the git commit message.
* Change the branch name so that it's not the same as the ones
that the other scripts will create, so that repo upload on those
CLs won't affect this one.

BUG=b:140261109
BRANCH=None
TEST=Create and build the "sushi" variant:
$ util/mainboard/google/hatch/create_coreboot_variant.sh sushi
$ util/abuild/abuild -p none -t google/hatch -x -a

Prior to this CL, you would get an error message that SPD_SOURCES is
not set. If you fixed that, then you would get failures for
GPIO_MEM_CONFIG_0, _1, _2, and _3 not defined, and/or gpio_table[]
and early_gpio_table[] not defined. After the CL, the build proceeds.

Change-Id: I0f48d6bb9544cad6d419d3a6fbb17f57200938b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:26:16 +00:00
Felix Singer 19e353473d inteltool: Add method 'print_system_info'
To get a better idea what this code does, this patch adds
a new method called 'print_system_info'.

Change-Id: I16f1c9cdc402b1a816fac65d1490432e39c07baf
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28 12:00:46 +00:00
Stefan Reinauer 7385b656c2 buildgcc: ACPICA: build more utilities and in parallel
- honor $JOBS in build_IASL

- Build the following utilities in addition to iasl for easier debugging of
  ACPI issues:

   * acpibin
   * acpidump
   * acpiexec
   * acpihelp
   * acpinames
   * acpisrc
   * acpixtract

Change-Id: I84476da8f9a5ba4860ba4ad0220ec3efb229cc03
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 17:46:37 +00:00
Himanshu Sahdev 6a3cf1b6fc util/crossgcc/patches: facilitate successful build of ipxe
New changes in the latest binutils 2.32 lead to assembler errors causes
ipxe build failure. IPXE uses the divide test which requires /dev/null as
input as well as the output file name.

This patch facilitates the /dev/null as an exception to the current
changes in binutils package while building crossgcc for coreboot leads to
successful build of ipxe and further tests to pass based on /dev/null and
applies automatically during the crossgcc rebuild.

Also, this can be reverted once binutils/ipxe provides an updated release
in this respect.

Fixes: https://ticket.coreboot.org/issues/204

Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35098
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 16:30:15 +00:00
Maxim Polyakov 9af10bf90f util/inteltool: Add server 5065x CPU model support
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).

The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.

These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-10-22 12:56:20 +00:00
Nico Huber e1b902c92c util/chromeos: Don't hide error output
Change-Id: Idf29275575ca7965a0df98dbc8f2b27ab9c5ec4d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-10-22 12:54:55 +00:00
Marshall Dawson 0581bf6a75 util/amdfwtool: Add holding locations for more APCBs
Increase the number of potential APCB images to 5 by adding to the
amd_bios_table.  New instance IDs are from 0 to 4.  The backup APCB
block (type 0x68) still supports only instance ID 0.

Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20 22:09:47 +00:00
Arthur Heymans 4cb888e946 util/ifdtool: Add support for setting flash density on IFD V2
Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-19 17:04:42 +00:00
Philipp Deppenwiese 7ba58718de util/cbfstool: Add optional argument ibb
* Mark files in CBFS as IBB (Initial BootBlock)
* Will be used to identify the IBB by any TEE

Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18 15:37:37 +00:00
Raul E Rangel 9ff4029db9 util/abuild: Have abuild generate the .xcompile if it doesn't exist
Previously if .xcompile was missing, abuild would silently ignore the
error. With https://review.coreboot.org/c/coreboot/+/34241 we now check
the return code so abuild started failing.

We should generate the .xcompile if it doesn't exist. The Makefile will
handle that so we include it as the first Makefile.

We then need to override the default target so we don't use the one from
the Makefile.

BUG=b:112267918
TEST=ran abuild and made sure it generated a .xcompile in the root.

Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-17 21:37:32 +00:00
Samuel Holland dc9025c14d util/ifdtool: Fix argument parsing for layout/validate
When `mode_validate` was added, a second copy of `mode_layout` was
accidentally added to the multiple-mode-argument check instead. This
prevents `-f` from working. Fix the check to reference the correct
variable.

Change-Id: Ibac6f090550ff63ec9158355b0450da204a300a7
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16 08:31:19 +00:00
Marshall Dawson 94f249254f util/amdfwtool: Grow the Embedded Firmware Structure
Ensure adequate space exists for all Embedded Firmware Structure
fields.

Field definitions are NDA only.  See PID #55758 "AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors".

BUG=b:141790457
TEST=run on Mandolin

Change-Id: I098ffc7c05d27387a877e6b7c8628d98939bd9af
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35667
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-16 02:29:07 +00:00
Maxim Polyakov 4fb80753f5 util/inteltool: remove unsupported MSRs for 06_9EH
Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:56:23 +00:00
Maxim Polyakov 9ebf5317bc util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH
Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:53:35 +00:00
Maxim Polyakov 3e7ff29995 util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr
According to the documentation [1], IA32_PLATFORM_ID MSR register
address should be 17H.

[1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s
    Manual. Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:42:47 +00:00
Maxim Polyakov 43a98b9589 util/inteltool: remove duplicate MSR for 06_9EH
Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:40:58 +00:00
Nico Huber 17e9bcb9b8 util/sconfig: Issue header for exposed PCI and PNP names
Let `sconfig` output a C header file with the symbol names that we
generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP
device names).

We add another command line argument for the path to the header
file. As the file is similar in nature to our `config.h` we simply
put it in $(obj)/ too.

Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-05 02:43:23 +00:00
Mathew King c7ddc999fc ifdtool: Add validate option to ifdtool
Add an option to ifdtool which validates that the flash regions defined
in the descriptor match the coresponding areas in the FMAP.

BUG=chromium:992215
TEST=Ran 'ifdtool -t' with a good bios image and verify no issues
     run 'ifdtool -t' with a bad bios image and verify expected issues

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:28:15 +00:00
Martin Roth ce005dac68 util/release: add gerrit stats script
This tool downloads, caches and analyzes commits pushed to gerrit
for a specified range of commits.  Currently it only works over SSH.

Data that is printed about the range of commits:
CSV Data about each individual commit:
- Commit ID
- Commit Date
- Author
- Commiter
- Submitter
- Lines added
- Lines removed
- Title
- Reviewers

It then prints the analysis it did on the data:
- Total Commits
- Total lines added
- Total lines removed
- Total difference
- Authors - Number of commits
- Total Authors
- Authors - Lines added
- Authors - Lines removed
- Reviewers - Number of patches reviewed
- Submitters - Number of patches submitted

The script relies on a number of perl modules
which must be installed separately.

Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 02:12:45 +00:00
Stefan Reinauer f5fa96f9c3 buildgcc: Run aclocal before configure
Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts
are not regenerated because 19.04 ships with 1.16.
There are not enough eyes to roll when working with GNU autotools.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 02:06:35 +00:00
Martin Roth f47c32a12d util/crossgcc: Add patch for __alloca missing on ubuntu 18.04
Bring this over from the HEADS repo.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 02:06:30 +00:00
Paul Fagerburg 4ab023329d util/mb/google/hatch: update CRC calculation for correctness
The CRC result is treated as a signed value, and so in certain
situations, the calculated value for the last four digits will not
be correct. Ensure that the CRC is treated as an unsigned 32-bit
value prior to converting the last 4 decimal digits to a string.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I92f9ce1ceb7450f90b89c94e0ace6f79a9419b42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35604
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:43:28 +00:00
Paul Fagerburg 39f3f52b3e util/mb/google/hatch: script can take optional bug parameter
When creating a new variant, adding a bug parameter after the name
of the variant will populate the BUG= field in the commit message.
If the parameter is not present, then BUG=None.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I3e08df5d80a5684c9f3675e3c0a8346240171cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-30 11:42:17 +00:00
Paul Fagerburg cad708d210 util/mb/google/hatch: fix style issues in shell script
* Use all caps for variables.
* Use a single exit code for failures.
* No need to popd before exiting the script.
* Do ${var,,} and ${var^^} into variables instead of using it everywhere.
* Add more punctuation in comments.
* Specify LC_ALL=C so that upper/lower case show the desired behavior.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I63aa0aa633f36b9543e809fc42fac955da5960a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-30 11:42:01 +00:00
Hung-Te Lin 117453e890 vboot: create board-specific test-only GBB HWID if not set
The HWID in vboot GBB is an identifier for machine model. On Chrome OS,
that should be provisioned in manufacturing process (by collecting real
hardware information), and will be checked in system startup.

For bring up developers, they usually prefer to generate a test-only
string for HWID. However that format was not well documented and cause
problems. Further more, most Chromebooks are using HWID v3+ today while
the test-only HWID is usually v2. Non-Chrome OS developers may also
prefer their own format.

To simplify development process, the GBB_CONFIG now defaults to empty
string, and will be replaced by a board-specific test-only v2 HWID
automatically. Developers can still override that in mainboard Kconfig
if they prefer v3 or other arbitrary format.

BUG=b:140067412
TEST=Built 'kukui' successfully. Removed kukui GBB config and built
     again, still seeing correct test HWID.

Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30 11:33:20 +00:00
Hung-Te Lin 544bc2693a util/chromeos: revise description for more utility scripts in future
The description.md and README.md was explicitly made for downloading or
extracting some resources, but we need to add more Chrome OS related
scripts soon; so the description should be revised.

Also changed README.md for better markdown style, for example
 - Use #, ## to replace the old '-' headers
 - Use code format for file names
 - Use code block for example of shell execution

Change-Id: Icc3677fa318b03f4aee1b0f5fb13b2095f2afe64
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30 11:09:22 +00:00
Alexander Couzens 3b8deeefa5 superiotool: add basic support for SCH5545
Based on the SCH5627 datasheet which is similiar
SCH5545 id 0xc4, SCH5627 id 0xc6.

Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28 18:39:10 +00:00
Edward O'Callaghan da33246bc5 util/mainboard/google: Fix hatch variant script
The script had a couple of bugs:
 * It didn't create the required directory under variants/
 * It was treating the wildcard as literal and so couldn't
   find variant files to copy.

V.2: Drop verbose cp && fixup wild card usage.

Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-09-25 13:31:03 +00:00
Furquan Shaikh d1a4a7a7fa util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKE
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig,
utility to create a new variant does not need to do that anymore in
Kconfig.name

Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25 12:56:13 +00:00
Angel Pons ce828b6ae8 util/lint: make clang-format non-fatal
The current clang-format configuration is completely broken. It forces
one to change the code style of patches before pushing them, only to
find out that checkpatch now complains about it. This means newcomers
get scared away, and developers only get angered and frustrated about
it, and end up working around clang-format's requirements anyway.

For now, make clang-format's complaints non-fatal, reducing them to text
noise. However, since clang-format is currently unusable, reverting it
out would be preferred.

Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-19 10:20:50 +00:00
Paul Fagerburg b4eb02aa8b hatch: automate creating a new variant in coreboot
To create a new variant of the hatch baseboard, we need to
add the variant's GBB_HWID and other information to Kconfig
and Kconfig.name, and set up a skeletal build based on the
hatch baseboard.

BUG=b:140261109
BRANCH=none
TEST=``./create_coreboot_variant.sh sushi && git show``
Kconfig will have three new lines for the SUSHI variant, and
Kconfig.name will have an entirely new section.
New files created are:
variants/sushi/Makefile.inc
variants/sushi/overridetree.cb
variants/sushi/include/ec.h
variants/sushi/include/gpio.h
variants/sushi/include/variant/acpi/dptf.asl

Also run the script with an existing board name to verify that you
can't create a variant that already exists.

Change-Id: I1a5b9c8735faafebb2e4e384cb3346867d64c556
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-19 09:37:12 +00:00
Sellerie 409a5dc8af util/inteltool: Add Intel HD 4400 (Haswell IGD)
Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.

It is found on the ark page of e.g. the Intel i3-4130 CPU.

Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 17:18:22 +00:00
Manoj Gupta 297e9c826f futility: Use HOSTPKGCONFIG for host PKG_CONFIG
futility is built for the host. However, when cross-compiling,
the target's pkg-config is called to get the library paths which
can add paths from the cross-compilation tree instead of host.
e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config
. /build/elm/usr/bin/pkg-config adds the paths specific to the
cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib.

This causes linker to complain that files in library paths do not
match the architecture. BFD produces a warning while LLD errors out.

Fix this by passing PKG_CONFIG from host when building futility.

BUG=chromium:999217
TEST=coreboot builds
BRANCH=None

Cq-Depend: chromium:1778519
Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 20:41:47 +00:00
Elyes HAOUAS 9890bd98b0 crossgcc: Upgrade CMake to 3.15.3
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html

Change-Id: Id3283b4a091a5a8afd76235059636bba1c238f0f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:55:18 +00:00
Kyösti Mälkki 5e2a2cd5e7 util/sconfig: Expose usable PCI and PNP device names
These devices can be accessed directly by symbolname,
without a search and walk through the tree, as they
have static paths.

Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31933
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 00:18:29 +00:00
Maxim Polyakov 1317689066 inteltool: Add Skylake Xeon E DMI3 Host bridge Id
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O

Change-Id: I4b429536fc2db16d770120487e4c383da437593a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 15:00:04 +00:00
Maxim Polyakov b89ce2e1b4 inteltool: add Lewisburg C62x GPIOs support
These changes are in accordance with the documentation:
[*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass

Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 14:59:09 +00:00
Maxim Polyakov ec32e61bb8 inteltool: add Lewisburg family C62x chipset PCI IDs
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-04 08:16:04 +00:00
Raul E Rangel 7b2deddbb0 Kconfig: Write tmp files into same directory as target files
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the
original files will be replaced with the tmp file, the parent directory
already needs to be writable.

Before this change, the tmp files would be created in the CWD (src) if
COREBOOT_BUILD_DIR was not specified.

BUG=b:112267918
TEST=emerge-grunt coreboot and verified no tmp files were created in the
src directory.

Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30 10:42:29 +00:00
Raul E Rangel d2f90a0659 kconfig: Use config's full path when generating tmp file
If KCONFIG_CONFIG is set to a full path, we should generate the tmp file
in the same directory instead of the current working directory.

BUG=b:112267918
TEST=emerge-grunt coreboot and verified with print statements that the
correct path was used.

Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-30 10:41:38 +00:00
Raul E Rangel 4007d7f8c7 Makefile: Pass .xcompile into genbuild_h
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.

BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.

Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28 18:29:15 +00:00
Patrick Georgi 3beb108a62 what-jenkins-does: Use abuild's -Z option
This reduces disk usage during builds by removing all object files and
other intermediate files directly after a build instead of waiting for
the entire build to pass.

Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 16:30:04 +00:00
Patrick Georgi 93bcebcfff abuild: Add -Z / --clean-somewhat option
This option removes everything in the build tree but coreboot.rom,
config.build, config.h and make.log - a useful subset of the tree for
further testing.

Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 16:30:00 +00:00
Patrick Georgi 19e1d631e3 what-jenkins-does: keep essential artifacts arounds
Keep for every board: coreboot.rom, config.h, config.build

That way these can be used in follow-up jobs.

Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-26 21:55:47 +00:00
Jacob Garber 1b7b7a3697 mb,autoport: Fix GCC 9 Port_List build error
Port_List is an array of 8 elements, and GCC 9 is warning that there
are no 'others' when all 8 elements are explicitly initialized, which is
causing the build to fail. Remove the 'others => Disabled' clause to
silence this.

Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20 15:31:54 +00:00
Jacob Garber 4f387e1240 util/nvidia/cbootimage: Update to upstream master
This brings in 4 new commits from the upstream repository.

65a6d94 Free image buffer on read error
9de64c7 Fix various abort(), crashes, and memory errors
7c9db58 Bump to version 1.8
3b3c3cc Use C99 uintXX_t instead of implementation-specific u_intXX_t types

Change-Id: If949309a7481537de6529c205fe745d5509906a9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20 15:28:49 +00:00
Jacob Garber 5fa756cc97 util/cbfstool: Remove unused assignment
This variable is overwritten on one branch of the next if statement, and
the other branch returns, so this assignment does nothing.

Change-Id: I63737929d47c882bbcf637182bc8bf73c19daa9f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20 15:20:30 +00:00
Matt Parnell 063b162008 util/superiotool: add IT8987 detection and register support
Signed-off-by: Matt Parnell <mparnell@gmail.com>

Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-08-19 10:36:17 +00:00
Raul E Rangel cccb815c5e util/abuild: Clean up the missing_arches check
This change adds the following improvements:
* Easier to read.
* Checks to see if .xcompile is complete.
* Checks the make return code. This will catch if .xcompile is missing.

BUG=b:112267918
TEST=Modified my .xcompile and ran abuild and verified that
missing_arches got set correctly. Also deleted .xcompile and verified
there was a failure.

Change-Id: I7604d431f398fc0c80a857a0c7c21e164004cc99
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-08 03:42:24 +00:00
Arthur Heymans 3071c8114a util/arm_boot_tools/mksunxiboot: Remove tool
Support for allwinner sunxi was dropped.

Change-Id: I0d4cbcac3e96e381185338455a773bcccc3401ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34688
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05 08:27:40 +00:00
Martin Roth 0baad5ad6d util/nvidia: Change ENODATA to ENOATTR for FreeBSD
FreeBSD doesn't have ENODATA defined, so the cbootimage utility wouldn't
build.  It looks like the BSDs use ENOATTR in the same fashion, so
update the error to use that.

Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-08-03 17:20:42 +00:00
Raul E Rangel c989e0bd56 util/abuild: Use realpath for FAILED_BOARDS/PASSED_BOARDS
The abuild script will `cd` into the build directory. FAILED_BOARDS
defaults to a relative path, so it ends up trying to echo into a
directory that doesn't exist.

If we set the realpath to the file then we can correctly update the
failed/passed boards file.

BUG=none
TEST=make what-jenkins-does and verified there was a failed_boards and
passed_boards in coreboot-builds.

Change-Id: Ib3af003b090668380a9425583a9f4367023820a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-03 17:11:17 +00:00
Felix Singer f98dc48386 inteltool: Add GPIO support for Skylake-H chipsets
PCH IDs:
  - H170, Z170, Q170, Q150, C232, QM170, HM170

Used documents:
  - Intel 332690-005EN

Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31 18:06:07 +00:00
Patrick Georgi fa781fa52c util/release/genrelnotes: Emit more markdown-ish output
It's better to format lists with bullet points.

Change-Id: I503ef2dea9146d67c220236b8a5b64c2ba2d794f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34504
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31 08:47:24 +00:00
Patrick Georgi b11a342703 util/release: Make sure intel-microcode ends up in the blobs tarball
Change-Id: Ib41c196cf543070e237d240cf31e019c9b2bf339
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34503
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31 08:47:21 +00:00
Pavel Sayekat 9429b70f91 util/inteltool: Add H110 GPIO support
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 18:06:13 +00:00
Marshall Dawson b85ddc5d44 util/amdfwtool: Correct fletcher32 algorithm
Change the fletcher32 checksum calculation to match PSP and AGESA
implementations.

The symptom of the failure has only been noted in Picasso's BIOS
Directory Table, when a BIOS binary image of different sizes were
passed to amdfwtool.  The PSP halts the boot process with the bad
BDT checksum, and if allowed to continue, AGESA asserts later due
to a failed BDT verification.

This version has been verified to produce the same result as found
at https://en.wikipedia.org/wiki/Fletcher%27s_checksum.

TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom
     is unchanged.

Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-29 05:58:08 +00:00
Martin Roth 57e257d987 util/abuild: Add asserts flag to getopts
We recently added the --asserts option to set asserts as fatal in abuild
but didn't add the flag to getopts, so it gets rejected as an invalid
argument.

Change-Id: Ic70e9a2bec039955cf62c175875598773ade2d3d
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-28 09:58:20 +00:00
Patrick Georgi 99f0e0c4dc util/testing: Allow adding abuild options to what-jenkins-does
JENKINS_ABUILD_OPT is passed in abuild's command line

Change-Id: I5e7fbb77a3c6592a4414a6c1e3f7556c7e3a824c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:07:01 +00:00
Patrick Georgi 3a0cad30f2 util/abuild: Add --asserts flag
This enables fatal asserts, which can be useful to get better
diagnostics by the build tools (both compilers and static analysis.)

Change-Id: I1e1653f465fe1f545878d6eec83b8645dc17d9cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:06:29 +00:00
Patrick Georgi c199973f78 util/testing: Factor out abuild options in what-jenkins-does
The abuild command line can vary a lot depending on options and the line
became unwieldy (plus, it's on two lines because we run abuild twice),
so factor it out into a variable.

Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:06:22 +00:00
Nico Huber 517ed8b0e4 xcompile: Store XGCCPATH
It can be useful to pass along to external projects, e.g. payloads.

Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 20:18:52 +00:00
Martin Roth d70f5fae1c crossgcc: Add nasm to toolchain
Tianocore payload uses nasm.  Supply it in the coreboot toolchain
instead of relying on system version.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 19:05:22 +00:00
Elyes HAOUAS 1662c0bbfe crossgcc: Upgrade CMake to 3.15.0
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html

Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33053
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:41:23 +00:00
Elyes HAOUAS 43e9bd6b9c crossgcc: Upgrade acpica to version 20190703
Changes: https://acpica.org/node/171

Change-Id: I3883718623e4a23a901a446f738a9e8c988d8433
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 18:40:56 +00:00
Elyes HAOUAS 1e9473cc25 crossgcc: Upgrade Expat to version 2.2.7
Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33825
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:33:01 +00:00
Elyes HAOUAS 7e3eab2c13 crossgcc: Upgrade Python to version 3.7.4
Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:32:39 +00:00
Elyes HAOUAS 31270646ba crossgcc: Upgrade GDB to version 8.3
Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32754
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:28:00 +00:00
Jacob Garber 52f0e84ba7 util/*/Makefile: Rename -W to -Wextra
-W is the old name for -Wextra, so let's rename it to be consistent with
the rest of the utility Makefiles.

Change-Id: I0e50f13d2617b785d343707fc895516574164562
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-23 09:10:47 +00:00
Jacob Garber 3a82e9b8a3 util/cbfstool/flashmap: Fix memory leaks on failure
Fix several memory leaks on failed printing or tests. These don't matter
much, but it keeps Coverity happy.

Change-Id: Ie750acb50ae1590c3aea533338a8827c03459c1a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 130245{1,2,3}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-21 18:54:43 +00:00
Patrick Rudolph b30a47b841 sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.

We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.

Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.

Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19 15:06:23 +00:00
Kyösti Mälkki 1557a67c83 device: Move pci_irqs outside DEVTREE_EARLY
Only needed in ramstage, and only for MP tables.

Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17 16:05:28 +00:00
Jacob Garber 198c2e63ac util/inteltool: Shrink buffer size
512 bytes is much too big for this buffer, which only needs to hold a
path that will have a length of at most 20. The large buffer size also
triggers a -Wformat-truncation warning with GCC since it is later
printed into the smaller temp_string array, so shrink it down to
something reasonable.

Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-16 16:25:11 +00:00
Martin Roth d3ce8c8442 util/amdfwtool: Add option to build verstage binary into the PSP
For AMD's Family17h processors, verstage needs to be run in the PSP,
before memory is initialized.  This adds that binary into the PSP
directory.

See the Family17h documentation in the coreboot documentation directory
for more information.

BUG=b:137338769
TEST=Build, add test binary to mandolin board, boot

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15 17:47:04 +00:00
Martin Roth ec933135ce util/amdfwtool: Do misc cleanup
- Correct command line argument for microcode patches from -u to -O
- Add #if PSP_COMBO around new_combo_dir() as it's only called when
that's enabled.
- Remove unused variable in integrate_bios_firmwares()
- Correct enum type from amd_fw_type to amd_bios_type in
register_fw_addr()

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15 17:46:46 +00:00
Keith Short 31af70dd96 util/testing: Ensure coreboot-gerrit fails if libpayload build fails
The JUnit output from the libpayload builds was getting deleted by the
coreinfo build.  Move the libpayload to later in the coreboot-gerrit
job.

Also add messages to stdout indicating the various libpayload configs
that are built and a message indicating when all libpayload builds are
complete.

BUG=b:137380189
TEST=Upload test commit that includes a libpayload compile error and
verify buildbot fails.

Change-Id: I43b55f402216582dcf81be34171437be345572ab
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 18:33:51 +00:00
Maxim Polyakov aae7552b24 util/superiotool/aspeed: fix SUART number
Change-Id: I20c4436d414bc6b9a3ff5138d6fd59ead8fd4a47
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-12 12:27:45 +00:00
Werner Zeh ac14a40d0e util/sconfig: Fix compile error with older glibc-headers
In patch e29a6ac16a (util/sconfig: Add
commonlib/helpers.h) helpers.h has been added to the include-list.
In headers.h we have a definition for __unused:

On a host system environment where glibc-headers-2.12-1.212 is
installed, a file included by <sys/stat.h> called bits/stat.h have the
following content on line 105 and onwards:

	long int __unused[3];
where the mentioned part is part of the structure called struct stat.

If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for
__unused will be defined by the preprocessor to be
'__attribute__((unused))', therefore the above mentioned structure member
will be expanded by the preprocessor to be
'long int __attribute__((unused))[3];', which is not a valid C syntax
and therefore produces a compile error for sconfig tool.

To handle this case we need to make sure commonlib/helpers.h is included
_after_ <sys/stat.h>. As the needed part of stat.h (which is
struct stat) is only used in main.c it is safe to move the include from
sconfig.h directly into main.c while taking care of the order.

Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12 11:02:29 +00:00
Jacob Garber 967f862e47 util/amdfwtool: Close file descriptor on error
Prevents a resource leak.

Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:41 +00:00
Jacob Garber 3dbaf4f336 util/romcc: Correct format specifiers
The right specifier for printing ptrdiff_t is %td.

Change-Id: I7bae4d47f15cfe85ca870f687c6f702339f680bb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 14021{64,68,76}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:23 +00:00
Jacob Garber 2e31ea05bb util/cbfstool: Close file on error
Prevents a resource leak.

Change-Id: I032227228c8e37e989960ad6292ded39b81835a9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1383919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:00 +00:00
Kyösti Mälkki e29a6ac16a util/sconfig: Add commonlib/helpers.h
Followup work injects ARRAY_SIZE() in static.c

Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-10 10:18:13 +00:00
Kyösti Mälkki 5ccce7cdc7 util/sconfig: Declare the repeated devicetree storage
With DEVTREE_EARLY we could create incomplete device
objects with topology links removed to reduce footprint
for bootblock.

Declare everything with 'static __unused DEVTREE_CONST'
to avoid compiler errors and to not expose unusable
device object names to global scope.

Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 10:17:48 +00:00
Nico Huber 45564050ec crossgcc: Fix runtime initialization of a constant
GNAT had a constant initialized at runtime which led to trouble
with compilers that decided to place it into an actual constant
section (e.g. GCC 9). Usually, this would be handled gracefully
if the Ada compiler knew about the runtime initialization. How-
ever, as the initialization was done by taking the address of
the variable, the compiler had no clue.

Change-Id: I73ce4cadc612c814ed2e22b44f429af2ad3db288
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34147
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 10:42:08 +00:00
Patrick Rudolph 674bb3bf65 util/superiotool: Add AST2400
Add support for AST2400 Super I/O.

The device doesn't have an ID register, so probe for scratch register
not to read as 0xff.

Tested on platform which has an AST2400.

Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-08 16:13:29 +00:00
Jacob Garber 2d58bf6a03 util/cbfstool: Prevent overflow of 16 bit multiplications
Considering the following integer multiplication:

    u64 = u16 * u16

What on earth, one might wonder, is the problem with this? Well, due to
C's unfortunately abstruse integer semantics, both u16's are implicitly
converted to int before the multiplication, which cannot hold
all possible values of a u16 * u16. Even worse, after overflow the
intermediate result will be a negative number, which during the
conversion to a u64 will be sign-extended to a huge integer. Not good.

The solution is to manually cast one of the u16 to a u32 or u64, which
are large enough to not have any overflow and will prevent the implicit
conversion. The type of the u64 is preferred, though a u32 is used
instead of size_t, since that can change depending on the platform.

Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07 20:59:04 +00:00
Jacob Garber 96e0ce30db util/nvramtool: Mark out_of_memory() as noreturn
This silences several false positives from scan-build.

Change-Id: I327a967c75d6aeec0b3aba16ee696dbae8cf997d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07 20:55:59 +00:00
Jacob Garber b592917dcf util/nvramtool: Enable -Wmissing-prototypes
Change-Id: Id751250b07a495dc25293ff703602bfefa9011bd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:54:04 +00:00
Jacob Garber f2a2137ae2 util/nvramtool: Make internal function static
This function is only used in this file, so it can be made static.

Change-Id: I90e673da91eb926424d1730c268860da7fa1627b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:26:44 +00:00
Jacob Garber 4177bedd65 util/nvramtool: Include missing header
The prototype for is_ident() is in this header, so include it.

Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:26:25 +00:00
Jacob Garber 57f2188d86 util/inteltool: Enable -Wmissing-prototypes
Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:23:55 +00:00
Jacob Garber 6faccd1f00 util/inteltool: Make internal functions static
None of these functions are used outside of the files they are defined
in, so they can all be static.

Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:23:42 +00:00
Marshall Dawson 30cf155168 util/cbfstool: Add AMD BIOS compression tool for PSP
Add a utility to generate a compressed BIOS image for AMD Family 17h.

If the input is an elf file, the utility extracts the program portion
for compression.  Otherwise the file is compressed as-is.

In modern AMD systems, the PSP brings up DRAM then uncompresses the
BIOS image into memory prior to x86 beginning execution.  The PSP
supports a zlib engine, and interprets the first 256 bytes as a
header, where offset 0x14 containing the uncompressed size.  For
further details, see AMD Platform Security Processor BIOS Architecture
Design Guide for AMD Family 17h Processors (NDA only, #55758).

BUG=b:127766506
TEST=Use with WIP Picasso

Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-03 21:28:43 +00:00
Patrick Georgi 848e30daa1 cbfstool: show "preserved" flag in cbfstool layout output
The flag is useful for updaters to determine which areas to leave
alone, such as VPD (vital product data) regions that are set in
factory and might contain unique (MAC addresses) or hard to obtain
(calibration output) data.

It's also useful to see which regions are marked as such.

Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 18:48:02 +00:00
Jacob Garber 0476332161 util/cbmem: Enable -Wmissing-prototypes
Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:12:21 +00:00
Jacob Garber 79a2f4767d util/cbmem: Make internal functions static
These functions are only used in cbmem, so they can be made static.

Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:12:09 +00:00
Jacob Garber 4d543b5aa6 util/cbmem: Enable -Wextra
This enables extra useful warnings.

Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:11:57 +00:00
Jacob Garber 414d5d8698 util/cbmem: Use correct integer types for loop indices
Make sure that the type of the loop index matches the type of the upper
bound. This fixes several -Wsign-compare warnings.

Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:11:46 +00:00
Patrick Georgi 328d2e2a7d util/docker/coreboot.org-status: Add more "nice" names for CPUs
It's not perfect and we'll need to find a better place for that,
but I'll look into that as part of the big board-status rework.

Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:08:18 +00:00
Patrick Georgi 3b34ef29b3 util/release: add more categories
Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:08:05 +00:00
You-Cheng Syu 1430b3995f util/cbmem: Update banner string regular expression
Banner string format has been changed (CB:30935). We should update our
regular expression correspondingly.

Also add "verstage" into the stage search list since some boards (e.g.,
Kukui) might start console initialization at verstage.

Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-01 21:21:57 +00:00
Jacob Garber 02b1e20f00 util/ifdtool: Enable -Wmissing-prototypes
Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01 14:30:53 +00:00
Jacob Garber 595d926bc2 util/ifdtool: Make internal functions static
These functions are only used in ifdtool, so they can be made static.

Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01 14:30:42 +00:00
Pandya, Varshit B 36cc664bc7 util/cbfstool/ifittool: use strtol function instead of atoi
Fix error "Invalid option -A" by adding "A" to options list.

Also, atoi does not parse hex string, for instance 0x200 is interpreted as 0,
and this causes a failure when updating second FIT table using -j option.
Use strtol instead of atoi

BUG=none
BRANCH=none
TEST=Build and boot hatch after enabling dual bootblock feature.

Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-01 13:44:48 +00:00
Pavel Sayekat 40dc75efcb util/superiotool/nuvoton.c: Minor tag update/removal
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-01 08:30:44 +00:00
Joel Kitching b4a1981289 cbfstool/fit: need inttypes.h for PRIx64
This is causing coreboot build in Chromium OS to fail.

BUG=None
TEST=emerge-eve coreboot
BRANCH=none

Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-26 09:19:00 +00:00
Elyes HAOUAS 741000d31b util/cbfstool/flashmap: Correct local includes
Change-Id: I78ba7afd2085c7e9c93e892470111bfee154bb04
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-24 10:52:53 +00:00
Patrick Rudolph 9ab80a33a5 cbfstool: Drop update-fit option
The ifittool is used instead. Drop old code.

Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-24 09:45:00 +00:00
Philipp Deppenwiese 5ada0023d1 cbfstool: Add ifittool
Add the IntelFirmwareInterfaceTable-tool to modify the FIT.
As cbfstool is overloaded with arguments, introduce a new tool
to only modify FIT, which brings it's own command line syntax.

Provide clean interface to:
* Clear FIT
* Add entry to CBFS file
* Add entry to REGION
* Delete entries
* Add support for types other than 1
* Add support to dump current table
* Add support for top-swap
* Sort entries by type

Most code is reused from existing cbfstool and functionality of cbfstool
is kept. It will be removed once the make system uses only ifittool.

Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout"
and https://github.com/slimbootloader/slimbootloader .

Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-24 09:42:31 +00:00
Arthur Heymans 6beaef983a sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.

Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21 09:00:57 +00:00
Nico Huber 6d7564cdfe Move -Wlogical-op into xcompile
Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where
we can easily distinguish between the two. However, this requires us to
split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`.

Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:44:49 +00:00
Marshall Dawson ce2b2bad77 util/amdfwtool: Update for Family 17h
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.

Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.

Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-19 19:14:39 +00:00
Nico Huber c6a584182e xcompile: Fix harmless typo
As CFLAGS_GCC and CFLAGS_CLANG are still the same at this point, this
just removes some duplicate flags.

Change-Id: I532e5fa146891b70e4c1949c614b280055524593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-19 11:27:09 +00:00
Pavel Sayekat cc48009631 util/superiotool/nuvoton.c: add NCT5539D register dump
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015).
Tested on ASUS-H110M-E/M.2 mainboard (Kabylake i3-7100 CPU).

Change-Id: Ib55068035ca574b22d0fea81e1a291f7cf0329d3
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-14 12:17:26 +00:00
Patrick Georgi 7945f75417 lint/clang-format: set to 96 chars per line
coreboot has decided to go with 96 characters per line.

Original Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651

Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-13 20:14:00 +00:00
Marshall Dawson 24f73d4f53 util/amdfwtool: Add multilevel PSP directory table
Add the ability to generate two PSP directory table levels.  The PSP
is capable of supporting two levels, with the primary intended to
remain pristine for the life of the system, and the second updatable.
In the event the second becomes corrupted, the primary is still
sufficient to allow a recovery of the other.

This patch modifies no directory table structures currently in use.
The soc or southbridge must pass an argument to force building the
secondary table.

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:01:07 +00:00
Marshall Dawson 7c1e1428ad util/amdfwtool: Align PSP NVRAM
Align the PSP's NVRAM item since it's intended to be updateable
in the flash device.

Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:00:27 +00:00
Marshall Dawson ef79fccf4e util/amdfwtool: Add argument for soft fuse override
Allow the soc build to pass a soft fuse value to the utility.  This
helps maintain compatibility across PSP generations.

Add a generic 'other' item to the amd_fw_entry structure that may
be used by non-fuse entries in the future.

TEST=Verify google/grunt amdfw.rom unchanged before and after.
     Compare internal board using override before and after.

Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-13 18:00:05 +00:00
Felix Held e5b05d61df util/superiotool: clarify usage of MISC and NANA defines
Change-Id: I0b3c5c810bfb05eaec13511391ecd55d7b9eb4e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13 14:07:57 +00:00
Iru Cai cd980abe18 autoport: Generate a libgfxinit template when IGD is detected
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-09 17:10:44 +00:00
Duncan Laurie 7775d67218 ifdtool: Enable GbE/PDR/EC region access only if they exist
Instead of assuming GbE/PDR/EC regions may exist or not, check if there
is a valid region defined in the descriptor and set the region access
permissions based on that.

The net effect change is to enable the use of the PDR region on the
sarien platform, which also uses the GbE and EC regions.

This results in the following example changes:

mb/google/sarien (GbE, PDR, EC)
.      DESC BIOS ME GbE PDR EC
-BIOS  r    rw      rw      r
-------------------------------
+BIOS  r    rw      rw  rw  r

mb/google/eve: (no GbE, no PDR, no EC)
.      DESC BIOS ME GbE PDR EC
-BIOS  r    rw      rw      r
-ME    r         rw r
-GbE   r            rw
-EC    r                    rw
-------------------------------
+BIOS  r    rw
+ME    r         rw
+GbE
+EC

BUG=b:134703987

Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07 20:51:27 +00:00
Nico Huber ec017590e5 util/lint: Make usage of IS_ENABLED() an error
As long as we keep the IS_ENABLED() definition in libpayload for
compatibility, we should check that IS_ENABLED() usage doesn't
sneak back in.

Also remove all other IS_ENABLED() checks.

Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04 13:16:16 +00:00
Nitheesh Sekar 6681f05373 qcs405: util/qualcomm: Add T32 debug scripts
Add T32 scripts that allow debug of any coreboot stage
on qcs405.

Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:20:38 +00:00
Damien Zammit 9b5e8c1718 xcompile: Remove --rtlib switch from clang CFLAGS
Fix the following error from clang invoking gcc linker with wrong arg:

i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1

Just remove --rtlib switch from CFLAGS relating to clang

Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29 20:33:35 +00:00
Evgeny Zinoviev 3d90d3bfce util/autoport: Add info about rank 1 mirroring
inteltool can't detect whether address mapping is normal or
mirrored, which in turn may be cause RAM initialization to
fail when using spd.bin generated by inteltool.

Mention this in readme as it may help someone.

Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29 20:07:10 +00:00
Alan Green 1470c7367b util/xcompile/xcompile: apply -march to clang as well as gcc
For x64 and x86_32 configurations, apply the -march flag to both GCC and
Clang flags.

This solves the problem of Clang-compiled coreboot failing due to Clang
emitting SSE instructions for code that is executed while SSE is not
enabled.

This patch takes functionality targeted for GCC configurations and moves
it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order
that it applies to both GCC and Clang.

This is an alternate patch to CB:32887.

Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-28 20:33:37 +00:00
Jacob Garber 298afb3140 util/romcc: Add extra null pointer check
It is possible that 'lnode->val' is set to 0 on a previous iteration of
the loop, so check that it is non-null here before dereferencing it.

Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:02:18 +00:00
Jacob Garber 9742ae1d11 util/romcc: Fix memory leak
The 'new_type' function already allocates memory, so it is only
necessary to clone the existing type if this function is not called.

Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity Scan CID 1129106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:02:07 +00:00
Jacob Garber 4b688ab3fe util/romcc: Add null check for filename
It is possible that 'filename' is still null in this if statement,
so we add an extra check to prevent a null dereference in strcmp.

Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1395330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:01:57 +00:00
Jacob Garber b4222a65ad util/romcc: Add extra NULL checks for member
In each of these cases it is possible that 'member' is NULL at the
beginning, which will skip the earlier while loops entirely and cause
a NULL dereference later on. Add extra error checks to prevent this.

Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:01:42 +00:00
Evgeny Zinoviev 7687617d00 util/autoport: Mention i2c-i801 module in readme.md
SMBus adapter will not appear if i2c-i801 module is not loaded.
Added it to the readme.

Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-23 08:59:48 +00:00
Elyes HAOUAS fa40e82270 util/sconfig: Move 'static' at beginning of declaration
When using -Werror=old-style-declaration, gcc reports an error:
"'static' is not at beginning of declaration"

Tested on 945G-M4 board.

Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:09:33 +00:00
Jacob Garber 9b0d8e7a1f util/romcc: Prevent out-of-bounds read
If 'class > LAST_REGC', then there will be an out-of-bounds read when
accessing 'regcm_bound'. Prevent this by skipping to the next iteration
of the loop. Note that this should not generally happen anyway, since
'result' represents a bitset for the indices of 'regcm_bound', and so
iterations where 'class > LAST_REGC' should already be skipped by the
previous continue statement (since those bits of 'result' should all be
zero).

Found-by: Covericy CID 1129122
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:03:11 +00:00
Jacob Garber ae8301fddb util/romcc: Fix parsing of empty string literal
The corner case of an empty string literal was causing romcc to
segfault. This checks if the literal is empty, and if so allocates a
size one buffer for the terminating null character. A test case for
this is added to ensure it doesn't happen again.

Found-by: Coverity CID 1129099
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:28:36 +00:00
Jacob Garber b79d2dee2b util/romcc: Free variable after it is used
Free 'arg_type' after it is used to prevent a memory leak.

Found-by: Coverity Scan CID 1129114
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:27:57 +00:00
Jacob Garber 40a85f85c6 util/romcc: Use 64 bit integers when shifting
'used_indices' is 64 bits wide, so use a fixed-width type to make
that clear. As such, 'index' can have a value of up to 63, so use a
64 bit integer when doing the shifts to prevent overflow.

Found-by: Coverity Scan CID 1287090
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21 09:27:03 +00:00
Elyes HAOUAS bd96a84300 util: Fix typo on plural form of index
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-05-20 14:45:35 +00:00
Jett Rink 1eeb94ff4a util/scripts: update references to cross-repo-cherrypick
It appears that the rebase.sh script was renamed to
cross-repo-cherrypick and changed directories. Update comments to
reflect that change.

Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-20 14:44:08 +00:00
Alex James 7aeeb48390 util/lint/check-style: Don't hardcode clang-format path
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-15 19:46:39 +00:00
Elyes HAOUAS 65209de411 autoport: Remove unneeded include <arch/io.h>
Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15 17:58:20 +00:00
Christian Walter 9a8c5e7ac0 util/inteltool: Add Kabylake E3-1200 Support
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15 17:21:39 +00:00
Elyes HAOUAS c15e600490 crossgcc: Upgrade acpica to version 20190509
Changes: https://acpica.org/node/170

Change-Id: I6779a20005ffc0d4781bb60de3ba48759ef67d40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-13 09:32:24 +00:00
Jacob Garber a75440739d util/inteltool: Use appropriate channel for printing timings
At least one channel must be present, so print an error if there is
not. However, we cannot always assume it will be the first channel,
so make the appropriate selection when printing the timings.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:24:14 +00:00
Jacob Garber 554e55b0f0 util/kconfig: Use snprintf to avoid buffer overflow
'name' and 'env' are supposed to be file system paths,
but could overflow the buffer if configured incorrectly.
Let's avoid that entirely.

Found-by: Coverity Scan #1362515
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 09:14:42 +00:00
Jacob Garber 4fbd22e38d util/intelvbttool: Add error checking for memory allocation
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can
fail, so add appropriate error checks for those cases.
This incidentally fixes a possible memory leak when
'malloc_fo_sub' succeeds but 'remalloc_fo' does not.

Found-by: Coverity Scan #1396050
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:35 +00:00
Jacob Garber 2be617b58b util/intelvbttool: Free file object on error path
Prevents a memory leak.

Found-by: Coverity Scan #1396047
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:27 +00:00
Jacob Garber 9bb0461fbd util/ifdtool: Add find_fd null check
As the previous comment indicated, this null check is
currently superfluous, but adding it in makes Coverity
happy, and future-proofs the code in case someone changes
the internals of 'find_fcba' later and forgets/doesn't know
to update this error check.

Found-by: Coverity Scan #1395066
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:14 +00:00
Nico Huber 772a154d39 nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.

TEST=Played tint on kontron/ktqm77. Score 606

Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12 15:03:03 +00:00
Joel Kitching 2eb89c8b14 vboot: include vb2_sha.h when required
Should include vb2_sha.h header when SHA library functions or
constants are required.  This replaces NEED_VB2_SHA_LIBRARY.

BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-09 06:32:44 +00:00
Elyes HAOUAS 1d3b3c3c09 {src,util}: Remove duplicated includes
Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07 16:15:56 +00:00
Patrick Rudolph ac24d3c311 sconfig: Add SMBIOS type 9 entries
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.

smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)

Example:

    device pci 1c.1 on
        smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
    end # PCIe Port #2 Integrated Wireless LAN

Tested on Lenovo T520.

Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:04:56 +00:00
Felix Singer 0a7543db2d inteltool: Add Sunrise Point-LP Skylake PCH IDs
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.

This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.

Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)

Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:38:49 +00:00
T Michael Turney 101098c41a sdm845: Combine BB with QC-Sec for ROM boot
TEST=build & run

Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03 21:59:05 +00:00
Furquan Shaikh 4d99b27018 util/sconfig: Throw an error if override tree has no devices
If override tree does not have any device, then the chip info
structure in it cannot be associated with the correct device and ends
up being added as a standalone chip info structure without any device
actually using it. This change prevents this condition by throwing an
error during compilation.

BUG=b:130342895

Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-24 16:23:51 +00:00
Patrick Rudolph e28fa4049d cbfstool: Fix cbfs_file_next_attr
The last attribute was never returned.
Fix size compare to retrieve all attributes.

Manually tested and seen all attributes, including the last one.

Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 10:23:56 +00:00
Elyes HAOUAS 5f28639a93 crossgcc: Update acpica to version 20190215
Support for ACPI specification version 6.3:

Add PCC operation region support for the AML interpreter. This adds PCC
operation region support in the AML interpreter and a default handler for
acpiexec. The change also renames the PCC region address space keyword to
PlatformCommChannel.

Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG.
These methods provide OSPM with health information and device boot
status.

PDTT: Add TriggerOrder to the PCC Identifier structure. The field value
defines if the trigger needs to be invoked by OSPM before or at the end
of kernel crash dump processing/handling operation.

SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT
is used for describing devices such as heterogeneous processors,
accelerators, GPUs, and IO devices with integrated compute or DMA
engines.

MADT: Add support for statistical profiling in GICC. Statistical
profiling extension (SPE) is an architecture-specific feature for ARM.

MADT: Add online capable flag. If this bit is set, system hardware
supports enabling this processor during OS runtime.

New Error Disconnect Recover Notification value. There are a number of
scenarios where system Firmware in collaboration with hardware may
disconnect one or more devices from the rest of the system for purposes
of error containment. Firmware can use this new notification value to
alert OSPM of such a removal.

PPTT: New additional fields in Processor Structure Flags. These flags
provide more information about processor topology.

NFIT/Disassembler: Change a field name from "Address Range" to "Region
Type".

HMAT updates: make several existing fields to be reserved as well as
rename subtable 0 to "memory proximity domain attributes".

GTDT: Add support for new GTDT Revision 3. This revision adds information
for the EL2 timer.

iASL: Update the HMAT example template for new fields.

iASL: Add support for the new revision of the GTDT (Rev 3).

More changes in this version at https://acpica.org/node/166

Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23 10:03:12 +00:00
Elyes HAOUAS b1f4d52580 crossgcc: Update CMake to version 3.14.2
Release Note :
https://cmake.org/cmake/help/v3.14/release/3.14.html
"The FindFontconfig module added by 3.14.0 accidentally used uppercase
FONTCONFIG_* variable names that do not match our conventions.
3.14.1 revises the module to use Fontconfig_* variable names.
This is incompatible with 3.14.0 but since the module is new in the 3.14
series usage should not yet be widespread"

Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:06 +00:00
Elyes HAOUAS 095c2617a3 crossgcc: Upgrade GCC to version 8.3.0
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:01 +00:00
Thejaswani Putta 6f5225c7e0 Klocwork: Fix the Null pointer derefernce found by klocwork
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 09:56:37 +00:00
Robin Broda 21f9b3ecd7 util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI devices
Signed-off-by: Robin Broda <robin@broda.me>
Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:55:31 +00:00
Elyes HAOUAS 75380d3a16 src/mb/Kconfig: Fix PCI subsystem IDs
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed
in commits

 dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()
 00bb441 sb/intel/lynxpoint: Remove PCI bridge function

Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 17:48:15 +00:00
Martin Roth 26c43b7a77 util/docker: Update JRE in coreboot-jenkins-node Dockerfile
openjdk-8-jre-headless is no longer available in the debian image we're
basing the coreboot-sdk off of.  Update it to 'default-jre-headless'.

Change-Id: I60f6ecbaedccc0da61f96e0bce4122406ba4bd91
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-17 14:48:32 +00:00
Patrick Georgi e8367c0c5e util/genbuild_h: Prefer iasl from .xcompile over a hard code
build.h provides iasl's version but right now assumes that it's kept in
util/crossgcc/xgcc/bin. Often true, but not always, so use the one found
in .xcompile to query the version as that's the version that is used in
coreboot builds.

Change-Id: Iaeedc22e0e14fa96b4f2a68127f405c7f0c9d5cc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-15 16:35:09 +00:00
Patrick Georgi 237baa1433 util/genbuild_h: Allow operation with older git versions
if git log --no-show-signature is not supported, retry without.

Change-Id: I9ee1f8e887cde5e4d6c5e6958f269c62572cdd53
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32299
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-12 10:19:59 +00:00
Sergey Alirzaev 8f6f3ac199 util/genbuild_h: Do not print PGP verification results in `git log` output
Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com>
Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32129
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 12:07:51 +00:00
Jacob Garber 94d61ecab0 util/inteltool: Swap conditions to prevent uninit reads
Both values in each array are only initialized if
`two_channels` is true, so we need to check that first.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:27:11 +00:00
Hung-Te Lin 0043a3db20 Documentation: Explain FMAP and FMD
The Flashmap (FMAP) was not clearly documented. The new flashmap.md
explains where to find more details about that and how / why it was used
in coreboot. Also explained what is FMD and how to use it (based on
original README.fmaptool).

BUG=None
TEST=None (only documentation)

Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:24:32 +00:00
Julius Werner f028604718 kconfig_lint: Make uses of CONFIG() on an unknown option an error
This check had very few false positives which were all easily resolved,
and it's unlikely that further false positives will become problematic
in the future. On the other hand, it does detect a very severe bug (when
you think you're using a Kconfig but you aren't due to a typo), so since
warnings are currently not very visible, let's turn this into an error
because the pros clearly outweigh the cons for that.

Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:21:55 +00:00
Martin Roth d727fb5035 util/docker: Update coreboot-sdk Dockerfile for new debian image
libssl1.0-dev is no longer available:
- Update to libssl-dev
- Add libcrypto++-dev to provide additional crypto libraries not
available in libssl-dev.

Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-09 14:12:54 +00:00
Martin Roth b0fe89d31b util/docker: work around toolchain autotools issue
The patches added to `make` require that we use automake & aclocal
to rebuild the configuration, but version 1.15 of autotools is
expected. After debian sid updated to autotools 1.16, the tools can't
be located.

We'll just pretend to have version 1.15 with symbolic links. This
doesn't seem to be a good solution but gets the job done.

Change-Id: I9f616b96e728106e7adf321325caa06808e064c2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 14:56:24 +00:00
Jacob Garber 3eebb16c05 util/arm_boot_tools/mksunxiboot: Correct format strings
%lx is the right format string for printing longs.

Found-by: Coverity Scan, CID 1229686, 1229687
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib7ab54dc039bdd60969c79f3c881d69fc68f0d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03 16:57:19 +00:00
Werner Zeh 622a28d22b util/kconfig: Fix missing library issue with ld 2.24 and newer
When invoking 'make menuconfig' with gcc 4.9.2 an error is thrown:

ld: build/util/kconfig/lxdialog/checklist.o: undefined reference
to symbol 'acs_map'

This happens with ld version 2.24 and newer when menuconfig is
executed for the first time after make clean. This does not happen
with ld 2.20 (part of gcc 4.4.7).

It can be fixed with the flag -ltinfo in HOST_LOADLIBES.

Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03 05:29:16 +00:00
Balazs Vinarz 28def8b5a0 util/lint: list files with whitespace issues
Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 14:58:12 +00:00
Patrick Rudolph 9b545df90b util/spdtool: Add tool to extract SPD from BLOBs
Opens a binary file to extract DDR SPDs using known bits.
At the moment only DDR4 SPDs are supported.
Dumps the found SPDs into the current folder, as either
binary or hex encoded file.

Works with python2 and python3.

Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-01 08:03:29 +00:00
Elyes HAOUAS 2d22d335dc crossgcc: Upgrade LLVM to 8.0.0
Change-Id: I80efe90e21947aac631d54fd7983319602fc39c2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-25 10:59:41 +00:00
Elyes HAOUAS 2ec5015f02 crossgcc: Update CMake to version 3.14.0
Change-Id: I9fec45429d80500d80cc6b774718ecc91720f3f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22 09:36:19 +00:00
Julius Werner e5eb2decd0 lint/kconfig: More checks, more errors
This patch changes a few more Kconfig linter warnings to errors that
currently do not show up in the tree and that seem unlikely to become
false positive in the future. One instance of duplicated code that
essentially checks for the same thing was consolidated.

It also adds a new test for references to boolean Kconfig options that
do not use the CONFIG() wrapper macro. It's a little flaky (e.g. hard to
handle multi-line comments), but it should be helpful the majority of
the time as a warning in a Jenkins comment.

Change-Id: I975ee77d392ed426f76f7671d9b6ef9441656e6a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22 09:31:11 +00:00
Angel Pons 22add8ea30 util/autoport: Rewrite readme.md
The last part of the file has not been modified much.

Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:22:06 +00:00
Angel Pons 08caa792e6 util/autoport: Trim gfx.did to size
Since the values are hardcoded, we might as well hardcode values that
make sense.

Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:20:05 +00:00
Angel Pons 9b1ae44b28 util/autoport: fix default headers
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-18 09:19:30 +00:00
Julius Werner 0e3f7d4780 Revert "lint/clang-format: set to 96 chars per line"
This reverts commit 626ba097a2.

This change was submitted under the incorrect assumption that there was
agreement on a coding style change. There wasn't, so while the issue is
under discussion we should revert to the previous status quo.

Making clang-format honor the line length is a separate issue from
changing the line length, and can be reuploaded as a separate CL.

Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 23:05:06 +00:00
Thomas Heijligen 725369fd0c inteltool: add 300 and C240 Series PCH
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h

On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.

Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-15 12:58:28 +00:00
Marshall Dawson 02bd77379b util/amdfwtool: Allow 0-length blobs
A side effect of the change 8e0dca05
"util/amdfwtool: Add generic image copy function"
was to treat a read operation of zero bytes as a failure.  Some
implementations exist that use zero length files as a means of
removing functionality.  This causes amdfwtool to exit with an
error.

Put the zero length capability back in, and generate the requested
table entry with a length field of 0x0.

TEST=Boot google/grunt, inspect PSP directory table
BUG=b:128507639

Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 12:57:57 +00:00
Alexander Couzens 96a437f4aa util/autoport: remove obsolete symbol SANDYBRIDGE_IVYBRIDGE_LVDS
This symbol was removed in
a6be58fece ("nb/intel/sandybridge: Remove the C native graphic init")

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-14 11:25:47 +00:00
Angel Pons 8296fdd979 util/autoport: Separate NB and SB PCIe port IDs
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.

Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13 09:48:40 +00:00
Julius Werner ef7a326787 lint/kconfig: Update to support new CONFIG() macro
This patch updates the Kconfig linter to support the new CONFIG() macro
in the same manner that IS_ENABLED() was previously supported. It will
be flagged when it is used on non-bool Kconfigs or used with #ifdef, and
it is supported for checking used Kconfigs. Remaining uses of
IS_ENABLED() are flagged with a deprecation warning.

Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31776
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08 08:33:56 +00:00
Damien Zammit 8e3b842b8b intelmetool: Add more flag descriptions
Obtained by inspecting intel SPSinfo tool output

Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e
Author: roncapat
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31589
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 17:22:31 +00:00
Damien Zammit f4491e73ca intelmetool: Consolidate all model support from upstream
Some of the older chipsets that are known not to have ME at all
were removed for some reason, add them back in.

Also some newer chipsets/ME models were missing, add them in.

Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-07 17:22:22 +00:00
Marshall Dawson 67bbb6db41 util/amdfwtool: Remove fanless SMU options
Complete the removal of the fanless command line options.  The only soc
using them has been converted to use the subprogram option instead.

TEST=Verify amdfw.rom is unchanged before and after the conversion
BUG=b:126691068

Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:03:59 +00:00
Marshall Dawson dbae632fec util/amdfwtool: Split type field for PSP entries
Separate the type field for the PSP directory table to better match the
AMD Platform Security Processor BIOS Architecture Guide (order #55758,
NDA only).  Instead of a 32-bit type, change to an 8-bit value and an
8-bit subprogram field to allow for a more generic application across
family/model products.

This patch also eliminates the "fanless" types, previously added for
stoneyridge, and converts the --smufnfirmware and --smufnfirmware2
arguments to use a subprogram value of 1.

Subsequent patches will change the stoneyridge makefile to use the
new option, and eliminate the fanless arguments.

TEST=Boot google/grunt, confirm no difference in amdfw.rom file.
BUG=b:126691068

Change-Id: If8f33000c31cba21f286f54459de185c21e46268
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:03:07 +00:00
Marshall Dawson 2794a86b1b util/amdfwtool: Streamline functions with context
Replace variables and function arguments with a context that may be
maintained and passed.  Add macros to clarify the pointer math.  Add
functions to generate tables instead of relying on correct ordering
and math.  Use defined sizes for tables instead of arbitrary additions
to an index.

TEST=Verify no difference in amdfw.rom for google/grunt before and
     after, and verify a grunt build with PSP_COMBO=1 runs.

Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:02:49 +00:00
Marshall Dawson 8e0dca05fb util/amdfwtool: Add generic image copy function
Consolidate the code that opens, stats, copies, and closes the
individual files into a single function.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied

Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:02:25 +00:00
Marshall Dawson a378c22f77 util/amdfwtool: Combine table header population
Rename psp_fill_head() and call it with the cookie to populate the
header.  The combo header and PSP directory header are similar and
should be calculated the same way.

Change-Id: I7e634542de65576addadbe683596cbe572de3dcd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:02:10 +00:00
Marshall Dawson 0e02ce83a1 util/amdfwtool: Remove duplicate PSP2 support
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed.  Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.

This patch is part 2 of 2 to reduce the number of command-line options
to amdfwtool.  Part 1 added the --combo-capable option that helps
put the PSP directory pointer in the correct location.  Part 2
removes the duplicated table, the support code, options, and updates
the usage text.

TEST=Build before/after images for grunt, bettong, apu2, and diff
     hexdumps of the amdfw.rom files.  Built/ran grunt with PSP_COMBO
     defined as 1.
BUG=b:126691068

Change-Id: I542a7f5023137f30fbe00533452d4448117df487
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:01:40 +00:00
Marshall Dawson 67d868d04b util/amdfwtool: Introduce combo-capable option
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed.  Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.

This patch is part 1 of 2 to reduce the number of command-line options
to amdfwtool.  Create a new option that is used as an indicator for
which Embedded Firmware offset to use.  Part 2 will be added once
makefiles no longer use the duplicated options.

This patch also adds two new options for fanless SMU firmware to be
used instead of the ones that will be removed in part 2.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied
BUG=b:126691068

Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:01:03 +00:00
Marshall Dawson 8a45a4dc3f util/amdfwtool: Clarify call to fletcher32
The fletcher32 algorithm generates a sum over a range of 16-bit
WORDs.  Change the function's interface to be more generic,
accepting a more intuitive size in BYTEs.  Don't require the
caller to understand the nature of the algorithm and convert to
WORDs prior to calling.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied

Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:00:30 +00:00
Marshall Dawson 239286ca44 util/amdfwtool: Clarify calculations with structures
Replace the use of multiples of DWORDs with structures that
describe the Embedded Firmware Table, and PSP directory
headers & entries.

TEST=Verify no difference in amdfw.rom for google/grunt build
     (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh),
     and pcengines/apu2 (F16h 30h-3Fh).  PSP_COMBO builds but
     was not verified.

Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:00:17 +00:00
Marshall Dawson c38c0c91aa util/amdfwtool: Fix iteration of PSP firmwares
Correct an oversight in the utility that attempts to match up eligible
PSP directory table entries with blob names passed on the command
line.  A 1:1 matchup of items shouldn't be assumed, so the i iterator
shouldn't be used to walk both lists.

This change has no effect on google/grunt (Family 15h Models 70h-7Fh),
but eliminates blank entries of all FF's on builds of amd/bettong
(F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh).  Removal of entries
also affects the checksum accordingly.

TEST=Build before/after images for grunt, bettong, apu2, and diff
     hexdumps of the amdfw.rom files

Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 15:58:42 +00:00
Philipp Deppenwiese c9b7d1fb57 security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.

* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.

Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-07 12:47:01 +00:00
Patrick Rudolph 0c590f064e pci_drivers/cpu_drivers: Fix constructed arrays on x86_64
The __pci_driver and __cpu_driver uses variable length arrays which are
constructed by the linker at build-time.

The linker always place the structs at 16-byte boundary, as per
"System V ABI". That's not a problem on x86, as the struct is exactly
16 Bytes in size. On other platforms, like x86_64 it breaks, because the
default data alignment isn't SysV compatible.

Set -malign-data=abi to make x86_64 gcc use the SysV psABI.
Fixes broken __pci_driver and __cpu_driver on x86_64.

Change-Id: I2491d47ed03dcfd8db110dfb181b2c5281449591
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 20:00:38 +00:00
Felix Singer 24b000a160 inteltool: Add multiple device IDs of Intel GPUs
* Intel HD Graphics 510
* Intel HD Graphics 515
* Intel HD Graphics 520
* Intel HD Graphics 530 (2x)
* Intel UHD Graphics 615 (2x)
* Intel UHD Graphics 617
* Intel UHD Graphics 620 (3x)
* Intel UHD Graphics 630 (7x)
* Intel UHD Graphics 640
* Intel Iris Graphics 540
* Intel Iris Graphics 550
* Intel Iris Pro Graphics 580
* Intel Iris Plus Graphics 650
* Intel Iris Plus Graphics 655

Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30610
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 11:29:51 +00:00
Krystian Hebel 9e3c30283f util/superiotool/ite.c: add support for IT8613E
Based on not publicly available IT8613E Preliminary Specification V0.3.

Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-06 11:28:28 +00:00
Julius Werner d60cc97526 lint/kconfig: Fix check for IS_ENABLED(XXX) where someone forgot CONFIG_
This is a great check, but unfortunately it's currently not effective
because most uses of IS_ENABLED() do not have whitespace in front of
them (they're mostly used as part of an if (IS_ENABLED(...)) condition).
This patch makes the linter a little more generous in what it considers
in scope to avoid these false negatives in the future.

Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 01:15:26 +00:00
Hung-Te Lin 49a4450563 cbfstool: Support new FMD flag "PRESERVE"
When updating firmware, it is very often that we may want to preserve
few sections, for example vital product data (VPD) including serial
number, calibration data and cache. A firmware updater has to hard-code
the section names that need to be preserved and is hard to maintain.

A better approach is to specify that in FMAP area flags (the `area_flag`
field) using FMAP_AREA_PRESERVE. With this patchset, a FMD parser flag
"PRESERVE" is introduced and will be converted to FMAP_AREA_PRESERVE
when generating FMAP data (by fmap_from_fmd.c).

For example, The FMD statement:

  RO_VPD(PRESERVE)@0x0 16k

will generate an FMAP firmware section that:

  area_name = "RO_VPD"
  area_offset = 0
  area_size = 16384
  area_flags = FMAP_AREA_PRESERVE

BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
     Manually added 'PRESERVE' to some FMD files, and verify (by running
     fmap.py) the output coreboot.rom has FMAP_AREA_PRESERVE set

Change-Id: I51e7d31029b98868a1cab0d26bf04a14db01b1c0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-05 20:51:39 +00:00
Patrick Rudolph 44b4ec740d rmodule: Add support for R_X86_64_PLT32
The recent toolchain update also updated binutils, which has a new
relocation type, introduced with commit bd7ab16b
(x86-64: Generate branch with PLT32 relocation).

Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32.
Add comment explaining the situation.
Fixes build error on x86_64.

Change-Id: I81350d2728c20ac72cc865e7ba92319858352632
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 19:36:52 +00:00
Hung-Te Lin 9497fcb742 cbfstool: Change FMD annotation to flags
The idea of "annotation" for firmware sections was pretty flexible, but
in future we will want multiple attributes applied to same area. For
example, indicate the section must be preserved when updating firmware
so serial number or MAC address can be preserved.

The solution here is to extend annotation so it can take multiple
identifiers (flags) in a row. For example, to declare a 64KB COREBOOT
section as CBFS using annotation:

 COREBOOT(CBFS)@0x0 64k

If there's a new flag "PRESERVE" indicating the section must be
preserved before update, we can declare it following CBFS flag:

 COREBOOT(CBFS PRESERVE)@0x0 64k

The flags are directly parsed in fmd_parser, and stored in an union
flashmap_flags. Output modules can choose to ignore or process the
flags.

Currently the only supported flag is "CBFS" (for backward compatible
with annotation). There will be more new flags in follow up patches.

BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices

Change-Id: Ie2d99f570e6faff6ed3a4344d6af7526a4515fae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31706
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 19:31:43 +00:00
Patrick Georgi 2785290989 util/lint: Fix clang-format test and enable it by default
git diff needed to emit diffs without prefix (e.g. a/ and b/) for
clang-format-diff to be able to work.

Also require that the test succeeds, but note that it only runs on
trees whitelisted in $(top)/.clang-format-scope.

Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 16:13:10 +00:00
Patrick Georgi 626ba097a2 lint/clang-format: set to 96 chars per line
80 chars + 2 tabs was the compromise we got to in the last round of
discussion.

Change-Id: I9293a69d1bea900da36501cde512004d0695ad37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05 12:45:47 +00:00
Nico Huber 8a95c6c48d util/inteltool: Add Apollo Lake GPIO groups and names
Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.

Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.

Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)

Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05 11:56:02 +00:00
Hung-Te Lin 4708612061 fmap: Add FMAP_AREA_PRESERVE
When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.

To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.

BUG=chromium:936768
TEST=make; boots an x86 image.

Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-04 13:25:01 +00:00
Patrick Rudolph 62b4b44961 rmodule: Don't emit reloc for R_X86_64_PC64
Relocations for PC relative instructions must not emitted.
As PC64 are unlikely with current code, it never was an issue.

Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03 16:46:30 +00:00
Kyösti Mälkki a37a1a65a7 util/cbmem: Improve utility description
Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01 10:00:46 +00:00
Nico Huber 4829af17e3 cpu/intel: Rename socket_mFCPGA478 to socket_m
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.

The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.

Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28 13:47:54 +00:00
Martin Roth 3361120bc8 util/abuild: Set fatal asserts when running scanbuild
Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert.  This
change fixes that and allows us to add asserts to protect
against other failures.

Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27 19:33:43 +00:00
Elyes HAOUAS b134368942 ACPI: Fix error on asl_compiler_revision format
dmesg report wrong asl compiler version as this value wasn't
in hexadecimal:
FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 01341407)
DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215)

This error was introduced on change-Id: I91b54b43c8b

Tested on 945G-M4 board, dmesg now report the right value:
FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 20190215)
DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215)

Change-Id: I5494bb1e7af17eba0c2da8a0c2eb9e40ffd8d065
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31612
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 21:44:01 +00:00
Philipp Deppenwiese 66f9a09916 security/vboot: Add measured boot mode
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.

Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 22:29:16 +00:00
Damien Zammit f0a9128424 intelmetool: Use GPLv2+ where possible
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.

However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.

Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 11:19:37 +00:00
Alex Feinman 2223cbf7de intelvbttool: Add support for reading vbt from sysfs
VBT on Intel(R) systems is available via sysfs as
    /sys/kernel/debug/dri/0/i915_vbt
However the size of this file reads as 0 causing
intelvbttool to fail. This patch implements incremental reads
with realloc for such cases or whenever the file size is not
available (e.g. reading from stdin).
After this patch is applied, intelvbttool can be used as follows:
    sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d

Change-Id: I5d17095a5747550b7115a54a7619b7294a846196
Signed-off-by: Alex Feinman <alexfeinman@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/31531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22 11:09:58 +00:00
Elyes HAOUAS 26071aaadf ACPI: Correct asl_compiler_revision value
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 19:07:31 +00:00
Elyes HAOUAS 94ad37619f SMBIOS: Fix bios version
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 19:07:18 +00:00
Nico Huber 55e3a6ae09 util/lint: Exclude util/inteltool from checkpatch
It's causing too much noise during review of register tables.

Change-Id: Iae6cd4454c5ed84b5fe0ea5f8a244e2a2fa13407
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31367
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20 12:17:32 +00:00
Elyes HAOUAS c3c9afbdf1 crossgcc: Update MPFR to version 4.0.2
Change-Id: I5569e61c2a3a64cf353afe3195eca82709362305
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31218
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18 20:20:58 +00:00
Elyes HAOUAS 7340a499fb crossgcc: Update binutils to version 2.32
Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15 17:16:11 +00:00
Bora Guvendik 85ea91ae3c util/ifdtools: Make EC region readable to BIOS/CPU
Allow EC region to be readable by BIOS/CPU so that flashrom
can read it.

BUG=b:123199222
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set,
run firmware_LockedME test.

Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-14 07:53:16 +00:00
Arthur Heymans 12431d6eef Makefile.inc: Create a default SMMSTORE region
Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06 18:15:59 +00:00
Arthur Heymans 0b75679cbb Makefile.inc: Optimize generating the default x86 fmap
Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.

Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06 18:15:27 +00:00
Aaron Durbin eb722282da cbmem: use aligned_memcpy for reading cbmem address information
The coreboot table entry containing the memory entries can have
fields unnaturally aligned in memory. Therefore one needs to perform
an aligned_memcpy() so that it doesn't cause faults on certain
architectures that assume naturally aligned accesses.

BUG=chromium:925961

Change-Id: I28365b204962ac89d65d046076d862b6f9374c06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Manoj Gupta <manojgupta@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-01 14:53:19 +00:00
Patrick Georgi ec31d1ac76 util/docker: Update container for doc.coreboot.org
Now running 1.8.3, with a fix to the theme so search still works, and
a recommonmark version that properly rewrites links to .md files.

Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-29 18:28:47 +00:00
Lijian Zhao 9871b04183 util/ifdtools: Consider EC region access
Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.

BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29 12:29:35 +00:00
Lijian Zhao 3e88b18bb6 util/ifdtool: Add lock support for CNL and ICL
Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.

BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29 12:29:24 +00:00
Angel Pons 175778f059 Revert "util/bincfg: code cleanup: convert sym_table to a local variable"
This reverts commit 48c24ce5ee.

Reason for revert: Commit broke bincfg, and sym_table as a global
variable is less bad than passing it around in function calls.

Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-26 13:35:43 +00:00
Elyes HAOUAS 3f7fd58823 crossgcc: Update CMake to version 3.13.3
Change-Id: If3bd670e2273715b6996e2ca78a0b9c412bfd220
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26 13:33:55 +00:00
Patrick Georgi b8c107c7b8 util/crossgcc: Update to binutils 2.31.1 and gcc 8.2
Change-Id: Icf7c6bdd4021bf84cc295c819f93838248e0f4c7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-26 13:33:32 +00:00
Kyle Stevenson 769c309e3d util/superiotool: detect Fintek F81866, F8196*
F81866 detection tested with the iBASE SI-613:

    superiotool r4.9-420-g034e5e6
    Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e

F8196* detection is based on chip IDs provided by iBASE, but untested.

Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39
Signed-off-by: Kyle Stevenson <kstevenson@comqi.com>
Reviewed-on: https://review.coreboot.org/c/31052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:24:59 +00:00
Martin Roth 3748aae7d6 util/lint: update non-ascii linter checking rules
- Check non-external payloads
- Remove directories that aren't in the coreboot git repo.
- Remove non-phrase rule from list of excluded phrases

Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24 13:51:51 +00:00
Nico Huber 533bc0a7ef util/kconfig: Add `toada` Ada spec generation tool
Converts `auto.conf` to an Ada spec file. Write to
$(obj)/cb-config.ads and set the package name to
`CB.Config`.

Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24 13:47:08 +00:00
Arthur Heymans 7e6946a74c cpu/intel/model_206ax: Remove the notion of sockets
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.

UNTESTED: This also updates autoport.

Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:39:19 +00:00
Martin Roth 300b25a910 util/lint: Update non-ascii linter for FreeBSD
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"

- Remove support for testing coreboot not in a git repo.  Many of
the other linters already don't support this.
- Use git grep to find offending files, then xargs to print out
the lines.

Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-23 14:55:31 +00:00
Wonkyu Kim 31eeda1c44 util/crossgcc: use fixed length version string.
After merging util/crossgcc: derive date and version from latest commit
(https://review.coreboot.org/c/coreboot/+/30804),
crossgcc build is broken in internal repository due to long version
name;coreboot.org repository is ok because it uses short tag name.
The patch uses "git describe" which is dependent on git tag name.
If tag name is little bit long, it can cause crossgcc build failed.

To avoid this issue, use only short version of hash string
which is fixed length. And it's enough as version string,
because we also use date(CROSSGCC_DATE) together.

TEST=Build crossgcc in both coreboot.org and internal repository
which uses longer tag name and check version string in build log.

Change-Id: I405b2e4e5c05831c25aebf1c73a281adab8ef452
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/31001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-22 19:45:27 +00:00
Thomas Heijligen da02719462 util/inteltool: Add support for Denverton
Used documents:
- C3000 Product Family Datasheet

Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae
Co-authored-by: Felix Singer <migy@darmstadt.ccc.de>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/30887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-21 13:27:24 +00:00
Angel Pons ca62334d76 util/autoport: Make dsdt.asl prettier
Small cosmetic changes which fix aesthetic inaccuracies.

Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-20 20:53:35 +00:00
Angel Pons 1b252fc37a util/autoport: Fix include style
Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30970
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 20:47:37 +00:00
Angel Pons 6541956e97 util/autoport: Break very long line
Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30968
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 20:46:16 +00:00
Angel Pons 07b6f16063 util/autoport: Correct DSDT include statement
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file),
some model_206ax code was moved to a common place. However, autoport
was not updated accordingly.

Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30967
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 19:36:13 +00:00
Iru Cai 1e2676bf1b autoport: move the generated gnvs.c to acpi_tables.c
Change-Id: I8f6eea579f69060608639b1c50255acd8ab5a4a2
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-15 23:15:38 +00:00
Patrick Rudolph 6085d39bdb util/superiotool: Add ITE8528
Add ITE8528 which can be found on the wedge100s.
Most registers are dumped from hardware.

No datasheet is publicy available.

Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-15 07:45:55 +00:00
Arthur Heymans 3ef017c4d4 [RFC]util/checklist: Remove this functionality
It was only hooked up for galileo board when using the obsolete
FSP1.1. I don't see how it can be useful...

Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30691
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 19:42:59 +00:00
Patrick Georgi 5ce73e9836 util/crossgcc: derive date and version from latest commit
This way date and version are automatically updated when util/crossgcc
was changed, the version contains the commit ID and we have less churn
on these variables.

Change-Id: I475ba9578a8bb421d7c342d2569d7de7fcf4161d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-11 14:55:39 +00:00
Elyes HAOUAS 75292a139e crossgcc: Update acpica to version 20190108
changes in this version: https://acpica.org/node/164

Change-Id: Iff7fb6990f69f658c41ec115a3383ec902d8300f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-10 12:54:31 +00:00
Elyes HAOUAS 930d96e1b6 crossgcc: Update Python to version 3.7.2
Change-Id: Ie0b3d31ba116314308d4fcc36a19587370fff7cc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30560
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07 10:33:37 +00:00
Nico Huber 844eda0f3b util/ifdtool: Fix regions_collide() check
The old version was unnecessarily complex and allowed one region to
include the other.

Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30673
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06 23:54:41 +00:00
Elyes HAOUAS a2046b29ef crossgcc: Update CMake to version 3.13.2
Change-Id: Ifd9e82d564e4e49194ac48786fd233cbf97a55c5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05 14:42:06 +00:00
Elyes HAOUAS 53feeb0f1a crossgcc: Update GDB to version 8.2.1
Change-Id: I454843dcabe7e3fa4b13dd58ce81ba9f25b5a432
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05 14:41:38 +00:00
Elyes HAOUAS d4cb736c31 crossgcc: Update LLVM to 7.0.1
Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05 14:41:30 +00:00
Shaleen Jain 2822d66238 util/inteltool: fix PCR init of Sunrise Point-LP devices
Fixes getting a dump of GPIO registers for these devices.

Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Signed-off-by: Shaleen Jain <shaleen@jain.sh>
Reviewed-on: https://review.coreboot.org/c/30604
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-05 11:15:04 +00:00
Elyes HAOUAS 71a743e961 crossgcc: Update acpica and Expat versions
Update:
 * acpica to version 20181213
   changes in this version: https://acpica.org/node/163
 * Expat to version 2.2.6
   changes in this version:
   https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes

Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-04 22:04:31 +00:00
Kyösti Mälkki 031dc67a61 util/superiotool: Add ITE IT8786E-I
Based on IT8786E-I V0.4.1 datasheet with following remark:

  "Please note that the IT8786E-I V0.4.1 is
   applicable only to the D version."

Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4
Reviewed-on: https://review.coreboot.org/c/30334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-04 15:07:19 +00:00
Angel Pons 782341dd3a util/autoport/readme.md: Correct minor inconsistency
Commit a5072af67d ("util/autoport: Use romstage.c instead of
early_southbridge.c") changed where the SPD map is. Reflect that.

Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30655
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 13:12:00 +00:00
Edward O'Callaghan 4139c15276 util/gitconfig/pre-commit: Use clang-format to sanitise commits
Use the `git-format' tool to sanitise coreboot commits such that
they conform to coreboot's coding style.

This fancy piece of machinary allows one to have LibFormat from
Clang to automatically check your commit conforms to coreboot's
coding style, fix any issues automatically and provides you a
diff you may review and apply at your convenience.

N.B. When the `clang-format' binary is not found we issue a warning
that the test was skipped and carry on as usual. Hence, this is
strictly non-enforcing at this current time. You may use it at your
leisure.

Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/c/8037
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 10:37:10 +00:00
Stefan Reinauer d1584fb250 crossgcc: Update acpica to 20180927
Update to latest version of iasl:

(From the acpica.org changelogs)
* Fixed a regression introduced in version 20180927 that could cause the
  compiler to fault, especially with NamePaths containing one or more
  carats (^). Such as: ^^_SB_PCI0

* Added a new remark for the Sleep() operator when the sleep time
  operand is larger than one second. This is a very long time for the
  ASL/BIOS code and may not be what was intended by the ASL writer.

* Implemented detection of extraneous/redundant uses of the Offset()
  operator within a Field Unit list. A remark is now issued for these.
  For example, the first two of the Offset() operators below are
  extraneous. Because both the compiler and the interpreter track the
  offsets automatically, these Offsets simply refer to the current
  offset and are unnecessary. Note, when optimization is enabled, the
  iASL compiler will in fact remove the redundant Offset operators and
  will not emit any AML code for them.

Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28944
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 10:28:46 +00:00
Stefan Reinauer aedb1dfbbb crossgcc: Update software versions
Update toolchain to the following software versions:

 o Python 3.5.1 -> 3.7.0
 o LLVM   6.0.0 -> 7.0.0
 o Expat  2.2.1 -> 2.2.5
 o MPC    1.0.3 -> 1.1.0
 o MPFR   3.1.5 -> 4.0.1

Change-Id: I66c6138c7b65c73a89b3cf980bb08950d8fffe6a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28887
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 10:28:00 +00:00
Tristan Corrick f50bd6d82d util/chromeos/crosfirmware.sh: Print more messages
The existing code has several messages that are only printed when the
DEBUG variable is set. These messages are not verbose, and are quite
useful to see how the script is progressing. So, print them
unconditionally.

Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03 16:53:57 +00:00
Tristan Corrick d80607da4d util/chromeos/crosfirmware.sh: Check for dependencies
crosfirmware.sh has dependencies that might not be installed on some
systems. If a dependency is missing, provide a clear message about the
issue and how to resolve it.

Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30549
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03 16:53:32 +00:00
Tristan Corrick 30348c2058 util/chromeos/crosfirmware.sh: Print download status
It's quite useful to know the download progress, as it can take a while
even with a fast connection. For example, the peppy recovery image is
~600 MiB. It also lets the user know that disk space is being filled.

Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03 16:52:57 +00:00
Tristan Corrick df90c626e0 util/chromeos/crosfirmware.sh: Add /sbin to PATH
On some systems, such as Debian 9.6, `parted` and `debugfs` are located
in /sbin. Adding /sbin to PATH means that this script can work when run
as a regular user.

Change-Id: I151dba467e2b196f13093334273dae8a05865491
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03 16:52:36 +00:00
Elyes HAOUAS 69b6c56909 util/xcompile/xcompile: Use tab for indent
Change-Id: I9878e6d962004003e2c05a6cdb8ecb0a3a02ae66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-28 22:33:30 +00:00
Matthew Garrett 2bf28e52ee util/inteltool: Add support for Sunrise Point LP
Used documents:
334658 (Sunrise Point-LP I/O datasheet vol. 1)
334659 (Sunrise Point-LP I/O datasheet vol. 2)
332690 (Sunrise Point I/O datasheet vol. 1)

Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/28623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-28 22:31:54 +00:00
Frans Hendriks e1700fc832 util/cbfstool/cbfstool.c: Fix typo
Fix typo of 'top-aligned'

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I6dc2f150d8ec245070257384b406a570498400b2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30337
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24 08:13:48 +00:00
Patrick Georgi 250f01e7e3 util/release: Don't assume the source is in a directory called coreboot
Change-Id: I384ff2f01b38916851522411d0c25c49793fe480
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-21 18:06:36 +00:00
Patrick Georgi 3b2305eed9 util/release: Use "gpg", not "gpg2" for creating signatures
It's the common name.

Change-Id: Iafa793b961847b2c98282fd035ea96ddf6109012
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21 18:06:15 +00:00
Patrick Georgi 35c8dcf992 util/release/genrelnotes: Don't assume we're on origin/master
A release may be done from an older commit. It's also not a problem as
commits are stored in the reflog (unlike local changes that the script
guards properly).

Change-Id: I26f1c16c1cdfc9e77e28528b3327ce30c5b82b19
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21 18:06:01 +00:00
Patrick Georgi fa13a6437e util/release: Test for rename(1) in genrelnotes
It's a separate package on debian, so it may not be installed with perl.

Change-Id: Id82661e1d7e6a025f5b207e3bd61669abc32d328
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21 18:05:42 +00:00
Patrick Georgi 84601e468f util/release: Also keep 3rdparty/fsp in the blobs tarball
Change-Id: I089519f685377ae02155817bb042f83d79d1af6c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21 18:05:24 +00:00
Patrick Rudolph 146fe6da09 util/xcompile/xcompile: Enable x86_64 support
Similar to i686 on x86_32, compile for nocona on x86_64.
Nocona is the first Pentium 4 CPU that has long mode support.
Required for 64bit support.

Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/29877
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20 22:13:48 +00:00
Bob Moragues 7f520c8fe6 zoombini: remove support for deprecated zoombini board
Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b
Signed-off-by: Bob Moragues <moragues@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30094
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 18:05:51 +00:00
Jonathan Neuschäfer cb76069e87 util/crossgcc/buildgcc: Remove quotation marks around hashes
They were not originally printed, and serve no good purpose, so let's
remove them again.

Change-Id: I4e00477f2e143f93fd27ba6a083977a667a3eb48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 17:02:01 +00:00
Stefan Tauner 47d6663bba utils: introduce find_usbdebug.sh to help find USB debug ports
Carl-Daniel made this script a long time ago but it never was picked up
in the tree. Now that USB debugging is way more common it makes
sense to include it.

I have made a number of changes to the original version:
* -h help text
* check for running as root
* enhanced readability (test -> if)
* new execution flow and refined output that better shows the device(s)
  attached to the debug port(s)
* handling of Intel rate-matching hubs
* hiding of (bogus) error messages from lspci and lsusb

Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Change-Id: Iadf775e990f5c5f91a28d57e3331d1f59acee305
Reviewed-on: https://review.coreboot.org/c/9305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 10:21:32 +00:00
Patrick Rudolph 21046a33ef util/cbfstool/cbfs-mkstage: Support x86_64
Add support for relocations on x86_64.
Required for 64bit romstage.

Change-Id: I1ff223d3476776297b501813a953356dd6fa9d67
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/30115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-12-19 06:06:49 +00:00
Patrick Rudolph 565bebe0b3 util/cbfstool: Support AMD64 rmodules
Add support for 64bit rmodule, as required for relocatable
ramstage on x86_64.

Change-Id: I7fbb3b4c0f76ce82c090b5f16f67a728b6bf94a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/29874
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 06:05:52 +00:00
Jonathan Neuschäfer 1fb7dd076f util/lint/spelling.txt: Protect "acknowledgement" entry
In commit eceba31c7f ("util/lint: Set "acknowledgement" correct"), the
word "acknowledgement" was removed from util/lint/spelling.txt. A more
robust solution is to comment it out, as done for "sepc" in commit
afa5ec8d5f ("util/lint: Update spelling.txt to latest linux  version").

Change-Id: Ia976dedc9b31190d22e7b946f14709d5c4577f71
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:26:15 +00:00
Jonathan Neuschäfer 05400b7a2f util/util_readme: Don't recommend running this script with "sh"
util/util_readme/util_readme.sh is specifically a bash script and
requires bash-specific features such as "[[". It doesn't work when run
with a "sh" shell that only implements POSIX features, such as dash.
Thus, tell the user to run the script directly, in which case the #!
line is used.

Change-Id: I5706ffe857c5a148e9776571a377ad8647f9a4c2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:25:21 +00:00
Jonathan Neuschäfer 6b867b8aa8 util/bucts: Add a description.md file
Change-Id: I367703ffcd8d10dec0c67b61c9ebbefd497424fd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:24:56 +00:00
Arthur Heymans 7ccb2821d2 util/board_status.sh: Fix command for fetching the kernel log
94b761c8e (util/board_status: run dmesg with sudo) attempted to
fetch the console as root locally but instead sudo was put in front
of the remote path which runs as root anyways.

Also unless quotation marks are used the cmd function will see 'sudo'
and 'dmesg' as separate aruguments.

Change-Id: Ib9e9e4b443f4e3ad04c5fda2c2ce626255a190f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:22:11 +00:00
Patrick Georgi 571477b514 util/scripts/maintainers.go: file: queries are more stable with quotes
The gerrit docs aren't very explicit about it, but file:"^foo$" is more
robust than file:^foo$.

Change-Id: I16c7d972d365cd04ca5fbb78012ad4eaad667be6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29781
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05 15:21:21 +00:00
Adam Kallai 66c22508c7 cbmem: Enable AArch64 support
TEST=on Chromebook Kevin with 64bit userland, it works well.

Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153
Signed-off-by: Adam Kallai <kadam@inf.u-szeged.hu>
Reviewed-on: https://review.coreboot.org/c/29978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-03 09:43:00 +00:00
Jonathan Neuschäfer c22ad581c8 arch/power8: Rename to ppc64
POWER8 is a specific implementation of ppc64, which is by now outdated
(POWER9 has been on the market for a while). Rename arch/power8/ to
potentially cover a wider range of hardware.

TEST=Toolchains built before/after this commit can build coreboot for
     emulation/qemu-power8 from before/after this commit.

Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2018-11-30 20:02:17 +00:00
Philipp Deppenwiese aea00f496b broadcom: Remove SoC and board support
The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.

* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries

Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30 10:26:37 +00:00
Nico Huber 94473afcd2 util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.
Hence, we have to decide based on the LPC ID which device to query.

Also fix a comment.

Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29 21:03:24 +00:00
Elyes HAOUAS f0c5be2a4f mb/*/*/Kconfig: Remove useless comment
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hellsenberg <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-28 13:53:51 +00:00
Martin Roth 7ed3fe2b47 romcc: Increase buffer size to fit max string size
On the updated builder image, the build is failing because the system
compiler has been updated to GCC 8.2.0.  It complains about the
possibility of overflow when putting one 30 character buffer plus 2
characters into another 30 character buffer.  To fix this, increase
the recipient buffer size by 2.

romcc.c:3645:2: note: 'sprintf' output between 3 and 32 bytes into a destination
of size 30 [-Werror=format-overflow=]
  sprintf(buf, "\"%s\"", scratch);
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
romcc.c:3649:2: note: 'sprintf' output between 3 and 32 bytes into a destination
of size 30 [-Werror=format-overflow=]
  sprintf(buf, "\"%s\"", scratch);
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Change-Id: I7879a7202cc3ff52301b10118fc49fcc601f133e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/29850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-28 11:47:32 +00:00
Julius Werner e3c2391fca cbmem: Fix remaining mapped memory accesses to use aligned_memcpy()
aligned_memcpy() was introduced to fix issues with platforms that don't
allow unaligned accesses to areas mapped with /dev/mem, but we missed a
few spots. Fix them.

Change-Id: I97ea953455b41a50023ceaca7eb148d60e6b8097
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-27 19:31:26 +00:00
Patrick Georgi d971e7670c util/crossgcc: Document how to build the toolchain for another location
One common issue with the toolchain is that it takes a very long time
to build while it's somewhat volatile inside the coreboot tree.

Installing the toolchain elsewhere helps keep it safe but since there
is no reliable default location outside the tree, keep the default
as is.

Change-Id: Ic414cddfd3c7097412f3f2c3c7ec7b7191fa32de
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-26 09:24:01 +00:00
Patrick Georgi 9651058c42 util/scripts/maintainers.go: drop special case for "THE REST"
It's not useful anymore.

Change-Id: Iba7f10dc87301911ff5f73c182b41c268fba310a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29658
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-24 22:12:07 +00:00
Elyes HAOUAS 6d19a20f5f mb: Set coreboot as DSDT's manufacturer model ID
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".

Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
2018-11-23 11:00:40 +00:00
Werner Zeh bbf1df76a6 util/cbfstool: Fix GCC error due to a shadowed declaration
There is already a function with the name buffer_size(). Adding a local
variable with the same name will lead to the following error on older
GCC versions (e.g. version 4.4.7):

declaration of 'buffer_size' shadows a global declaration

To fix this rename the local variable to buffer_len.

Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-11-23 05:08:30 +00:00
Frans Hendriks 166cbdec5b util/cbfstool/rmodule.{c,h}: Fix typo and correct header
Header contains ':' in copyright line. rmdoule is a typo
Remove the ';' and correct typo to rmodule.

BUG=N/A
TEST=N/A

Change-Id: I05b1fb80a81682646c9fba3d234de235b6bc9e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-22 14:58:38 +00:00
Xiang Wang 7db270c25c riscv: fix bug of sifive-gpt.py
The GPT version must be "00 00 01 00" and the little endian should be
represented as 0x10000.

Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table

Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/29767
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-22 14:48:43 +00:00
Aamir Bohra 1018be2852 util/ifdtool: Add IceLake platform support under IFDv2
Change-Id: Ib69a2cbc3d8ab9f35c940e95b0edb4b04b50b716
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1162995
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29696
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 13:45:52 +00:00
Elyes HAOUAS 0cca6e24b7 ACPI: Fix DSDT's revision field
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.

Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 12:12:04 +00:00
Arthur Heymans a29498f599 util/bucts: Add tool to manipulate BUC.TS bit on Intel targets
The purpose of this tool is to manipulate and get information about the
`Back Up Control, Top Swap` mechanism present on most Intel Southbridges.

This tool is initially written by Peter Stuge.

This tool makes it possible to have a backup mechanism for the
bootblock by using the southbridges Back Up Control Top Swap.

Sometimes it is also possible to circumvent vendor write protection mechanisms
in order to flash coreboot. An example of where this would be useful would be
the Lenovo Thinkpad X60 and T60.

Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18224
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-19 08:19:16 +00:00
Patrick Georgi 94b761c8ed util/board_status: run dmesg with sudo
Newer kernels only allow root to access the kernel log buffer.
In another case (cbmem) we use sudo to get past that, so we can
expect sudo to be available here, too.

Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/29670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-18 17:12:17 +00:00
Angel Pons 7ec15c82f4 util: Fix shebang for python2 scripts
Python 3 is the default Python interpreter on most modern systems.
Python 2 scripts must specify they should be run with Python 2 in their
shebang. Solves issue raised in CB:28953.

Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-18 09:12:22 +00:00
Yegor Timoshenko c2e4941367 treewide: use /usr/bin/env where appropriate
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.

Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-17 07:32:03 +00:00
Vadim Bendebury 98485de881 util/cbsftool: allow enabling verbose make output
Sometimes it is necessary to be able to see exact command lines used
when compiling and linking. Use the same scheme as some other
Makefile's - enable verbose output when variable V is set to 1.

TEST=tried building cbfstool with V=1, observed verbose output.

Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/29431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 12:59:09 +00:00
Alex Thiessen 52fdc05013 util/gitconfig/test: Add commit-msg hook test
Add a test that, after cloning the repository to a temporary directory,
installs git hooks and attempts to do a good and a bad commit, expecting
the former to succeed and the latter to fail, thus testing the
`commit-msg` hook.

Change-Id: Icdaf0109c60cb5b6952b1a2468ab050a742e4201
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23281
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:08:48 +00:00
Nico Huber 9b1cbe040b util/docker: Rename _CONTAINER_VERSION => _IMAGE_TAG
This is so confusing, let's name it what it is ;)

Change-Id: I6f87e2f6912d886e241e03998fb4136fb28bc7b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 10:06:09 +00:00
Nico Huber 9b731b5c08 util/docker: Use common .ccache for local builds
Bind a volume for .ccache to the `docker-run-local` targets. By default
the current user's $(HOME)/.ccache will be used, it can be overridden
via the DOCKER_CCACHE variable.

Also rearrange some docker parameters to keep the target readable.

Change-Id: I7d0bdb3861ac56361cacfa74aaf8b45c4f135e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 10:06:02 +00:00
Joel Kitching 21fdd89b0c cbfstool: add unprocessed flag for file exporting
Add an unprocessed flag (-U) which modifies how files are exported.
In the case of a compressed raw file, extract without decompressing.
In the case of a stage or payload, extract without decompressing or
converting to an ELF.

This can be useful for verifying the integrity of a stage or payload,
since converting to an ELF may not be a deterministic process on
different platforms or coreboot versions.

BUG=b:111577108
TEST=USE=cb_legacy_tianocore emerge-eve edk2 coreboot-utils chromeos-bootimage
     cd /build/eve/firmware
     /build/eve/usr/bin/cbfstool image.bin extract -r RW_LEGACY \
       -n payload -f /tmp/payload_1 -U
     START=$((16#`xxd -s 20 -l 4 -p tianocore.cbfs`))
     SIZE=$((16#`xxd -s 8 -l 4 -p tianocore.cbfs`))
     dd if=tianocore.cbfs skip=$START count=$SIZE bs=1 > /tmp/payload_2
     diff /tmp/payload_1 /tmp/payload_2
     rm /tmp/payload_1 /tmp/payload_2

Change-Id: I351d471d699daedd51adf4a860661877f25607e6
Signed-off-by: Joel Kitching <kitching@chromium.org>
Reviewed-on: https://review.coreboot.org/29616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16 09:47:35 +00:00
Nico Huber 674ed24075 util/docker: Unify local build targets
Add a `docker-run-local` target that is used as a template for the
local build targets (`docker-build-coreboot`, `docker-abuild`, and
`docker-what-jenkins-does`).

Note this changes the user for `docker-what-jenkins-does` which has
(ccache) issues if it's not `root`. Will be fixed in a follow-up.

Change-Id: I9088fb9211726cddc37b17ddf70170c2c382679e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:43:51 +00:00
Richard Spiegel b59c1f4345 util/cbfstool/cbfs_image.c: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.

BUG=b:118484178
TEST=Build CBFS with original code, run objdump and saved output. Added
modifications, build cbfs again, run objdump again, compared objdump outputs.

Change-Id: I30187de8ea24adba41083f3bfbd24c0e363ee4b8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:42:00 +00:00
Alex Thiessen 15aad88404 util/gitconfig: Add timeout test
Add a `util/gitconfig/test` subdirectory which will contain tests to run
as executable files, add a helper script.

Add a timeout test that verifies that gitconfig completes in under two
seconds (typical run time is ~30 ms). Add gitconfig tests to the
`testing` Makefile under the `test-tools` target.

Change-Id: Id46f905b9f782e67be97a65d10045c3345dc996b
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23280
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-15 09:07:05 +00:00
Patrick Georgi e874df9e0b util/scripts/maintainers.go: Add Gerrit reviewers config emitter
The gerrit reviewers plugin has a certain configuration format. Teach
maintainers to emit it when called with -print-gerrit-rules.

Change-Id: I92cfc905e0c1b03b7cf793a4324c392140a22060
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-13 17:44:36 +00:00
Patrick Georgi 62a27385fd util/scripts/maintainers.go: Introduce command line argument handling
First new option is -debug.

Change-Id: Ia6e9b3675449a0b1e6f5d7526ee999f925eaadb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-13 17:44:23 +00:00
Patrick Georgi 89bd4892b3 util/scripts/maintainers.go: Provide delimiters between maintainers
Help automated tools make sense of the output.
Instead of "[name 1 <email> name 2 <email>]", it now prints
"name 1 <email>, name 2 <email>". As long as there are no commas in the
maintainer names, they can be split easily.

Change-Id: I4a254f566404b081a08923bc7ceb49f02039aa2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29604
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-13 17:44:04 +00:00
Patrick Georgi 0cadafaac9 util/scripts/maintainers.go: Use a full glob parser
Instead of checking only for three cases, just use a glob parser (that
translates the glob to regex).

After that, maintainers src/arch/x86/memlayout.h emits:

    src/arch/x86/memlayout.h is in subsystem X86 ARCHITECTURE
    Maintainers:  []
    src/arch/x86/memlayout.h is in subsystem MEMLAYOUT
    Maintainers:  [Julius Werner <jwerner@chromium.org>]

The latter entry was invisible to the maintainers tool because its path
description wasn't in one of the supported formats.

Change-Id: I7e5cf4269415269552e35f2c73952ce3dff487e1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-13 17:43:43 +00:00
Patrick Georgi 2e5d6a8153 util/scrips/maintainers.go: Allow file to appear in multiple components
Without this change, the tool only reports the first hit. We want to see
all of them.

Change-Id: Ib59b13c50b61c48e3cb200bf57e28c9453590819
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-13 17:43:28 +00:00
Patrick Georgi 92332635bf util/scripts/maintainers.go: Stub support for website tag
ME Cleaner's component has an entry specifying its website, which this
parser didn't know how to handle. Avoid the resulting warning.

While at it, de-C the switch statement and make it work go-style. This
also fixes "R" statements being ignored.

Change-Id: Ifc23e28daba9d85bf690557a80134accea8bed21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-12 21:13:32 +00:00
Patrick Rudolph aece006b38 util/intelvbttool: Cleanup and fixes
* Clear remalloced memory
* Fix check for invalid VBT offset in header
* Fix VBIOS checksum generation
* Fix VBIOS size field
* Align VBIOS size to multiple of 512
* Reassign pointers after use of remalloc
* Don't leak on error path

Current version is enough to allow the proprietary Windows Intel GMA
driver to find the VBT in the legacy VBIOS area and it doesn't BSOD
any more.

The LVDS screen remains black, due to an unknown issue with the
proprietary driver, while the VGA works.

Tested with libgfxinit and native graphics init.

Change-Id: If07b1bb51d8fb3499d13102f70fedb36c020fb72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12 18:41:12 +00:00
Patrick Georgi 4cec6b6d93 board-status.html: improve instructions
The foreword mentioned that you need a gerrit account, but not how to
have git push with the right credentials.
To ease onboarding, point out where to get them.

Change-Id: I0b022bc064e3bc89568617c1a3a3e0e5236ba520
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-07 21:42:34 +00:00
Nico Huber dd477e9ba3 coreboot-sdk: Build Clang first in a separate step
If we build one of the `all*` targets, build Clang first. Compiling
Clang (just for the host arch, I assume) takes more than half of the
time of the default build. When run as a separate step, we can make
use of Docker's cache if any step after Clang fails.

Change-Id: If67b458cde656f1dc6774215f6a575a48d12b797
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-05 21:33:13 +00:00
Nico Huber b133c61a91 coreboot-sdk: Prefer gnat package over gnat-6
The choice of `gnat-6` was originally an optimization because the meta-
package `gnat` installs not only the current GNAT version but also other
unwanted (and hard to explain) dependencies. Later it was necessary
because GCC 8 couldn't compile our older crossgcc.

Now that we switched crossgcc to GCC 8.1, `gnat` should be fine.

Change-Id: Ica8a1f9d6d71a74ffc4ec76aa0cfbe4b604cde1b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29454
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 21:32:22 +00:00
Nico Huber c8767058e4 coreboot-sdk: Don't install libisl-dev
The current version in debian:sid is incompatible with our crossgcc
version. But it turned out that we don't use the optimization features
enabled by libisl at all: crossgcc builds with and without (a proper
version of) libisl-dev installed generate the same coreboot binaries.

Change-Id: I9f9115d8ab33cbe11aa77f16c98465e1c1dedeac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-05 21:32:09 +00:00
Nico Huber 2c64a2c649 coreboot-sdk: Don't install libelf-dev
As by afda56e1ad (buildgcc: Drop libelf/elfutils), it's not used (atm).

Change-Id: I3124cb6db5975c21e635636babe700adb0f8cd8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-05 21:30:57 +00:00
Denis 'GNUtoo' Carikli 48c24ce5ee util/bincfg: code cleanup: convert sym_table to a local variable
Global variables are considered a bad practice.

Change-Id: I652a8da75498f871a53eb7509f6145c4842e3373
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/27810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-24 10:02:06 +00:00
Fehér Roland Ádám d5a8155f1b util/inteltool: Fix LynxPoint (non-LP) GPIO register map
The GPIO register dumper code for the LynxPoint family PCH chips
(Intel 8 Series and C220 Series) was incorrectly using a
shortened version of the LynxPoint-LP GPIO register map.
Switched to the correct register map for the affected chipsets.

Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f
Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com>
Reviewed-on: https://review.coreboot.org/29167
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 19:42:11 +00:00
Joel Kitching 672d5ad20b cbfstool: make comments more consistent
Fix a typo and make comments more consistent (start with
capital letter).

BUG=None
TEST=None

Change-Id: I97bff5e05596fc6973f0729e276a2e45b291120d
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-10-14 19:13:14 +00:00
Patrick Georgi c366f90a2e util/abuild: When using blobs, enable 3rdparty/fsp by default
This is a no-op on non-FSP systems, but enables using it when supported.

Change-Id: I66fe9b8587753ea017e13a752a7728e47287e9a0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-12 23:24:27 +00:00
Angel Pons 49c8de74ee util/superiotool/smsc.c: Add SCH5504 register dump
There is no datasheet available for this SuperIO, but dumping all
possible registers on a Dell Optiplex GX520 resulted in data that was
similar to other supported chips. Data also matches what is set in the
BIOS, e.g. the parallel and serial ports' addresses.

Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-10 11:19:01 +00:00
Nico Huber e3c05c4a3f util/cbmem/Makefile: Remove .dependencies on `clean`
Change-Id: Ic122b3eaed54e29bbb3e11de84822169c81c04eb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-09 07:08:18 +00:00
Angel Pons fa6ff60c8c util/superiotool/smsc.c: Add some register dumps
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.

The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.

Datasheets used:
 - SCH311X: DS00001872A
 - SCH5127: DS00002081A

Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-08 17:54:27 +00:00
Nico Huber d44221f9c8 Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.

Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.

Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08 16:57:27 +00:00
Patrick Rudolph 17856b720b util/intelvbttool: Rewrite tool
* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout

Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.

The required arguments have been changed:

./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]

SOURCECMD set the VBT source. Supported:
 inlegacy  : Legacy BIOS area at phys. memory 0xc0000
 invbt     : Read raw Intel VBT file
 inoprom   : Read VBT from Intel Option ROM file

DESTCMD set the VBT destination. Supported:
 outdump   : Print VBT in human readable form
 outvbt    : Write raw Intel VBT file
 patchoprom: Patch existing Intel Option ROM

Any combination of SOURCECMD and DESTCMD is possible.

Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-08 02:33:06 +00:00
Angel Pons a5072af67d util/autoport: Use romstage.c instead of early_southbridge.c
Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.

Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04 18:20:16 +00:00
Daisuke Nojiri 2b59c610d0 cbfstool: Clear entry being removed in all cases
Currently, an entry being removed is cleared only if the next entry
is also null or deleted.

This patch ensures the entry being removed is cleared regardless of
the next entry type.

BUG=chromium:889716
BRANCH=none
TEST=Run cbfstool bios.bin remove -n ecrw.
Verify bios.bin has 0xFF in the space of the removed entry.
TEST=Run cbfstool bios.bin remove -n fallback/payload (located at the end).
Verify fallback/payload is removed.
TEST=Run sign_official_build.sh on recovery_image.bin. Extract
firmware contents from chromeos-firmwareupdate in the resigned image.
Run 'futility vbutil_firmware --verify' for vblock_A's and FW_MAIN_A
extracted from bios.bin. See the bug for details.

Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04 17:16:41 +00:00
Jonathan Neuschäfer da6ad0bc50 util/abuild/abuild.1: Fix references to CBROOT parameter
One occurence of this parameter was changed from LBROOT to CBROOT in
f8ee1806ac ("Rename almost all occurences of LinuxBIOS to coreboot.").
Change the others, too.

Change-Id: Ic0da24c32cd6d2f0577de037b5463c800f455786
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04 09:39:08 +00:00
Evgeny Zinoviev e180825080 Documentation: add description for util/pmh7tool
Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-30 03:17:39 +00:00
Jonathan Neuschäfer ce8763fb13 mb/lowrisc: Remove the Nexys4DDR port
This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.

Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.

Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-26 15:36:40 +00:00
Patrick Georgi fcc2950a60 util/lint: Ignore "visible if" statement in Kconfig files
They allow reducing the visible set of options to remove clutter.

Change-Id: I18c953c7feae23c0752392a2bf8f49783c17310e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-18 15:00:44 +00:00
Paul Menzel b7b085dc65 board-status: Only store CBMEM console from last boot
Since CBMEM console became a ring buffer, logs from several boots can be
stored. We are only interested in the current boot.

>    -c | --console:                   print cbmem console
>    -1 | --oneboot:                   print cbmem console for last boot only

For CBMEM time stamps only the time stamps of the current boot are
stored, so only the commands for the CBMEM console need to be adapted.

Change-Id: I18caa4aeebbd5576b9e218d176a7db5a8e868b74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-17 13:53:02 +00:00
Hung-Te Lin 936dbe1d06 sconfig: Allow setting device status in device tree
For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.

The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.

BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve

Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-16 08:37:36 +00:00
Philipp Hug 2326a284ac riscv: add trampoline in MBR block to support boot mode 1
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.

Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.

Further changes are needed in the bootblock

Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-14 14:33:09 +00:00
Ronald G. Minnich 688eec1b97 lint-000-license-headers: add SPDX-License-Identifier: GPL-2.0-or-later
Change-Id: Icbf21b02d3092815bbe876eceea72ebba8dd54da
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-14 08:54:28 +00:00
Angel Pons 392e886552 util/superiotool: Add Winbond W83667HG register dump
This SuperIO is supported by coreboot and used in two Asus boards. However,
superiotool was lacking a register dump for this chip. Add the corresponding
data from datasheet W83667HG-B revision 1.3 into superiotool.

The SuperIO's datasheet was obtained by requesting it to Nuvoton.

Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-13 13:30:46 +00:00
Patrick Georgi dce4d465a6 util/crossgcc: Tell gcc that it'll use gnu as and ld
Otherwise it reduces its expectations on what as and ld take in terms
of arguments, which breaks some edk2 related builds because tons of
-I$path_to_stuff arguments aren't passed along.

Change-Id: I53f87442de03d5ead8a6632d3102d5502065b828
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 19:17:15 +00:00
Martin Roth ee0f225e3a util/lint: update whitespace checking rules
- Check payloads, the root Makefiles and toolchain.inc
- 3rdparty is already not checked, so remove
- The marks around COPYING, LICENSE, and README were not needed
- Skip checking .ico files

Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:56 +00:00
Martin Roth 8600893017 util/lint: Update whitespace linter for FreeBSD
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"

I found that changing this to other forms takes MUCH longer, so I left
the original method mostly unchanged except for moving the include &
exclude lists into variables.

Currently, I'm setting all non-linux operating systems to use the second
version. I'll update that if I find other that other OSes support the
first.

Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:18 +00:00
Martin Roth b7c0b8c8ee util/crossgcc: Add GCC 8.1 patch for missing backslash
When building the toolchain under BSDs, this missing backslash is
needed.

Change-Id: I40b0adaa73b241713493fd74f24c93f85e7aabbe
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28362
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02 03:09:46 +00:00
Evgeny Zinoviev 672f56166d util/pmh7tool: Add option to read specific bit
Change-Id: I045383eedbcf438270e9c64329a8d910bb941ab8
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-31 19:54:43 +00:00
Martin Roth b69ae97ada util/abuild: Use env to find bash
FreeBSD doesn't have bash in /bin, so use env to find it.  This is
already done in many other scripts that are used in the actual build
path.

Change-Id: If6fb6bc3c55835e2144599fea1cdb2f7abefb0fc
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-30 14:48:09 +00:00
Elyes HAOUAS 446e4d73cb util/ipqheader: Fix typo
Change-Id: Ibfcb870bb6e7ed747f8875520ab094def49e53cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-28 14:23:09 +00:00
Elyes HAOUAS 8fda8f4ac3 util/romcc: Fix typos
Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 14:22:24 +00:00