Commit graph

2867 commits

Author SHA1 Message Date
Matt DeVillier
404962f32c google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low
Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]

This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.

BUG=b:35648315

Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Tested-by: Rajat Jain <rajatja@chromium.org>

Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:53:55 +00:00
Matt DeVillier
eb7940d8b0 google/cyan: Mask Audio IRQ on boot
Adapted from chromium commit cf18ab6
[Strago: mask Audio IRQ on boot]

Do not start with audio interrupt unmasked; this causes interrupt storms
on newer kernels that no longer mask all interrupts when initializing
Cherryview pincontrol driver.

TEST=Boot various cyan boards with kernels 3.18 and 4.14;
verify everything works.

Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894688
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:53:46 +00:00
Matt DeVillier
0aa52739dd google/cyan: Mark GpioInt() resources as PullDefault
Adapted from chromium commit 3750e09
[Strago: mark GpioInt() resources as PullDefault]

coreboot considers GPIO resources first-class citizens and initializes
all pads according to their intended use, with necessary pull settings
applied. Therefore let's use PullDefault as pull qualifier in AML,
letting the kernel know that it should not attempt to alter pull settings
when using GPIOs.

TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices.

Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/898259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27760
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02 10:52:45 +00:00
Matt DeVillier
73b723d7db google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggered
Adapted from chromium commit 126d352
[Strago: switch Touchpad and Touchscreen interrupts to be level-triggered]

The Elan and other touch controllers found in this device work much
more reliably if used with level-triggered interrupts rather than
edge-triggered.

TEST=Boot several cyan boards, verify that touchpad and touchscreen
work.

Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894689
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:52:32 +00:00
Matt DeVillier
6444d7df0b google/cyan: do not hardcode virtual interrupt numbers
Adapted from chromium commit ee7a150
[Strago: do not hardcode virtual interrupt numbers]

Instead of hardcoding virtual interrupt numbers that may change as
the kernel changes, use GpioInt() resources to describe keyboard,
touchpad, and touchscreen interrupt lines.

TEST=Build and boot several cyan variant boards, verify keyboard,
touchpad and touchscreen work with newer kernels (4.14+).

Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iecfb45be433249d274532eb746588483fedb3f52
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:52:19 +00:00
Justin TerAvest
ed219ae306 mb/google/octopus: Enable EC SW sync for all
Since this works on Yorp and Bip, we should enable EC SW sync for all
known boards so that it doesn't get forgotten.

BUG=None
TEST=None

Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02 10:51:42 +00:00
Matt DeVillier
3044af7adc mb/google,samsung/*: Add LPC TPM chip driver to devicetree
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.

Test: boot various google/samsung boards, verify SSDT created with 
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux

Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01 22:23:54 +00:00
Gaggery Tsai
70627775f2 mb/google/poppy/variant/nami: Overwrite AC/DC loadlines
This patch adds a function to overwrite AC/DC loadlines for differnt
projects.

BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
     AC/DC loadline settings. Tested on Vayne and Akali.

Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-01 14:35:35 +00:00
nickchen
44a1ab2d05 mb/google/octopus: add lpddr4 skus for new memory sources
Add lpddr4 skus for new memory sources K4F6E3S4HM-MGCJ and MT53E512M32D2NP-046.

BUG=b:111964159
BRANCH=master
TEST=emerge-octopus coreboot chromeos-bootimage

Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f
Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 19:16:45 +00:00
Justin TerAvest
c9c954f681 mb/google/octopus: Enable EC SW sync for fleex
This never got enabled for fleex; we should enable this to make it
easier to have updated EC firmware.

With this commit, here's the relevant console messages:
sync_one_ec: devidx=0 select_rw=4
update_ec: Updating RW(active)...
Trying to locate 'ecrw' in CBFS
update_ec: image len = 137580
EFS: EC is verifying updated image...
send_packet: CrosEC result code 1
EFS: EC doesn't support EFS_VERIFY command
vboot_hash_image: No valid hash (status=0 size=0). Compute one...
print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd
Trying to locate 'ecrw.hash' in CBFS
sync_one_ec: jumping to EC-RW
send_packet: CrosEC result code 12
EC returned from reboot after 27753us

BUG=b:112038021
TEST=Successful boot after EC update via sync

Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-31 19:16:39 +00:00
Richard Spiegel
4665c593ef mainboard/google/kahlee: Update VBIOS image
The careena board requires a different setting within VBIOS in order to
pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS.

CQ-DEPEND=CL:1153080
BUG=b:111673328
TEST=Verify, via SOME unspecified method, that the new vBIOS is built into
the Grunt/Careena ROM files.

Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27643
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 00:50:28 +00:00
Patrick Rudolph
e67f626664 mb/google/stout: Use new PMBASE API
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30 18:59:20 +00:00
Patrick Rudolph
baea5994d8 mb/google/link: Use new PMBASE API
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:58:49 +00:00
Patrick Rudolph
ecb2399ab8 mb/google/parrot/smihandler: Use new PMBASE API
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:58:13 +00:00
Richard Spiegel
5d3707bbc3 mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, AGESA environment needs eDP high vdiff enabled.

BUG=b:111673328
TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and
boot grunt. Add new code to grunt, build and boot, verify eDP changed.

Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30 18:57:18 +00:00
Tim Chen
9b7e096073 mb/google/poppy/variants/atlas: Add new Nanya memory option
- add Nanya NT6CL256T32CM-H1 to memory strapping table

BUG=b:111906760
BRANCH=none
TEST=none

Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30 18:56:17 +00:00
Matt Delco
8928bc0d63 mainboard/google/nocturne: simplify camera power references
This change primarily moves the PowerResource up to a more common scope so
that the _PRx references are simpler. The ^ scope modifier isn't well
supported everywhere amongst OSes and drivers.  Windows 10 will BSOD
early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could
not find the object referenced by a _PRx) with the way things are currently
laid out).

I've also not seen a firmware outside of coreboot that tries to reference
count _ON and _OFF. Isn't it up to the OS to deference count, and whatever
it tells ACPI is what should happen (i.e., on means on and off means off)?

Some of the _UIDs are also duplicated.  This change makes them unique.

A few cosmetic changes are made so that diffing cam0.asl against
cam1.asl has fewer extraneous differences.

Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30 18:55:50 +00:00
Matt DeVillier
b89bd788be google/caroline: Change debounce time for jack insertion and ejection
Adapted from chromium commit 7633daa
[caroline: Change debounce time for jack insertion and ejection]

We are using max debounce time. During this time line, MICBIAS will be
zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE)
We need to reduce this time to below 100ms for caroline device.

BUG=b:79559096
TEST=see there is no more irq before jack insertion/ejection irq
complete

Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a
Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1143109
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>

Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:50:54 +00:00
Hung-Te Lin
1be16f08f2 google/kukui: Enable eMMC in bootblock.
On kukui board, the eMMC is routed to EC for boot ROM emulation when
loading bootblock, and should be set back to real eMMC as early as
possible after bootblock is loaded.

BUG=b:80501386
TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled.
BRANCH=None

Change-Id: Ifefb2e26ed048c38595907cc0875757410129828
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:50:09 +00:00
Nick Vaccaro
4f9ff53e42 mb/google/poppy/variants/nocturne: enable FPMCU power
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.

BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.

Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:48:43 +00:00
Nick Vaccaro
d091cd1fc1 mb/google/poppy/variants/nocturne: enable ec host event wake
Enable nocturne to wake from lid attach/detach events.

BUG=b:111803637
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has
commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne
wakes from suspend on a lid attach/detach event.

Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27649
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:48:33 +00:00
Alan Chiang
e81b2e4712 mb/google/nautilus: Remove obsolete fields
Some fields were only required during early stages of IPU3.

Remove some fields that aren't used for the current version of IPU3.

BUG:None
TEST=Launch camera app and check if it works properly.

Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30 18:48:02 +00:00
Furquan Shaikh
520149dc63 mb/google/octopusi/variants/bip: Fix unused pins and those with external terminations
For unused pins, configure them as GPIO input and use the default
termination. For the pins where board has an external termination,
remove SOC's internal termintation.

BUG=b:110654510
TEST=On Bip, flashed image and verified that it boots to OS. Also
executed a few suspend resume cycles.

Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30 18:46:01 +00:00
Seunghwan Kim
2ee7f483b1 mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.

We would set GPP_D21 to high to change LTE tx power to normal mode as
default.

BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default

Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 06:12:06 +00:00
John Su
dc515b5aed mb/google/poppy/variants/nami: Fix fan is always ON
Add the new setting for fan performance state.

BUG=b:111860513, b:11865138
TEST=Fan do not run below trip point

Change-Id: I894460b8b418217e2477608094c37018437cbb78
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-30 02:36:30 +00:00
Martin Roth
7a3458432c mainboard/google/kahlee: Pad SPD serial Number with spaces
All of the other SPDs are padded with spaces to make them use the full
size of the serial number field.  The hynix-H5AN8G6NCJR-VKC SPD was not,
and that seems to be causing problems with some tools.

BUG=b:111903749
TEST=Mosys correctly identifies memory on board using that SPD.

Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-30 02:20:04 +00:00
Furquan Shaikh
4dc6646f53 mb/google/octopus: Perform EC init before bootblock gpio configuration
A variant might talk to the EC to get board id in order to identify the
right GPIO configuration. Thus it is important to ensure that the LPC IO
windows are configured before this. This change moves the call to
perform EC init before configuring bootblock GPIOs.

BUG=b:111933657
TEST=Verified that reading board id does not fail on phaser.

Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27671
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29 03:51:00 +00:00
Kevin Chiu
030ba1bff3 mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC error
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking:
ERROR Event: 04011200 Data: 0, 0, 0, 0

BUG=b:111901461
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27657
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28 04:21:50 +00:00
Tristan Shieh
131ff8ccec google/kukui: Add SPI NOR support
This patch sets SPI flash related configs and inits SPI bus 1 to
support SPI NOR flash.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27 05:35:43 +00:00
Matt DeVillier
2cc81dc4b7 google/caroline: Add missing audio codec info
Add audio codec definitions in devicetree, which were accidentally
dropped when upstreaming

Test: build/boot Caroline with GalliumOS 3.0a2, verify working audio.

Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27626
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26 15:50:55 +00:00
Matt DeVillier
ce31521611 google/caroline: Fix I2C2 ACPI device definition
Remove duplicate FMCN package for I2C2, since already generated by
the devicetree-linked generic i2c driver.  This fixes an ACPI parsing
error which resulted in the touchpad and touchscreen being non-functional.

Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad and
touchscreen functioning properly, no ACPI errors in dmesg.

Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26 15:50:46 +00:00
Furquan Shaikh
0a144fa583 mb/google/octopus/variants/phaser: Provide override GPIO config
This change provides override GPIO table for variant phaser depending
upon the board id. Additionally, early_gpio_table is also provided for
phaser since EN_PP3300_WLAN needs to be handled differently based on
board id.

BUG=b:111743717
TEST=Verified that GPIO configuration for the override GPIOs is
different than before with this change.

Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-26 15:37:08 +00:00
Furquan Shaikh
06a41f1f60 mb/google/octopus: Use newly added gpio_configure_pads_with_override
This change updates mainboard_init to call
gpio_configure_pads_with_override instead of gpio_configure_pads to
allow variants to provide overrides for the GPIO config table provided
by the baseboard.

BUG=b:111743717
TEST=Verified on phaser that GPIO config with and without this change
is the same.

Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26 15:36:44 +00:00
Aaron Durbin
e7f4780137 mb/google/octopus: update phaser touchscreen enable gpio
The next build for phaser swapped the gpio for the touchscreen
enable. In order to support previous builds the devicetree needs
to be updated at runtime based on board revision id.

BUG=b:111808427,b:111743717
TEST=built

Change-Id: I45ef05ea0b991d04d5bf410cd7a175913bf0bf5d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27638
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26 15:36:11 +00:00
Aaron Durbin
2fcc034705 mb/google/octopus: add variant devicetree update callback
The variants of the octopus family have their own schedule and needs
for modifying settings based on the phase of the build schedule while
also needing to maintain support for previous builds. Therefore, utilize
the SoC callback, mainboard_devtree_update(), but just callback into
the newly introduced variant_update_devtree(). The indirection allows
for the ability to move the call around earlier than the
mainboard_devtree_update() if needed while maintaining consistency in
the naming of the variant API.

BUG=b:111808427,b:111743717
TEST=built

Change-Id: If1c2f60cabe65b5f1c6a04dd60e056e50c4993df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-26 15:35:57 +00:00
Aaron Durbin
8c2852420c mb/google/octopus: remove unused variant_board_id()
The variant_board_id() API was never used on octopus because all
boards in the octopus family used the EC to get board id, i.e. they
all use EC_GOOGLE_CHROMEEC_BOARDID. Therefore, remove the code
and declarations so as not to cause confusion.

BUG=b:111808427,b:111743717
TEST=built

Change-Id: I4f9a24b46dd4262120075d3d42daf22015a3dd50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26 15:35:34 +00:00
Hung-Te Lin
03e9cb9b35 mediatek/mt8183: Enable bootblock self-decompression
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.

A fully functional bootblock (that can boot into verstage or romstage)
is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK)
is enabled, only 25088 (66%) bytes are needed.

Inspired from crosreview.com/1070018.

BUG=b:80501386
TEST=manually flashed into kukui and boots into romstage.

Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-26 11:34:05 +00:00
Pratik Prajapati
4c067c8550 nocturne: configure VR per Intel recommendation
These values are Intel recommended.
IccMax = 28A
DC and AC LL = 4mOhms
Pl2 = 18w

BUG=b:79666828
BRANCH=none
TEST=Enabled p-states with patch 
Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then
"emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi
image onto nocturne, boot to kernel and verify device stays alive and
responsive for several minutes without locking up.

Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27175
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26 11:33:05 +00:00
Pratik Prajapati
0545166485 mb/google/poppy/variants/nocturne: enable p-states
This patch enables p-states for nocturne which was disabled by commit
de31587a (mb/google/poppy/variants/nocturne: disable p-states). p-states
feature was disabled as a temporary work-around as system was getting
hung while booting up. Now with IMVP7 firmwware turning and hardware
rework the issue is not seen, so its safe to enable p-states.

BUG=b:79666828
BRANCH=none
TEST=cherry picked Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
patch and then "emerge-nocturne depthcharge coreboot chromeos-bootimage"
, flash spi image onto nocturne, boot to kernel and verify device stays
alive and responsive for several minutes without locking up.


Change-Id: I82d1516998cc26b789faa5d4e897feb06dc06020
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27257
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26 11:32:49 +00:00
Furquan Shaikh
d1b482c716 mb/google/octopus: Fix unused pins and those with external terminations
For unused pins in octopus baseboard, configure them as GPIO input
and use the default termination. For the pins where board has an
external termination, remove SOC's internal termintation.

BUG=b:110654510

Change-Id: I67ec62913b0ef47105289838218f5d74c004223c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25 21:35:22 +00:00
Furquan Shaikh
d7b88dcbcd mb/google/x86-boards: Get rid of power button device in coreboot
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button

Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.

On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.

Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.

This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.

BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.

Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25 18:52:40 +00:00
Philipp Deppenwiese
db70f3bb4d drivers/tpm: Add TPM ramstage driver for devices without vboot.
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.

* Add TPM driver in ramstage chip init which calls the tpm_setup
  function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
  in ramstage.

Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25 15:53:35 +00:00
T.H. Lin
770b0346ff mb/google/poppy/variant/nami: Add custom VBT for panel T8/T10
Fix VBT SSF setting for panel T8/T10 as Akali/Akali360 panel
has T8 minimum 33.3 ms and T10 minimum of 100 ms.

BUG=b:111530392
BRANCH=nami
TEST=emerge-nami coreboot chromeos-bootimage
Test & measure T8/T10 waveform

Change-Id: I642a1aa0b2d13b33e6113f94e73dfc77834766d4
Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-24 18:55:02 +00:00
Matt DeVillier
6b27c38f4a google/glados: use level trigger for touchpad interrupt
Coolstar's custom touchpad drivers for Windows require level triggering,
and the Linux drivers don't care/perform identically either way. Set
touchpad interrupt to level trigger, matching change made to other
Chromebooks.

Test: boot Windows 10 on google/chell, verify touchpad functional

Change-Id: Id5f145b8b24c04f9c6661710a0cda95f135293e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24 12:07:56 +00:00
Matt DeVillier
fefd8e7fde google/glados: enable VMX for all variants
Explicitly enable VMX, as some OSes (eg, Windows) need VMX
feature enabled and locked in order to fully support virtualization

Test: boot Windows 10 on google/chell, verify OS reports virtualization
enabled

Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24 12:07:20 +00:00
Matt DeVillier
bba1ee070d google/asuka: Add as a variant of glados
Add google/asuka (Dell Chromebook 13 3380) as a variant of
glados Skylake reference board:
- add asuka-specific DPTF, EC config, GPIO config, Kconfig,
    NHLT config, PEI data, VBT, SPD data, and devicetree

Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]

Test: build/boot google/asuka, verify correct functionality

Change-Id: I591578fea2514a28c75177835807c3f250904577
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27421
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24 12:05:42 +00:00
Matt DeVillier
ec975b0a4f google/cave: Add as a variant of glados
Add google/cave (Asus Chromebook Flip C302SA) as a variant of
glados Skylake reference board:
- add cave-specific DPTF, EC config, GPIO config, Kconfig,
    NHLT config, PEI data, VBT, SPD data, and devicetree

Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]

Test: build/boot google/cave, verify correct functionality

Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24 12:05:12 +00:00
Matt DeVillier
19e7060d7f google/caroline: Add as a variant of glados
Add google/caroline (Samsung Chromebook Pro) as a variant of
glados Skylake reference board:
- add caroline-specific DPTF, EC config, GPIO config, Kconfig,
    NHLT config, PEI data, VBT, SPD data, and devicetree
- add caroline-specific memory-init param to romstage
- adjust mainboard EC SCI events for boards with tablet function

Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]

Test: build/boot google/caroline, verify correct functionality

Change-Id: I611a4e76581ba2e5b42e1bc48b0a5b8c70f3598e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24 12:04:37 +00:00
Matt DeVillier
57dd073369 google/sentry: Add as a variant of glados
Add google/sentry (Lenovo Thinkpad 13 Chromebook) as a variant of
glados Skylake reference board:
- add sentry-specific DPTF, EC config, GPIO config, Kconfig,
    NHLT config, PEI data, VBT, SPD data, and devicetree
- add sentry-specific GPIO determination of which audio codec
    is present

Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]

Test: build/boot google/sentry, verify correct functionality

Change-Id: I783422aedac8b7fc52098eebd05b2061a1011b60
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27418
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24 12:04:26 +00:00
Matt Wells
c8e974f063 mb/google/kahlee: Update i2c timings
Change the I2c timings to the latest measurements.

BUG=b:72442912
TEST=Boot grunt

Change-Id: I6f9538d26b77ae952ad585e569b3a836e1a09da2
Signed-off-by: Matt Wells <dawells@google.com>
Reviewed-on: https://review.coreboot.org/27553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-23 08:10:05 +00:00