Commit Graph

28044 Commits

Author SHA1 Message Date
Nico Huber 44e89af6e6 soc/intel/skylake: Unify serial IRQ options
We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.

In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.

Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?

Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-01 10:07:10 +00:00
Matt DeVillier ff79341a80 payloads/tianocore: Add option for custom bootsplash
Add Kconfig options to use custom bootsplash file,
dependent on using MrChromebox's stable branch, with
help info conveying required file format.

Adjust Makefile to copy the custom bootsplash and
overwrite the default Logo.bmp file, handling both
absolute and relative paths, and restore the original
logo file after building so as to keep the working
directory clean.

Test: build with and without custom bootsplash, ensure
correct bootsplash displayed

Change-Id: I164f46777169801cff56633fd920bc81b7c8129a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-01 10:06:02 +00:00
Elyes HAOUAS f288b396bc src/arch/x86/acpi.c: Update ACPI table's revision numbers
Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-01 10:03:05 +00:00
Elyes HAOUAS 0d4de2a477 ACPI: Rename FADT model and set it to zero
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.

So set this value to zero as we are using greater version than ACPI 1.0.

Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01 10:02:29 +00:00
Subrata Banik c3d03b3197 drivers/intel/fsp2_0: Add more EFI return status into FSP2.0 driver
This patch adds few more required EFI return status into FSP2.0
drivers so that coreboot code can make use of those.

Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-01 10:01:38 +00:00
Werner Zeh 45e295b973 mb/siemens/mc_bdx1: Enable TPM2 on LPC
This mainboard has a TPM located on the LPC bus. Enable the driver for
it so that it is initialized and the ACPI table entry is generated.

Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01 10:01:22 +00:00
Kyösti Mälkki a37a1a65a7 util/cbmem: Improve utility description
Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01 10:00:46 +00:00
Joyce Toh ddbdf9a0fb mb/google/sarien: ALC3204 HDA verb table pin config change
On Sarien, change pin config of 0x19 (headset mic) and
0x21(headset headphone) to change jack location so that naming does
not use "Front" in the name."Front Headphone" --> "Headphone" so it
matches naming on Arcada.

BUG=b:126334749
TEST= verify with 'evtest' command that jack name is
"HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone"

Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61
Signed-off-by: Joyce Toh <joyce.toh@intel.com>
Reviewed-on: https://review.coreboot.org/c/31624
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01 01:57:31 +00:00
Xiang Wang 411a8b7a66 src/mb/sifive/hifive-unleashed: replace fdt in maskrom
The fdt in the maskrom cannot be used to start linux. The correct fdt
is dumped by replacing the bbl of the original firmware and used in
coreboot.

Correct the mac address in fdt by reading otp

Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/31047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-02-28 17:10:01 +00:00
Frans Hendriks c6d672fe1d src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area
Calculation of memory reserved by FSP is incorrect.
Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28 17:09:29 +00:00
Subrata Banik fa011db6f0 soc/intel/cannonlake: Add CometLake SoC support
This patch adds SOC_INTEL_COMETLAKE Kconfig option.

Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 17:08:27 +00:00
Puthikorn Voravootivat 805bd10ede mb/google/poppy/variants/atlas: Update DPTF parameters
Preliminary dptf change for Atlas
- Throttle charger using all temp sensors (not just ambient)
- Throttle charger with higher priority than CPU
- Update throttle temperature using data from surface thermistor
  in thermal chamber test

BUG=b:113101335
BRANCH=None
TEST=based on preliminary data from thermal chamber test

Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
2019-02-28 17:05:35 +00:00
Puthikorn Voravootivat 8997f67cf0 mb/google/poppy/variants/atlas: Add tdp_pl1_override value
Use 7w PL1 with DPTF throttle to enable better performance for atlas.

BUG=b:113101335
BRANCH=None
TEST=Recommend setting from thermal team. Build coreboot on atlas

Change-Id: Idcf44f213259634a507a013b31b410ed322e9479
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31627
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 17:05:18 +00:00
Frans Hendriks 255f35c2d2 src/soc/intel/braswell/southcluster.c: Config ISA DMA controller
ISA dma controller is not configured.
Add call isa_dma_init().

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28 17:04:12 +00:00
Frans Hendriks 9348413c61 soc/intel/braswell: Correct configuration of interrupts
The level/edge mode of PIRQ is not configured and i8259 PIC not initialized.
Add calls to:
- i8259_configure_irq_trigger()
- setup_i8259()
- write_pci_config_irqs()
to correct the configuration of interrupts.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28 17:03:49 +00:00
Frans Hendriks 3e8504a325 src/soc/intel/braswell/acpi/irqlinks.asl: Allow IRQ10 and 11 for all LNKx
IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates.
These interrupt numbers are added to all LNKx.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29287
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 14:16:14 +00:00
Richard Spiegel b28025a434 cpu/x86/mtrr/mtrr.c:Avoid static scan false positive
Static scan does not know the contents of the fixed MTRR descriptor, so
it has no way to eval the result for variable num_ranges. If num_ranges
is less or equal to 0, the for loop will not be entered, and the values
of fixed_msrs will not be set. Asserting that num_ranges is greater than
0 ensures the loop enters at least once.

BUG=b:112253891
TEST=build grunt

Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 13:57:07 +00:00
You-Cheng Syu c60c3269ec libpayload: cbfs: Check decompressed size when loading files
After loading compressed files in CBFS, we should check the decompressed
size is equal to the expected size. This might help us detect file
content corruption or compressor/decompressor bugs.

BUG=none
BRANCH=none
TEST=manually (we can still boot into kernel on Kukui, and verify that
     loading files from CBFS still works by seeing ChromiumOS firmware
     screen).

Change-Id: Ia756cc5477670dd0d1d8aa59d4160ab4233c6795
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31564
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 13:56:45 +00:00
You-Cheng Syu 5ec1d24974 libpayload: cbfs: Require input size and output size for cbfs_decompress
Currently, cbfs_decompress() calls ulzma() and ulz4f() for LZMA/LZ4
decompression. These two functions don't accept input/output size as
parameters. We can make cbfs_decompress more robust by calling ulzman()
and ulz4fn() instead. This could prevent us from overflowing destination
buffer.

BUG=none
BRANCH=none
TEST=boot into kernel on Kukui with COMPRESSED_PAYLOAD_LZMA /
     COMPRESSED_PAYLOAD_LZ4.

Change-Id: Ibe617825bd000ed618791d8e3c5f65bbbd5f7e33
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-02-28 13:56:26 +00:00
Nico Huber 08087a3e8a cpu/intel: Remove socket_BGA1284
Unused since the removal of `fsp_sandybridge`.

Change-Id: Iea31e341c3df680ed48db4f8734d9d0bde120be3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31646
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 13:49:17 +00:00
Nico Huber c570a0e713 cpu/intel: Rename socket_mPGA478MN to socket_p
These marketing names are much easier to distinguish. My
mnemonic: Socket M => up to Merom, Socket P => up to Penryn.

Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31645
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 13:48:58 +00:00
Nico Huber 1083a4d232 cpu/intel: Remove models 69x and 6dx
These came for the Socket 479 which is not supported anymore.

Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31644
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 13:48:37 +00:00
Nico Huber ec6d07a330 cpu/intel/socket_m: Remove models 69x and 6dx
These sneaked in and were never supported by this socket (nor expected
in the notebooks that have it).

Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28 13:48:20 +00:00
Nico Huber 4829af17e3 cpu/intel: Rename socket_mFCPGA478 to socket_m
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.

The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.

Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28 13:47:54 +00:00
Nico Huber 620e0f3f22 cpu/intel: Remove `socket_mPGA478`
Doesn't look like it could be used.

Change-Id: I8074df12d062bd15f2388b367b3698c9d3b7b5b6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28 13:47:21 +00:00
Maulik V Vaghela 64b82be3e3 mb/google/hatch: Add GPIO programming for GPP_C0 to GPP_C7
coreboot did not program all GPIOs from C0 to C7 correctly which are
SMBUS GPIO. Some of the GPIOs are left in default mode which is
native function but we need to configure as GPIO mode and provide proper
configuration as per schematic.

After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not
getting idle due to GPIO configuration and CSME was not getting power
gated due to SMBUS.

BUG=b:123702553
BRANCH=none
TEST=Check on hatch board. CSME was not getting power gated for s0ix.
After applying this patch CSME is power gated now

Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-28 13:46:47 +00:00
Furquan Shaikh 67a489fdb0 soc/intel/cannonlake: Disable ACPI mode on BS_DEV_INIT exit
Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of
pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it
more aligned with the behavior on other Intel SoCs. However, as the
PMC device is hidden, it never gets enumerated and so init function
does not get called for it. This change moves the call to disable ACPI
mode to exit of BS_DEV_INIT instead.

BUG=b:126016602
TEST=Verified that:
1. pmc_set_acpi_mode is actually getting called.
2. EC panic event gets logged to eventlog correctly.

Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31633
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 13:43:45 +00:00
Ran Bi a198c9d732 google/kukui: Add RTC initialization
Initialize RTC at ROM stage.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I9d9c68755e8a6ac65dd794211e6ccf06e5057567
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-28 13:42:25 +00:00
Ran Bi 47d46d0a18 mediatek/mt8183: Add RTC support
This patch implements RTC initialization.
1. initialization dcxo
2. rtc clock using dcxo 32k
3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN
4. rtc register initialization
5. refactor the driver common part

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-28 13:42:17 +00:00
Maulik V Vaghela 7bdae06170 vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
Adding header files for FSP for cometlake platform version 1034

Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-28 13:33:40 +00:00
Kyösti Mälkki 035876c4dd mb/intel/saddlebrook: Fix 2nd DIMM slot
Assumed broken during review and rebase. The
SPD at address 0x52 will appear at index 1.

Change-Id: I213853d2b981294554d8d1b254da476905a41c13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-28 10:35:22 +00:00
Kyösti Mälkki 7ba14406c3 intel/spi: Switch to native PCI config accessors
Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-28 10:34:43 +00:00
Kyösti Mälkki 17387f67ad intel/spi: Fix use of __SIMPLE_DEVICE__
Fix cases of using ENV_SMM where __SIMPLE_DEVICE__
should be used instead.

Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-02-28 09:55:42 +00:00
Maulik V Vaghela db9e9ac30d soc/intel/cannonlake: Add PCH series check for CML LP PCH
TEST=Verify PM_STS1 value is is not 0xFF.

Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 09:26:01 +00:00
Subrata Banik ba8af5807c soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device ID
This patch adds CML-U 2+2 SA DID into systemagent.c and report
platform.

Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31638
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 02:22:11 +00:00
Subrata Banik e87bdbba29 soc/intel/skylake: Remove redundant PM emulation timer macros
This patch removes duplicate pm timer emulation macros from soc
directory and makes use from common code msr.h

Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31610
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 02:21:44 +00:00
Martin Roth 3361120bc8 util/abuild: Set fatal asserts when running scanbuild
Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert.  This
change fixes that and allows us to add asserts to protect
against other failures.

Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27 19:33:43 +00:00
YH Lin 97278939ff flapjack: use sku_id 0 for un-provisioned board
Instead of using 2, 0 is now used for non-CBI provisioned board or
corrupted CBI board to confrom to the sku encoding.

BUG=b:123676982
BRANCH=kukui
TEST=test with un-provisioned board to verify the sku_id.

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce
Reviewed-on: https://review.coreboot.org/c/31623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27 11:10:49 +00:00
Kyösti Mälkki e613d704d1 console: Split loglevel for fast and slow
For fast CBMEM console use minimum BIOS_DEBUG level.
For other consoles, Kconfig and/or nvram settings
apply.

Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27 11:10:00 +00:00
Kyösti Mälkki 7132f259bf console: Refactor printk() varargs prototypes
Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27 11:09:31 +00:00
YH Lin 40f65425e4 ec/google/chromeec: fix the error status passing
Various instances of google_chromeec_command() can return non-zero number
(both positive and negative) to indicate error -- fixing cbi_get_uint32()
and cbi_get_string() so they follow the same convention.

BUG=b:123676982
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c
Reviewed-on: https://review.coreboot.org/c/31585
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:08:18 +00:00
Tim Wawrzynczak b47c633c31 rtc: Fix rtc_calc_weekday
This function appeared previously unused (called only from rtc_display, also unused),
but it returned an incorrect weekday.  Change the algorithm to use Zeller's Rule, a
well-known algorithm for calculuating weekdays.

Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27 11:07:11 +00:00
Rizwan Qureshi ec645cb086 mb/google/hatch: Initialize GPIO_PCH_WP early in boot
Initialize GPIO_PCH_WP early in boot. Update cros_gpios[] array with
GPIO_PCH_WP information. Also, Configure recovery mode GPIO as virtual
since hatch does not have one.

BUG=b:125943273

Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:05:38 +00:00
Rizwan Qureshi ba482d3972 mb/google/hatch: Select SD_PWR_EN Active high config
Hatch implements active high SD_PWR_EN and requires a workaround
in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low
in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.

BUG=b:123350329

Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:05:26 +00:00
Rizwan Qureshi 8aadab7e96 soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#
SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.

However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.

Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.

Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.

BUG=b:123350329

Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31445
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:05:13 +00:00
Rizwan Qureshi e64c25ca1a soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers
Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers.

BUG=b:123350329

Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:04:40 +00:00
Rizwan Qureshi 51749b2766 mb/google/hatch: update SD card detect GPIO
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO,
expose that GPIO for kernel to configure card detect IRQ.

BUG=b:123350329

Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:04:29 +00:00
Matt DeVillier ce529b6318 mb/google/cyan: fix RAM training on edgar variant
Adapted from Chromium commit 5351dc0d
[Edgar: To set the RX ODT limit and dram geometry with RAMID detection]

Several cyan variants require memory init parameters be passed to FSP 
for handling of specific Micron modules; without these, RAM init will
fail when loading training data from the MRC cache, and boot will halt.
This was missed when I upstreamed edgar along with the other cyan
variants, so add the required memory init parameters for edgar as per
its source Chromium branch.

Test: build/boot on edgar board with affected Micron memory 
modules, verify boot successful with populated MRC cache.

Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31615
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:04:00 +00:00
Patrick Rudolph 2201da3a8b soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE
To support measured boot, drop VBOOT_RETURN_FROM_VERSTAGE.
The SoC has enough CAR space to support a separate verstage.

Tested on OpenCellular Elgon.

Change-Id: I18022000f6f05df89d3037896ef627070bfcca06
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31568
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:03:07 +00:00
Furquan Shaikh ac8c60e011 soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init
PMC initialization on Cannon Lake happens earlier in the boot sequence
than other SoCs because FSP-Silicon init hides PMC from PCI bus. As
ACPI disabling was done as part of PMC init, it was being called
earlier than what other SoCs do. This resulted in a different order of
events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it
ended up clearing EC events (which happens as part of ACPI disabling
in SMM) before logging any events of interest that happen during
mainboard initialization.

This change moves the call to disable ACPI to pmc_soc_init just like
other SoCs to keep the order of events more aligned.

BUG=b:126016602
TEST=Verified that EC panic event gets logged to eventlog correctly.

Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-27 03:52:02 +00:00