The pep.asl file is being obsoleted by runtime generation, therefore
switch elkhartlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The pep.asl file is being obsoleted by runtime generation, therefore
switch jasperlake boards to this method.
soc/intel/jasperlake: Switch to acpigen PEPD
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Now that the PMC device is marked as hidden in devicetrees, the device
callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks.
Note that this moves PMC initialization from BS_DEV_INIT_CHIPS to
BS_DEV_ENUMERATE, which aligns with other Intel SoCs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If292728ad975ba803fed6abea879f6f634470a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The pep.asl file is being obsoleted by runtime generation, therefore
switch tigerlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The LPM enable mask is useful to have in more than one place, therefore
more the get_disable_mask() function and its helpers to lpm.c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The pep.asl file is being obsoleted by runtime generation, therefore
switch alderlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is a use-case for generating the AML bytecode at runtime for the
Intel Power Engine device, which comes in a followup patch.
BUG=b:185437326
TEST=verified on google/brya and google/dratini by dumping SSDT and
verifying the PEPD device matches what was previously in the DSDT:
Scope (\_SB.PCI0)
{
Device (PEPD)
{
Name (_HID, "INT33A1")
Name (_CID, EisaId ("PNP0D80")
Method (_DSM, 4, Serialized)
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x63
})
}
If ((Local1 == One))
{
Return (Package (0x01)
{
Package (0x03)
{
\NULL,
Zero,
Package (0x02)
{
Zero,
Package (0x02)
{
0xFF,
Zero
}
}
}
})
}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03)){}
If ((Local1 == 0x04)){}
If ((Local1 == 0x05))
{
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
{
\_SB.PCI0.LPCB.EC0.S0IX (One)
}
If (CondRefOf (\_SB.MS0X))
{
\_SB.MS0X (One)
}
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()
}
}
If ((Local1 == 0x06))
{
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
{
\_SB.PCI0.LPCB.EC0.S0IX (Zero)
}
If (CondRefOf (\_SB.MS0X))
{
\_SB.MS0X (Zero)
}
If (CondRefOf (\_SB.PCI0.RGPM))
{
\_SB.PCI0.RGPM ()
}
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the get_supported_lpm_states() function to set the respective FSP
UPD.
TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This function searches the known MCH device IDs for Alder Lake and
returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or
unknown.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit b90e6fdd25. Latest
releases of PSP does not load PSP verstage on S0i3 resume. Hence no need
to skip PSP verstage on S0i3 resume.
BUG=b:196400450
TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle
and then a reboot and ensure that the system boots to OS.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Right now the ACPI code doesn't support accessing the remote GPIO block
yet, so don't generate invalid remote GPIO access functions and warn
about those being unsupported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't
located right after the 4th GPIO bank, but instead at a different
location inside the APCIMMIO region. A difference to the first 4 GPIO
banks is that the corresponding GPIO MUX registers aren't in a separate
bank, but at the end of the remote GPIO region. So this remote GPIO
region only supports 48 GPIOs with a 32 bit configuration register each
and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the
remote GPIO region.
For now using the remote GPIOs from verstage on PSP isn't supported. To
support this, it would need to map acpimmio_remote_gpio and update the
pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a
few others.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB
helps in improving overall boot time since it reduces hashing and
body loading time.
Increasing it over 4 KiB doesn't result in significant improvement,
thus keeping the value at 4 KiB as of now.
Timing data:
Note that before Data is with 1 KiB block size.
|------------------------------------------------------|
| Stage | Block Size | Before | After |
|finished loading body| 4 KiB | 205,187 | 189,947 |
|finished loading body| 8 KiB | 205,187 | 188,708 |
|finished loading body| 16 KiB | 205,187 | 188,085 |
|finished loading body| 32 KiB | 205,187 | 187,793 |
|------------------------------------------------------|
BUG=b:188577893
BRANCH=None
TEST=Boot time for Brya improves by 20 - 25 msec
Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.
This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.
BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs
Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
From ACPI specification, version 6.2 Errata A:
A `duty_width` value of 0 indicates that processor duty cycle is not
supported and the processor continuously runs at its base frequency.
Because Broadwell sets `duty_width` to 0, processor duty cycle is not
supported, and the value of `duty_offset` is ignored. For consistency
with Lynx Point, set `duty_offset` to 0.
Change-Id: I68cb85ec32a6cceda0cea29d76df6c6219b78a40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers
and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO
MUX registers.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.
Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.
Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow to select the primary graphics device between the IGD and the
external PCIe GPU depending on the ONBOARD_VGA_IS_PRIMARY config.
The option sets the priority only. This means that if a high priority
is set for an external PCI device and it is not connected/not enabled,
then the device with a lower priority will be used, in our case it is
IGD.
TEST = Set PRIMARY_PCI and boot Linux on the Kontron mAL10 [1] with
the miniPCIe video adapter on the Silicon Motion SM750 controller. As
a result, the display connected to an external GPU device shows the
Tianocore logo + setup menu and the desktop.
[1] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The eventlog requires RTC to provide correct timestamps, so we have to
turn on the config and add the common drivers.
BUG=b:199003609
TEST=check timestamp in 'mosys eventlog list'
BRANCH=none
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. Disable external output reset signal in first WDT reset
to preserve WDT original reset reason for WDT issue in kernel stage.
2. After preserved WDT reset reason, do fully reset again by sending
external output reset signal.
BUG=b:194025005
TEST=boot to kernel ok and function test pass
Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com>
Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Since both functions are only called from one function each, inline them
into those functions. Also get_gpio_mux just returned the return value
of iomux_read8, so there were two functions with identical functionality
which shouldn't be the case.
Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This aligns the GPIO MUX access more with the GPIO control register
access and will facilitate adding support for the remote GPIO bank. Also
change the GPIO number argument type to gpio_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move those two functions near the top of the file to have all functions
that do the hardware accesses in one place.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use unsigned integers for variables that aren't supposed to become
negative.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ee037221b9818b0474fe0376323e522c1b3b516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the raw GPIO MMIO register access is now only used inside the
gpio_banks block, the gpio_read32 and gpio_write32 functions can be
moved to that block to reduce the visibility and enforce the usage of
the functions provided by the gpio_banks block.
The iomux_read8 and iomux_write8 functions can't be easily moved to the
gpio_banks block, since it's also used in the pre-SOC AMD chipsets that
use the ACPIMMIO access functions directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
The I2C code should use some GPIO API to access the GPIO registers
instead of accessing the GPIO MMIO regions itself.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84dff381ad86e0c7f879f0f079186aec9cafc604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
No need to do raw GPIO MMIO accesses when basically the same
functionality can be achieved by using existing APIs. Using the existing
GPIO API instead of raw GPIO MMIO register accesses allows containing
all direct GPIO MMIO accesses inside the common AMD GPIO code which will
be done in subsequent patches. Since the value parameter of gpio_set is
int, change the type of the val parameter of drive_scl to int as well
even though I'm not sure why a signed integer was used for this in the
common GPIO API. Since program_gpios already configures the SCL GPIOs as
outputs, gpio_set can be used in drive_scl which only sets the output
value, but doesn't configure the direction.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks similar to the same as before during the reset_i2c_peripherals
call, but due to the additional overhead of the read-modify-write to the
GPIO register instead of just a write, the pulse width gets about 50%
longer. Since the udelay call in drive_scl still has an open TODO to
make this configurable and the pulses being longer is in the safe side,
this side-effect can be addressed in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO
configuration register and drives it as output, so don't initially
configure the GPIO as input with no pull up/down. This is a preparation
to use the common AMD GPIO access functions instead of the raw register
accesses, since the gpio_set function only sets the output value, but
doesn't reconfigure the direction. Using gpio_output there instead would
reconfigure the direction as well, but would result in doubling the
number of MMIO accesses, so just configure the GPIOs correctly right
away to avoid that.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks exactly the same as before during the reset_i2c_peripherals call.
This was probed at the SCL pad of the unpopulated I2C level shifter on
the side that is connected to the SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get rid of several unused PCH PCI device macros. These macros expand to
a call to the `pcidev_path_on_root_debug()` function, which only exists
to debug bad code. If needed, these macros should be reimplemented with
the `pcidev_path_on_root()` function instead.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I366e064f3fe708b55fb381aee25b2795b1c61142
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There are multiple HECI clients in the CSE. heci_send_receive() is
sending HECI messages to only the MKHI client. Add an argument to
heci_send_receive() function to provide flexibility to the caller to
select the client for which the message is intended.
With the above change heci_send() and heci_receive() functions are
no longer required to be exposed.
In the follow-up patches there will be messages sent to one other
client.
BUG=None
BRANCH=None
TEST=Build and boot brya. HECI message send and receive to MKHI client
is working. Also, MEI BUS message to disable bus is working.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add tpch device information for thermal functionality under dptf
for alderlake soc based platform.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add PMC IPC commands information for FIVR control functionality.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently maximum VBT data size for Jasper Lake is 8KB, but Bugzzy
would use VBT data over 8KB. This change makes use of Kconfig option to
increase the maximum VBT data size to 9KB for Jasper Lake.
BUG=b:194029827
BRANCH=dedede
TEST=build and boot bugzzy and verify fw screen is loaded
Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57201
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: I10f859f30b260d012f0bc8755f32413d8b2cf267
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since the FSP binaries for Picasso are present in the amd_blobs repo,
select the ADD_FSP_BINARIES option if the Kconfig option to check out
that repo is set.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
