This patch makes Ampton EC wake up AP from s0ix when the state of
charge drops to 2%.
Demonstrated as follows:
1. Boot Ampton.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 2.
4. System resumes.
BUG=b:189540432
BRANCH=Octopus
TEST=Verified on Ampton.
Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350
Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56341
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_parts_uesd.txt that contains the new
memory parts used by primus and Makefile.inc generated by
gen_part_id.go using mem_parts_used.txt.
BUG=b:193813079
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For new MT8195 devices we will control mt6360 via EC,
so we have to add ec function of controlling MT6360 and
add CONFIG to separate them.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic2228f5b45173f0905ea66a3a1f00ec820e0f855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch sets the optimized FIVR configs for ehlcrb customized
based on the performance measurements to achieve the better power
savings in sleep states.
- Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5
states.
- Update the supported voltage states.
- Update max supported current, voltage transition time and RFI
spread spectrum.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the new definition of mt6360_regulator_id,
merge the MT6360 LDO and PMIC interfaces into one.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On MT8195 platforms with BC1.2, we have to use EC to control
MT6360 so the mt6360_regulator_id is redefined to match the
numbers defined in EC driver.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the variants can have different memory move the SPD related
content to the variant directory.
Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B.
BUG=b:193732051
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory MT40A1G16RC-062E:B
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.
Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.
Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The configuration of the setting `chipset_lockdown` doesn't have any
effect for most of the variants since their configuration of
`common_soc_config` overwrites the configuration of the baseboard's
devicetree. If `chipset_lockdown` is configured separately in the
baseboard devicetree, the variant overridetrees reuse its
configuration.
Thus, move `chipset_lockdown` out of `common_soc_config` in the
baseboard devicetree and configure it separately.
Change-Id: I595c042cf62680d61f60965710d382bfdcd81671
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the part number for all boards was "Grunt". This patch adds the
correct part number/name for all variants.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:193499785
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
We may want to use that flash vendor on future variants.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To be able to enable & disable PSP_verstage in the saved .config file,
the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a
select to a default with a prompt.
BUG=182477057
TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK,
verify that VBOOT_STARTS_IN_BOOTBLOCK is set.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.
Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up lockdown configuration and move it to the baseboard's
devicetree.
Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it
for the rvp8 variant for consistency as well.
Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains
identical. intel/rvp8 changes, as expected.
Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown.
Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If two generic devices use the same number, device coming later
overrides the earlier device, as a result of this the static.c has
only one device.
In the case where we have UFC set to UFC_USB, this will result in
no IPU device scope in SSDT, since its entry will be set to disbled
after UFC probe.
TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.
BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to reference correct USB port number for driver to
identify type-C port number correctly.
BUG=b:189476816
BRANCH=None
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Change-Id: I20c088ee81610155067abad086eba8d72f73ad60
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the kano variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:193052432
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KANO
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove register "generic.stop_delay_ms" and measure data, it still
can meet elan touchscreen specification that reset pull high to
I2C time > 150ms (T3 > 150ms).
BUG=b:185308246
TEST=Measure the T3 delay time is greater than 150ms on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the redrix variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192052098
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_REDRIX
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on tglrvp system
Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR
detect condition for boten/botenflex sku.
BUG=b:186174768
TEST=build and test on boten/botenflex
Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
touchpad:390.4 kHz
BUG=b:192601250
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and
provide a flashmap for partitioning. Select the used flashmap on variant
level to allow different layouts for different variants.
Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove Kconfig switches that are not needed for mc_ehl based mainboards.
Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
There will be more variants of this mainboard so prepare the scheme for
Kconfig to handle the variants properly.
Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a new mainboard called mc_ehl which is based on Intel's
'elkhartlake_crb'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Follow-up commits will
introduce the needed changes for the new mainboard.
Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Compared SSDT with this patch against DSDT without this patch, they are same
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
The caller is already passing the address to the required LTE reset and
enable GPIO. During memcpy, the address to that pointer is used which
will lead to copying undefined data. Fix the pointer/address used in
memcpy.
BUG=None
BRANCH=dedede
TEST=Build Kracko, Drawcia and Metaknight mainboards which use this
function.
Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Found-by: Coverity CID 1458053, 1458054.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
brya0 is a reference and development platform, therefore it would be
helpful to have Crashlog enabled.
Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The brya EC supports S0ix hang detection, but it was not enabled in
coreboot as well, masking that event out of S0ix, therefore add it in to
the EC S0ix wake mask.
TEST=After EC prints "Warning: Detected sleep hang! Waking host up!",
the host actually wakes up
Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Allow to use the 2nd COM port of the AST2400 which can be also used via
IPMI/serial-over-lan.
Change-Id: I6f9c85b1f5428d3c3acf7a2f20296134c4611b1e
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R.
Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated
with MT40A512M16TB-062E:R DDR4 memory parts.
BUG=b:192380070
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct
P-sensor.
BUG=b:192331122,b:181555900
TEST=check P-sensor driver can be probed without error.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tidy up the code that programs the PAM (Programmable Attribute Map)
registers. Introduce the `D0F0_PAM` macro and use it to replace the
magic `0x59` and `0x5a` values in the code. Adjust the range of the
for-loop to work with the `D0F0_PAM` macro, and properly indent the
loop's body.
Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Mainboard information can be found in the included documentation.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create the cappy2 variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192035460
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY2
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:55348
BUG=b:191897776
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add LTE modem to devicetree.
Configure GPIO control for LTE modem by fw_config.
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.
BUG=b:186393848
TEST=Build image and check with command modem status
Change-Id: I20450ae37e5047dba67211316515994bd2a09600
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.
BUG=b:178092096
BRANCH=dedede
TEST=Build and boot to OS to check LTE by modem status
Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `smbios_full_table_len` function to consolidate table
length calculation. The case where the length of a table equals the
length of the structure happens when a table has no strings.
Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Factor out some boilerplate code into a helper `smbios_carve_table`
function, which zeroes out the table memory and fills in the header
fields common to all tables.
Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The initial value of `len` is never used. Declare and initialise all
local variables in a single statement to avoid this problem.
Change-Id: Ieb96758f4cd19d9d3f8fdc543e8ca17db06a2123
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Where applicable, use the size of the associated variable.
Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf
BUG=b:191213263
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I3f6875ef438b147436605629445d346a56896a87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
set GPP_C3 and GPP_C4 as NC since LAN function removal.
BUG=b:190643562
Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function
Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.
BUG=b:184074997
TEST=Build and boot guybrush without error
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict.
BUG=b:181555900
TEST=check dmesg there are no IRQ request errors like below.
genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1)
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To set the Fibocom 850-GL module to USB mode, it needs to be disabled
when PCIe training happens, or it will automatically switch to PCIe
mode. This patch makes sure it's shut down when training happens in
FSP-M. It will be brought up in ramstage and will be available for USB
enumeration later.
BUG=b:187316460
TEST=Run lsusb from the OS and see that the Fibocom module is present
on USB.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures the bootblock portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
Setting the PCIE Reset happens in coreboot instead of in the FSP.
The Aux reset lines are anded with the PCIe RST line, so both have
to be brought up together. On v1 of guybrush, the PCIe reset line
also resets EC communication, so it must be brought up immediately on
that version.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
New kconfig parsers interpret $(var) themselves, leading to empty
fields. Old kconfig understands \$(var), so use that.
Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add configs for Herobrine variants. Also enable ec sw sync as this
should not be disabled by default.
BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B
./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B
Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide
full range backlight settings to the kernel.
BUG=b:190443612
Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
1. Add 2 port 2 endpoint
2. Add support for OVTI5675
3. Guard entries in override device tree by FW_CONFIG
MIPI UFC is on I2C2
This configuration is as per P2 schematics
BUG=b:190674542
TEST=Build and Boot on Brya
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When initializing eSPI early, guybrush has requirements to configure the
bus properly. Those are normally run in bootblock_mainboard_early_init,
but when setting up eSPI early, those have not run yet.
BUG=192100564
TEST=Build along with previous patch, eSPI works on guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To reduce power load, set unused GPIOs to NC and close
unused interface in devicetree. GPIOs and
interfaces are as below:
GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07
Interface: I2C1/I2C3/I2C5
USB: port2_3/2_4/2_6
BUG=b:185044041
BRANCH=dedede
TEST=Built bios and test, it reduces power load without affecting
device function.
Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
UFC on brya can be USB or MIPI
Add FW_CONFIG bit for this option
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:54292
BUG=b:186521258
TEST=Updated BB retimer FW from 3.4 to 3.5 without any device
connected.
Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify driver from hid to generic(ELAN0001 that used
generic driver without hid).
BUG=b:191620724
BRANCH=dedede
TEST=build bios and boot, touchscreen will work properly.
Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
CB:55452 uses FMAP instead of "cbfs master header".
The flash size statement in vboot-rw.fmd does not contain the start
address, resulting in a non-booting system.
Add start address to FLASH statement.
BUG = N/A
TEST = Boot Facebook FBG1701
Change-Id: Id05ad33babb416a37c657b25cdb1e98d47c1a56d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000.
This fixes build failure when selecting the option to validate the
layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR)
Test: build google/casta successfully with IFD validation selected
Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CBnT provisioning tooling in intel-sec-tools are now cbfs aware
and don't need to have a fixed size at buildtime.
Tested on OCP/Deltalake with CBnT enabled.
Change-Id: I446b5045fe65f51c5fa011895cd56dbd25b6ccc7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55821
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_parts_uesd.txt that contains the only
memory parts used by primus for Proto build and Makefile.inc
generated by gen_part_id.go using mem_parts_used.txt.
BUG=b:186091208,b:189169995
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
add memory configuration for chronicler,
based on schematic and gpio table, update gpio and devicetree settings for chronicler.
BUG=b:187318819
BRANCH=None
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
verify bootable with chronicler
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Error Could not add [key.vbpubk]: too big occurs, when Eltan verified boot is enabled.
Update value of VENDORCODE_ELTAN_VBOOT_KEY_LOCATION.
BUG = N/A
TEST = Boot Facebook FBG1701 with Eltan verified boot enabled.
Change-Id: I1faecd189915985df633ac74627fd872ce8867f0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
BUG=b:191213716
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid from using same the name AMDI5682 as Zork, changing to use
AMDI1019. The corresponding kernel change is on CL:2929864
BUG=b:189297564
TEST=Audio works with the corresponding kernel change.
Cq-Depend: chromium:2929864
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This motherboard is almost identical to the ASUS P5QL PRO,
with the only noticeable difference being that the ASUS P5Q SE
has a P45 MCH while the P5QL PRO has a P43 MCH. Few changes were
required.
Signed-off-by: Hunter Sell <alicelyralain@gmail.com>
Change-Id: I36612bac16a79f05f3fe57e535e4ba3c73790a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Makefile.inc to include three generic LPDDR4 SPDs for the following
parts for Gimble:
DRAM Part Name DRAM ID to assign
MT53E512M32D2NP-046 WT:E 0 (0000)
H9HCNNNCPMMLXR-NEE 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Set the GPIO configuration of gimble
BUG=b:191213263
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.
Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Temporarily set eSPI mux in verstage_mainboard_early_init.
Ideally cezanne code should have common function to do this and
mb-specific code would just call it, but for now PCI access doesn't work
in the PSP so we can't do it.
AMD team confirmed that the current PSP doesn't configure LPC so we
don't have to disable LPC when configuring eSPI mux so we can
temporarliy skip the LPC part here.
BUG=b:183149183
TEST=boot guybrush with psp_verstage
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
In order to enable ACP DMIC hardware runtime detection, indicate that
ACP DMIC is present.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated in the ACP device.
Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add weida touchscreen support for magister.
BUG=b:191633024
BRANCH=dedede
TEST=Build and verify that touchscreen works on magister.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
This selected by default if 3rdparty/fsp is used. There is no need to
override this behavior in the mainboard Kconfig.
Change-Id: I01ee2e90e0eceaa3100d911b5460cf99f413b185
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Config items depends on USE_VENDORCODE_ELTAN but are VBOOT specific.
Correct dependency of these items on VENDORCODE_ELTAN_VBOOT.
BUG = NA
TEST = Boot facebook FBG-1701 with possible combinations of Eltan
security.
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: Icd1c3e5c70ca562190308752f45aac734826649a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52132
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSP_Verstage will enable eSPI early in the boot sequence. If the
platform isn't using psp_verstage, the system can hang on the first
port 80h postcode that comes out because they aren't routed to an
active device until eSPI is configured.
BUG=b:191370340
TEST=Build without PSP_Verstage, verify system doesn't hang.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the GPIO configuration of primus
BUG=b:190643562
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I405561ae8a44d95ffdc526241f9c52761f67ed35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This motherboard is somewhat similar to the p8h61-m_pro, but also different.
It has two exposed RAM slots with a pinout for four, and it's an OEM
variant used in PCs ASUS sold in stores.
Signed-off-by: Hunter Sell <alicelyralain@gmail.com>
Change-Id: Id08349feb0aeaf21406f814f6d19bbe0d9312a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PEG bifurcation is strapped to x8/x8 on this board, but only the first
port is used. Disable the PEG device at 00:01.1 because it is unused.
Should fix booting with commit ae999503f6
(nb/intel/haswell/pcie.c: Add missing pre-ASPM init). The `config_of()`
function call added in that commit makes coreboot die if any PEG device
that is enabled by strapping is not present in the devicetree. While it
is true that the PEG code should not use `config_of()`, this PEG device
should still be disabled on this board as it is never used.
Change-Id: I16809e081f9a56ba2f1fdfcb4b8289d75161056b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Remove some redundant parts of devicetree comments. This used to happen
when using autoport, but has been fixed at some point.
Tested with BUILD_TIMELESS=1, Lenovo T440p remains identical.
Change-Id: Ie24b5430c7771c9ce4dda6c9a10d70ee9000df7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
An error in script did not set the attribute properly:
- Entry CS0 is not used as sensor, but as ground,
- Entry CS1 is used as the startup sensor.
This fixes a regression caused by commit
689c25b9d6 (drivers/i2c: sx9310: Replace register map with descriptive names)
EQ=b:173341604
BRANCH=volteer
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I92c01209031e9a917d95b1cb2537b0ce7b93e66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51893
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add devfn macros for some peripheral devices that are attached to PCIE
GPP Bridge.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I7c5433dff2329f13c282908e2b848405819347ff
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable Acoustic noise mitigation for blipper and set slew rate to 1/8
which is calibrated value for the board.
BUG=b:187760191
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test
Change-Id: I187702c23712416eaaaaf1e210dcfc6b2c560041
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
- set subsystem/subvendor ID to Realtek default, as the one dumped
from the vendor UEFI firmware provides no advantages
- Add a codec reset before setting the subvendor ID using the Azalia macro
for consistency with all other Realtek HDA codecs
- disable jack detect for the external mic on the 3.5mm jack, since it's not
currently working, so that the external microphone can be manually selected
Change-Id: Ib0f99e5088973a721c0a295899012c9aea5009cf
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- set subsystem/subvendor ID to Realtek default, as the one dumped
from the vendor UEFI firmware provides no advantages
- fix the number of verb entries, which excluded the 4 following the
pin configs
- issue the reset *before* setting the subvendor, and use the Azalia macro
- disable jack detect for the 3.5mm jack, both line out and mic, since
it's not currently working, so that the outputs can be manually selected
Change-Id: Icd961c3c5aec23cf61d6a9ad65c603c6dc04697a
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable FastPkgCRampDisable for all domains, set SlowSlewRate to fast/16
for all domains. This aligns the settings with the Librem 14.
Test: boot Librem Mini v2, observe high frequency acoustic noise reduced.
Change-Id: I10bc2a3e6b631b8c0b430e204f376aa9a81ac683
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Decrease SA slew rate to match other domains and reduce
high-frequency noise slightly.
Change-Id: I02cd93481f6bfba6249cb338a0e2f47d471a438e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write
protect signal is decoupled from the hardware write protect signal.
Instead, we'd like for it to mirror the software write protect status.
This commit simply checks the software write protect status of the SPI
flash and sets the CBI EEPROM write protect if it's enabled. To prevent
changing the WP signal at run-time, the GPIO configuration is also
locked down after the level has been set. If HW WP is deasserted, the
CBI EEPROM WP will be deasserted as well.
BUG=b:191189275,b:184592299
BRANCH=None
TEST=Build and flash lalala, disable SW WP by running `flashrom -p host
--wp-disable` from a root shell and verify that the GPIO is asserted
after a reboot. Export the gpio via sysfs and verify that attempting to
change the value of the GPIO is futile. Enable SW WP via `flashrom -p
host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs
and verify that attempts to change the GPIO value are futile.
localhost ~ # iotools mem_read32 0xfd6e08d0
0x44000200
localhost ~ # cd /sys/class/gpio/
localhost /sys/class/gpio # echo 217 > export
localhost /sys/class/gpio # cd gpio217/
localhost /sys/class/gpio/gpio217 # echo out > direction
localhost /sys/class/gpio/gpio217 # cat value
0
localhost /sys/class/gpio/gpio217 # echo 1 > value
localhost /sys/class/gpio/gpio217 # cat value
1
localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0
0x44000200
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To enable display, we have to:
1. Configure panel power and backlight
2. Configure eDP driver
BUG=b:189985956
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: Ida6c157a6a3bd904d3fa3dd2001385ced34f7711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55574
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the default rom size to 32MB and remove chromeos.fmd
because Chrome OS is not supported on EHL for now.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I49d9404eb901087037b5423a4a503c5271e14138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Turn on CBI and add helper functions for determining the board
configuration from the firmware config settings in CBI.
BUG=b:187316460
TEST=Built
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change also restores GPIOs to their proper settings for prior board
revs.
BUG=b:189362981
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
