Create a single function to determine if the 360 sensor board is present
on a device.
BUG=b:143701965
TEST='emerge-drallion coreboot'
Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Current design reset pin is connected to PLTRST.
GPP_E7 is stop pin for touch. Reserve reset pin for
next stage implement.
BUG=b:143733039
BRANCH=N/A
TEST=check touch screen can work properly
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Set GPP_E16 reset to DEEP.
BUG=b:143057255
BRANCH=N/A
TEST=Measure GPP_E16 from S0 to S5 has no glitch
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add second source touch pad with i2c address 0x15.
BUG=b:142629138
BRANCH=N/A
TEST=check new touch pad can work properly
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common
code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl
and nvs.h from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn off HDMI power when enter s0ix and S5.
BUG=b:143057255
BRANCH=N/A
TEST=Measure the power on GPP_E16 under s0ix and S5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I580e6094d48663d5c208fd82c7744485d899bcc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36224
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change GPP_B21 default to low. This can prevent power leakage
of non-touch sku.
BUG=b:142849034
BRANCH=N/A
TEST=Measure the power of non-touch sku, check GPP_B21 is 0V.
Boot up with touch sku and check touch functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Chrome OS firmware images have moved bitmap resources from GBB into CBFS
for a long time, so the GBB should only hold firmware keys and HWID,
that is usually less than 10k.
ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but
many recent x86 simply copy from old settings and may run out of space
when we want to add more resources, for example EC RO software sync.
Note, changing the GBB section (inside RO) implies RO update,
so this change *must not* be cherry-picked back to old firmware
branches if some devices were already shipped.
BRANCH=none
BUG=None
TEST=make # board=darllion,hatch,kahlee,octopus,sarien
Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the SPD data for MT40A1G16KD-062E:E
BUG=b:139397313
TEST=Compile successfully.
Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape
in the same way bash/zsh do. As a result, the decoded files ended up
with ASCII numbers instead of the decoded binary data.
Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Disable memory channel by HW strap pin. Using for factory
debug.
BUG=b:139773082
BRANCH=N/A
TEST=Rework HW strap pin and check /proc/mem_info
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Implementing logic base on sensor detection to determine SKU id.
BUG=b:140472369
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds SPD files for Drallion. Use spd_index
matrix to correspond mem_id. This can save the dummy spd index
to reduce the size of SPD.bin.
BUG=b:139397313
TEST=Compile successfully
Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.
TEST=Build and boot arcada_cml
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483
TEST='compile successfully'
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.
TEST=Build and boot sarien/arcada.
Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Drallion uses the same touch panel as Sarien. Copy the deivce
from Sarien.
BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on HW schematic to modify USB setting.
Drallion has two type C on left and two type A on right.
BUG=b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Based on HW schematic to modify PCIE setting.
BUG=b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Drallion will use soldered down memory and use
GPP_F12 to GPP_F16 indicates mem_id.
BUG=b:139397313
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.
BUG=b:139095062
BRANCH=N/A
TEST=Build without error
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
The current HWID for drallion is reported as invalid by chrome, generate
new valid HWID with the following command and taking last 4 digits.
`printf "%d\n" 0x$(crc32 <(echo -n '$1'))`
BUG=b:140013681
Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Drallion doesn't have on board LAN, remove GBE bin file config.
BUG=b:139906731
TEST=emerge-drallion coreboot chromeos-bootimage and check
image-drallion.bin not include GBE region
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mathew King <mathewk@chromium.org>
Drallion will use soldered down memory. Add dummy spd file.
BUG=b:139397313
BRANCH=N/A
TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These variants are to support the sarien and arcada boards
with CML SOC, the drallion variant will be used to support the
upcoming drallion board.
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
One case slipped past the review and rebase of 733c28fa42
(soc/intel/{cnl,icl}: Use new power-failure-state API).
Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.
BUG=b:138098572
Test=compiles
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
