The region top_of_ram -> cbmem_top is used by FSP and cbmem, but is
also just regular DRAM. Marking it as such improves the final MTRR
solution a lot and fixes MTRR starvation depending on the setup.
Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47868
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.
During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.
Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Tigerlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Drawlet
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies CSE Lite driver to use 'if' C-lanugage construct
instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts
of CSE Update related KConfigs to prevent appearing them in the menu.
TEST=Built the code for drawcia
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also,
use SMM_TSEG_SIZE in place of a magic number.
Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.
Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Only Google Eve uses a non-zero value, but it overwrites in C code.
Drop the devicetree setting, since no mainboard uses it.
Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The value for this setting is not used anywhere. Drop it.
Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure DPR to span the region between cbmem_top and TSEG base.
This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently it's not possible to add multiple graphics drivers into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics drivers can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace all duplications of fill_fb_framebuffer and provide a single one
in edid_fill_fb.c. Should not change the current behaviour as still only
one graphic driver can be active at time.
Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update USB & PCIe devices in ASL files as per EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS.
Also update device function number for GSPI #2 in asl file.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If166fefe567a857ca29527d0367197139efbf6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For EHL, SpiProtectionMode is added to HFSTS register #1.
The original Manufacturing Mode is detected via FpfSocConfigLock
instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode,
and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the southbridge_write_acpi_tables declaration from acpi.h to common
lpc_lib.h, as common LPC is always the caller. This removes a duplicate
declaration since all soc/intel devices use common LPC, but not all use
common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c
with the other acpi functions.
Note that this would have the reverse problem if there is ever a non-common
LPC device.
Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS
or North XHCI block has a similar enough PCI MMIO structure to make this
code mostly reusable.
1) Rename everything to drop the `pch_` prefix
2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI
controller
3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI
controller
BUG=b:172279037
TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via
EC; type on keyboard, verify it wakes up, eventlog contains:
39 | 2020-12-10 09:40:21 | S0ix Enter
40 | 2020-12-10 09:40:42 | S0ix Exit
41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1
42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109
which verifies it still functions for the PCH XHCI controller
Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
When EHL initial mainboard patch is uploaded, there are some build
errors caused by EHL soc codes. Here are the fixes:
1. include gpio_op.asl to resolve undefined variables in scs.asl
2. remove unused variables in fsp_params.c
3. rearrage sequences of #includes to fix build dependency of
soc/gpio_defs.h in intelblocks/gpio.h
4. add the __weak to mainboard_memory_init_params function
5. add the missing _len as per this patch changes
https://review.coreboot.org/c/coreboot/+/45873
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to lock down the DMI configuration
in dmi_lockdown_cfg() by setting Secure Register Lock (SRL)
bit in DMI control register.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables support for extended BIOS window by selecting
FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the
extended window in host address space.
BUG=b:171534504
Cq-Depend: chromium:2566231
Change-Id: I039155506380310cf867f5f8c5542278be40838a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
This change adds support to Lock down the configuration of
extended BIOS region. This is done as part of
fast_spi_lockdown_cfg() so that it is consistent with the
other lockdown.
Change includes:
1. New helper function fast_spi_lock_ext_bios_cfg() added that
will basically set EXT_BIOS_LOCK.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables caching for extended BIOS region.
Currently, caching is enabled for the standard BIOS region
upto a maximum of 16MiB using fast_spi_cache_bios_region,
used the same function to add the support for caching for
extended BIOS region as well.
Changes include:
1. Add a new helper function fast_spi_cache_ext_bios_window()
which calls fast_spi_ext_bios_cache_range() which calls
fast_spi_get_ext_bios_window() to get details about the
extended BIOS window from the boot media map and checks for
allignment and set mtrr.
2. Make a call to fast_spi_cache_ext_bios_region() from
fast_spi_cache_bios_region ().
3. Add new helper function fast_spi_cache_ext_bios_postcar()
which does caching ext BIOS region in postcar similar to 1.
4. If the extended window is used, then it enables caching
for this window similar to how it is done for the standard
window.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47991
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the SPI-DMI Destination ID for tigerlake
soc. This is needed for enabling support for extended
BIOS region. Also, implements a SOC helper function
soc_get_spi_dmi_destination_id() which returns SPI-DMI
Destination id.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0b6a8af0c1e79fa668ef2f84b93f3bbece59eb6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change enables support for configuration of extended BIOS
region decode window. This configuration needs to be performed
as early as possible in the boot flow. This is required to
ensure that any access to the SPI flash region below 16MiB in
coreboot is decoded correctly. The configuration for the extended
BIOS window if required is done as part of fast_spi_early_init().
Changes include:
1. Make a call to fast_spi_enable_ext_bios() before the bus master
and memory space is enabled for the fast SPI controller.
2. Added a helper function fast_spi_enable_ext_bios() which calls
fast_spi_get_ext_bios_window() to get details about the extended
BIOS window from the boot media map.
3. Depending upon the SPI flash device used by the mainboard and
the size of the BIOS region in the flashmap, this function will
have to perform this additional configuration only if the BIOS
region is greater than 16MiB
4. Adddditionally, set up the general purpose memory range
registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows configuring the General Purpose
Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality:
1. Add a helper function dmi_enable_gpmr which takes as input base,
limit and destination ID to configure in general purpose memory range
registers and then set the GPMR registers in the next available
free GMPR and enable the decoding.
2. Add helper function get_available_gpmr which returns available free
GPMR.
3. This helper function can be utilized by the fast SPI driver to
configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds details about the memory map windows to translate
addresses between SPI flash space and host address space to coreboot
tables. This is useful for payloads to setup the translation using the
decode windows already known to coreboot. Until now, there was a
single decode window at the top of 4G used by all x86
platforms. However, going forward, platforms might support more decode
windows and hence in order to avoid duplication in payloads this
information is filled in coreboot tables.
`lb_spi_flash()` is updated to fill in the details about these windows
by making a call to `spi_flash_get_mmap_windows()` which is
implemented by the driver providing the boot media mapping device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reserves the window used for extended BIOS decoding as a
fixed MMIO resource using read_resources callback in systemagent
driver. This ensures that the resource allocator does not allocate
from this window.
Additionally, this window is also marked as fixed memory region in
_CRS for PNP0C02 device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I42b5a0ebda2627f72b825551c566cd22dbc5cca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change enables support for a custom boot media device in fast SPI
controller driver if the platform supports additional decode window
for mapping BIOS regions greater than 16MiB. Following new Kconfigs
are added:
1. FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW: SoC can select this to indicate
support for extended BIOS window.
2. EXT_BIOS_WIN_BASE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is
selected, this provides the base address of the host space that is
reserved for mapping the extended window.
3. EXT_BIOS_WIN_SIZE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is
selected, this provides the size of the host space reserved for
mapping extended window.
If platform indicates support for extended BIOS decode window,
cbfstool add command is provided additional parameters for the decode
window using --ext-win-base and --ext-win-size.
It is the responsibility of the mainboard fmap author to ensure that
the sections in the BIOS region do not cross 16MiB boundary as the
host space windows are not contiguous. This change adds a build time
check to ensure no sections in FMAP cross the 16MiB boundary.
Even though the platform supports extended window, it depends upon the
size of BIOS region (which in turn depends on SPI flash size) whether
and how much of the additional window is utilized at runtime. This
change also provides helper functions for rest of the coreboot
components to query how much of the extended window is actually
utilized.
BUG=b:171534504
Change-Id: I1b564aed9809cf14b40a3b8e907622266fc782e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
