Commit Graph

32080 Commits

Author SHA1 Message Date
Arthur Heymans 0ca944b16f security/tpm: Drop CAR_GLOBAL_MIGRATION support
Change-Id: I1c09eda6164efb390de4626f52aafba59962f9c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37029
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29 09:08:33 +00:00
Arthur Heymans 344e86bb3b security/vboot: Drop CAR_GLOBAL_MIGRATION support
Change-Id: I9dee03da028b9111b685e325368815a86e444a47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-29 09:05:04 +00:00
Arthur Heymans 7255610d9f sb/intel/spi: Drop CAR_GLOBAL_MIGRATION
Change-Id: I693cf494522c3bc1e1697a09be3e98fcb6db634d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-29 09:04:49 +00:00
Arthur Heymans 5b0db35e0d vendorcode/siemens/hwilib: Fix current file string usage
The CAR_GLOBAL accessors likely hid a bug where strncmp/cpy was passed
a pointer to a char array instead of the char array.

Change-Id: I68788e47ef27a959d6e048e9385afcfb663cdebc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-29 09:03:41 +00:00
Arthur Heymans b6c9a5d797 vendorcode/siemens/hwilib: Drop CAR_GLOBAL_MIGRATION
TEST: BUILD_TIMELESS=1 results in identical binaries.

TODO: Is this code correct? The strncpy/strncmp current_hwi seems
wrong.

Change-Id: Icf44fee8f7f538df6c34dfbd98b852954d146896
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-29 09:03:18 +00:00
Kevin Chiu fba9f33187 mainboard/google/kahlee: add G2 TS support for careena
Add G2 GTCH7503 HID TS support
spec from G2: G7500 / Ver.1.2 (3, April, 2018)

BUG=b:141577276
BRANCH=master
TEST=emerge-grunt coreboot

Change-Id: I91e4f2b934b64b14bca20108037b721288d40942
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37318
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29 09:01:08 +00:00
Michał Żygowski a3ce27d3dd cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer.

SSE will be automatically enabled in bootblock_crt0 for platforms that
migrate to C bootblock. Because of that family specific CAR setup may
avoid additional code.

TEST=boot PC Engines apu1 and apu2

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29 09:00:16 +00:00
Michał Żygowski f3db2aea85 sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-29 08:59:43 +00:00
Arthur Heymans c1abf137ff Documentation/4.12-relnotes.md: Add SMMSTORE as production ready
Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37244
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29 08:58:07 +00:00
Arthur Heymans b52cc0e094 Documentation: Add SMMSTORE documentation
This documents the smmstore API.

Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-29 08:58:01 +00:00
Arthur Heymans ed50d85576 drivers/smmstore: Fix some issues
This fixes the following:
- Fix smmstore_read_region to actually read stuff
- Clean up the code a little
- Change the loglevel for non error messages to BIOS_DEBUG
- Use an incoherent rdev to potentially speed up reading access

TESTED on google/wolf with out of tree patch to hook up smmstore to
sb/intel/lynxpoint.

Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-29 08:56:43 +00:00
Peter Lemenkov bf5aacca2c mb/lenovo/t400/Makefile: Build gpio w/o subdir makefiles
Change-Id: Ia2e889fe72d746b71d92026e358c7471f56b381f
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-29 08:56:15 +00:00
Peter Lemenkov 30da30c1db mb/lenovo/t400/Kconfig: Remove default data.vbt path
Change-Id: Ib720d9ca57cf1ce640f168cd6aab654b53e92b82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-29 08:56:00 +00:00
Kyösti Mälkki b6e3618138 soc/amd/common: Remove guards on ACPIMMIO utils
If one wishes to use the functions guarded here, he
has to have datasheet open anyways. It should be clear
from there which regions are supported and which are not.

TEST=Reproducible build of google/aleena.

Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-28 16:12:31 +00:00
Maulik V Vaghela c2a05d143b soc/intel/tigerlake: select correct chipset based on soc Kconfig
Since we accomodate both Tigerlake and Jasperlake soc in single folder,
we need to select IFD chipset correctly based on soc.

Change-Id: I73cfe4f583da3a28c3b29d29a93ff62097130e27
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-28 10:53:40 +00:00
Kyösti Mälkki c9eae795d1 soc/amd/common: Fix indirect includes
Builds that would otherwise be reproducible are sometimes
broken due to added #include combined with __LINE__ used
in assert() statement.

Change-Id: If4a02393799a34bbae4f6e506052774526c1a969
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37266
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28 10:53:19 +00:00
Arthur Heymans 9f5c895ec7 mb/*/*/Kconfig: Drop redundant redeclaration of MAINBOARD_VENDOR
Change-Id: Ic92e08ae5b741889a8200d10ea8148e4b4384dc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37270
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28 10:52:27 +00:00
satya priya 5c44c4ac7d libpayload: Add BIT(x) macro definition
Add BIT(x) macro definition in libpayload.

Change-Id: I15ca2d3758d516cecf9edd60af47e7fdbd808c40
Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-28 10:51:49 +00:00
Jonathan Zhang c9ece506e0 pci_ids: Update Intel Lewisburg SMBUS PCI ID
Change PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS to PCI_DEVICE_ID_INTEL_LWB_SMBUS.

Ideally the abbreviation for Lewisburg should be LBG instead of LWB.
However, LWB is used for consistency.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Anjaneya (Reddy) Chagam <anjaneya.chagam@intel.com>
Change-Id: Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28 10:50:56 +00:00
Elyes HAOUAS 282171c105 mainboard/google: Remove unused include <stdlib.h>
Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-11-28 10:49:47 +00:00
David Hendricks 6572fe538a Documentation: Rework staging and commit information
This patch does two things:
- The CLI and Git Cola sections contained some duplicated information
  about pushing patches, which is now factored out into its own section.
- The draft workflow is now disabled, so that part has been reworded to
  describe how to submit a private patch.

Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-28 10:49:30 +00:00
Patrick Georgi c4b7ad4db5 util/release: Don't try to remove a file named like a long string
Change-Id: I81fcb58720fb20ac4f57e31e9f991f5009aba568
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-28 10:48:25 +00:00
Nico Huber 7b3e8730ee soc/intel/skl: Drop FSP_CAR remnants
FSP-T support was abandoned long ago for Skylake. With FSP1.1 support
also dropped now, it's more visible that this code is unused.

Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37251
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28 10:46:54 +00:00
Jacob Garber 693e04f5c6 arch/arm/include: Remove unused armv7 types.h
This header was originally copied from the Linux kernel. However, these
days all fixed-width integers are defined in stdint.h, and all of the
other typedefs in this file are kernel-specific and aren't used
anywhere, so we can drop it.

Change-Id: I6ee7acb5e12f4b4b7c4325cedcfee36b93ab6a3d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-28 10:46:37 +00:00
Julius Werner d618aaceae security/vboot: Use persistent context to read GBB flags
With the persistent vboot context coreboot no longer needs to read GBB
flags from flash itself -- it can just ask vboot for the cached result.
This patch removes the existing GBB code and provides gbb_is_flag_set()
(with a slightly better namespaced name) as a static inline instead.

Change-Id: Ibc3ed0f3fbeb53d630925d47df4dc474b0ed07ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-28 07:03:20 +00:00
Patrick Georgi 3e8ef1028d util/kconfig: Move coreboot specific changes into Makefile.inc
This eases maintenance of our kconfig fork.

Change-Id: Ia4bc0bf22e66457356b9f8fcbea9412792495bca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-27 23:27:29 +00:00
David Wu d492f01bf1 mb/google/hatch/var/kindred: Add ELAN touchscreen support
Add ELAN EKTH6918 USI touchsreen support.

BUG=b:131205495 b:127996093
TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage
     and check touchscreen work.

Change-Id: I8b003685cd7ee68738bcd4298b63a44d6e6118e4
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37236
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 18:55:03 +00:00
Vadim Bendebury c7fc199f40 cr50 i2c: add error message reporting TPM IRQ timeout
Various recent x86 SOCs have trouble registering short pulses
generated by the H1 to indicate that it is ready for the next
transaction.

This patch adds an error message to report this condition, which would
greatly reduce the amount of guesswork when troubleshooting new
platforms.

BUG=b:144002424

TEST=tried this code on the Drallion device exhibiting the problem,
     observed error messages in the coreboot log;

  $ grep IRQ ap.log
  Cr50 i2c TPM IRQ timeout!
  Cr50 i2c TPM IRQ timeout!
  Cr50 i2c TPM IRQ timeout!
  Cr50 i2c TPM IRQ timeout!
  ...

Change-Id: I5f6ee3986bed58e12fd0ec8cecbf35f46c9263c2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-27 17:29:31 +00:00
Marshall Dawson 12294d0c48 soc/amd/stoneyridge: Add selectable APU names
Add APU names of STONEYRIDGE and MERLINFALCON to Kconfig.  The existing
convention of SOC_AMD_PRODUCTNAME_PKG will be phased out.

Don't explicitely use the APU_STONEYRIDGE name yet when creating
default paths.  Prairie Falcon relies on the default setting, and this
will be addressed in a later change.

Change-Id: I2061b9b02f6e9def4e151fc38951ad8abb68df1d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-11-27 13:51:45 +00:00
Marshall Dawson 3ac0ab524b soc/amd/stoneyridge: Add selectable packages
The StoneyPI package supports Family 15h Models 60h-6Fh and 70h-7Fh
in FT4 and FP4 packages.  Add options for the packages.  The existing
convention of SOC_AMD_PRODUCTNAME_PKG will be phased out.

Change-Id: I60232ca099b813640742868db08aa66b32265f3b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-11-27 13:51:25 +00:00
Usha P 65a8c2e076 soc/intel/skylake: Clean up report_cpu_info() function
This patch makes below clean-up for report_cpu_info()
function.
1. Remove unused variables.
2. Make fill_processor_name function available in bootblock.
3. Reuse fill_processor_name.

TEST= Succesfully able to boot soraka and verify the
cpu_name "CPU: Intel(R) Pentium(R) CPU 4415Y @ 1.60GHz"

Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36840
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 13:50:33 +00:00
Surendranath Gurivireddy d367503147 soc/intel/cannonlake: Disable USB2 PHY Power gating
Workaround to disable USB2 PHY power gating to fix issue seen when
Apple 87W USB-C charger is connected in S0ix state on WHL platforms
(based on Intel's recommendation).  Issue is seen on CML platforms also.
So, disable power gating for Drallion too.

Add devicetree entry to set the flag to disable USB2 PHY power gating
for different CNL PCH based platforms

BUG=b:133775942
TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if
the system wakes up after that

Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com>
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 13:50:14 +00:00
Kyösti Mälkki b0f15f0f86 soc/intel/tigerlake: Fix smm_relocation_params
Platform is not yet build-tested, this should have gone in
with commit f5c0d61 intel/smm: Provide common smm_relocation_params.

Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-27 13:49:08 +00:00
Arthur Heymans 7d802a48f3 soc/intel/baytrail: Don't reinitialize SPI after lockdown
With the common southbridge SPI code reinitialization after lockdown
is not necessary, hence the SMM finalize call becomes a no-op.

Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36008
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 13:47:38 +00:00
Arthur Heymans b48d63359b soc/intel/baytrail: Use sb/intel/common/spi.c
This common implementation is compatible.

Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-27 13:47:11 +00:00
Angel Pons 4ff63d3a11 soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
Do it in coreboot code instead of letting FSP do it.

Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-27 13:45:49 +00:00
Matt DeVillier 941796a50d google/jecht: add libgfxinit support
Tested on Guado variant

Change-Id: Ie3a42d1d69d11eebda25e60572f5d9a7452144c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27 13:43:11 +00:00
Matt DeVillier 7ad1a34ea7 google/beltino: add libgfxinit support
Tested on Zako variant

Change-Id: I433863b34731584797456eee6c2d270868a4f13f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27 13:43:03 +00:00
Matt DeVillier 8cfffb4427 google/eve: add libgfxinit support
Change-Id: Id9d9d804dfc2301b8d2186aff7be331d5ddbf18a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27 13:42:48 +00:00
Matt DeVillier 64dc5c1d53 google/fizz: add libgfxinit support
Change-Id: Idd7bfa4a97770f525c3f25f04f90c4bf092e4ae1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27 13:42:38 +00:00
Matt DeVillier a2ac3ad5e5 google/glados: add libgfxinit support
Both linear framebuffer and vga text mode verified
on chell and caroline variants

Change-Id: I106e7bb761055581634176a112816be8447e6745
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27 13:42:22 +00:00
Elyes HAOUAS 3ba84c5950 crossgcc: Upgrade LLVM to version 9.0.0
Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:41:17 +00:00
Elyes HAOUAS 18315db8e0 crossgcc: Upgrade CMake to 3.16.0
Change-Id: Ib564217c4fdcb609fd6dfd4cb71288dd54ffe4bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:29:00 +00:00
Elyes HAOUAS a2fbddfabc crossgcc: Upgrade Expat to version 2.2.9
Changes: https://github.com/libexpat/libexpat/blob/R_2_2_9/expat/Changes

Change-Id: I591e4ed186bc8d46ff64161eddc488b640cad5fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:23:36 +00:00
Elyes HAOUAS 33847db3ce crossgcc: Upgrade Python to version 3.8.0
Change-Id: I1265e7df4d6c04aa1ccf0c65dc87e62bec5a4a35
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:23:08 +00:00
Elyes HAOUAS 2368681c83 crossgcc: Upgrade GDB to version 8.3.1
Change-Id: I380ba8678b22483b0d9c5fc558c0e08fd38778e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-27 13:22:48 +00:00
Elyes HAOUAS 18ecdbfeb8 crossgcc: Update binutils to version 2.33.1
Change-Id: I3bb6055383aa72153fffc70adc9cc446e5a0612e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36013
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 13:22:08 +00:00
Kyösti Mälkki 9266ce90c6 AGESA,binaryPI: Remove early_all_cores()
This was implemented to make sure it gets called before
attempting any PCI MMIO access. Now that we have one
central romstage_main() implementation this extra precaution
is no longer useful.

Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27 10:41:39 +00:00
Kyösti Mälkki 56397364c9 binaryPI: Drop CAR teardown without POSTCAR_STAGE
The remaining (active) binaryPI boards moved away from
BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now.

As the cache_as_ram.S is also used with AGESA, this slightly
reduces the codesize there for romstage and postcar as well.

This commit is actually a revert for the vendorcode parts,
AMD originally shipped the codes using 'invd' for the CAR
teardown, but these were changed for coreboot due the
convoluted teardown that used to happen with non-empty stack.

Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27 10:39:20 +00:00
Kyösti Mälkki 46f04cbb49 binaryPI: Drop BINARYPI_LEGACY_WRAPPER support
Drop all the sources that were guarded with this.

Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27 10:37:50 +00:00