In deltalake, there's no embedded controller and BMC version is
used to represent ec version.
TEST=Build with CB:45138 and CB:46070
Execute "dmidecode -t 0" to check if the firmware version is correct
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested on OCP deltalake. The console now shows up on the serial.
Change-Id: If4c412c1ca749f1feba47b2ce0beb52d0111be86
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Override smbios_fill_dimm_locator for type 17 Locator and Bank Locator.
Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS
is always enabled and it makes the code cleaner.
One sample type 17 table displayed as below:
Handle 0x0010, DMI type 17, 40 bytes
Memory Device
...
Locator: DIMM F0
Bank Locator: _Node0_Channel5_Dimm0
Tested=On OCP Delta Lake, the Locator and Bank Locator strings
are expected.
Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move and use the common xeon_sp/cpx/acpi asl for skx/.
There were only minor whitespace differences between the directories.
Update the mainboards to build the moved files.
TiogaPass coreboot.rom checked with BUILD_TIMELESS.
Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is selected by Xeon SP Kconfig already.
Change-Id: If1ef7f86b27d7be74912c9ad1f9c1efbda6233e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.
Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kconfig 5.8 interprets $(...) itself using environment variables, which
generally means that they expand to the empty string. \$(...) works
with both our current and new Kconfig with the desired behavior
(to pass it through unmodified).
Change-Id: I726567eeb61d2035560152677d2b4548c1472be9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested=On OCP Delta Lake, BMC SOL can see POST codes
Change-Id: I2c27055475e6dadcd4282cd1bf191a1b83150f02
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DeltaLake is a single socket server. Its platform design has 1 DIMM
slot per channel. There are 6 DIMM slots.
Configure DIMM_MAX to overwrite SOC default.
Change-Id: I47ecc81452fe59ed59fd3a239ffe329cbc031d7a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44048
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add driver for OCP specific ipmi commands. With this driver, OCP
specific ipmi command can be used after implementing functions here.
TEST=Build with CB:42242 on Delta Lake, select Kconfig option:
IPMI_OCP and add device in devicetree to open this function.
Use ipmi-util in OpenBMC to dump raw data and check if this
function work.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I2efa85978ec4ad3d75f2bd93b4139ef8059127ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform
Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to MP MB to port SMBIOS type8 data.
Tested=Use "dmidecode -t 8" to dump SMBIOS data,
and check if type8 tables are implemented.
Change-Id: I356e645774d78c623c1398c8b1473562e1529cf2
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested on OCP Delta Lake, the timer action can be set correctly.
Change-Id: I1013169e12455e01214d089c9398c78143af4df8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value in romstage. By default it would start the timer
and trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.
Add RO_VPD and RW_VPD sections.
Tested on OCP Tioga Pass.
Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the common driver to configure the GPIOs on the Delta Lake
platform as done for Tioga Pass in commit 89d2aa0. The GPIO
settings are dumped by inteltool with original UEFI firmware,
then use intelp2m to generate header file.
TEST=Dump GPIO settings by Intel ITP and check if match gpio.h.
Change-Id: I8005d4caa2d87b6831099bfec3a40246224f3cb5
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use macros to configure each of the IIO ports instead of an array
of some unknown parameters. This will clean up the code and make
it easier to read.
Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical.
Change-Id: I2911992435a6c93624525426d56212f821abb866
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When RTC failure is detected, send IPMI OEM command to issue CMOS clear.
This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS
clear command by resetting RTC data, erasing RW_VPD (TODO) and add a
SEL, then reboot the system.
Tested=on OCP Delta Lake, after removing RTC battery we can see the above
flow can be executed correctly.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Populate SMBIOS data from OCP_DMI driver read from FRU
2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting
PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add function to send POST start command to BMC. This function is
used in romstage and the POST end command will be sent in u-root.
TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,
root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1:
ipmid: POST Start Event for Payload#2
root@bmc-oob:~#
Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create SMBIOS type 9 by getting PCIe config from BMC.
TEST=Check SMBIOS type 9 is created correctly on different SKUs
Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Change PCH power policy. Set default of
POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power
state to S5 when power is reapplied after power failure.
TEST=Base on CB:42289, CB:43338 and build for Deltalake.
The following Kconfig options must be selected:
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select CPU_INTEL_COMMON_SMM
Boot the system and check the last bit of GEN_PMCON_B is set to 1
through ITP with command: pch.pm_dump
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Read VPD variable 'fsp_log_level' to decide FSP log level.
2. Define the default values when the VPD variables cannot be found,
put all the values to vpd.h for better documentation and maintenance.
Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable.
Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit a5ca4a0c75.
Reason for revert: Breaks coreboot tree because of non existent kconfig symbol
Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement sending POST start/end command to BMC.
TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,
root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST Start Event for Payload#1
2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST End Event for Payload#1
root@bmc-oob:~#
Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Delta Lake uses GPIO pin GPP_B20 for POST complete event,
BIOS needs to pull this pin low for BIC (Bridge IC) to start
reading sensors.
Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm
the pin is low.
Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not.
With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and
would be set to enabled if both places cannot find it.
Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable
and verified the results are expected.
Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: insomniac <insomniac@slackware.it>
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value. By default it would start the timer and
trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.
Tested on OCP Delta Lake.
Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In romstage get the config from BMC IPMI and update the IIO accordingly.
Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation
register values are expected.
Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on OCP Delta Lake.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are 4 slots in YV3, Location In Chassis should be 1~4.
Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct.
Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR
for OEM string 1 to 6, add string 8 for PCIE configuration.
2. Set the read PPIN MSR to BMC.
Tested on OCP Delta Lake.
Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sonora Pass server program was terminated.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42948
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result.
TEST=Check if the BMC IPMI reponse data is correct or not.
Change-Id: I675060299b486986ebc39d8f714615b3e13de89a
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add RW_MRC_CACHE flash region to hold MRC cache data.
With memory training skipped for subsequent reboots, the boot
time is reduced by 8 minutes on OCP Delta Lake server, when
FSP verbose logging is turned on.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OCP Delta Lake server is a one socket server platform powered by
Intel Cooper Lake Scalable Processor.
The Delta Lake server is a blade of OCP Yosemite V3 multi-host
sled.
TESTED=Successfully booted on both YV3 config A Delta Lake server
and config C Delta Lake server. The coreboot payload is Linux kernel
plus u-root as initramfs. Below are the logs of ssh'ing into a
config C deltalake server:
jonzhang@devvm2573:~$ ssh yv3-cth
root@ip's password:
Last login: Mon Apr 20 21:56:51 2020 from
[root@dhcp-100-96-192-156 ~]# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 52
On-line CPU(s) list: 0-51
...
[root@dhcp-100-96-192-156 ~]# cbmem
34 entries total:
0:1st timestamp 28,621,996
40:device configuration 178,835,602 (150,213,605)
...
Total Time: 135,276,123,874,479,544
[root@dhcp-100-96-192-156 ~]# cat /proc/cmdline
root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
