Commit Graph

22828 Commits

Author SHA1 Message Date
Julien Viard de Galbert 66c210ae37 mainboard/intel/harcuvar: update to set the HSIO lines configuration
Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22310
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:33:18 +00:00
Julien Viard de Galbert f528195bdf soc/intel/denverton_ns: re-factor HSIO configuration
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.

Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:32:53 +00:00
Patrick Rudolph 6a81184058 device/device_util: Add string for DEVICE_PATH_NONE
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE
can be translated to string and shouldn't be translated by
"Unknown device path type: 0".

Makes console output a lot prettier and readable.

Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots.

Change-Id: I08d471d8217f966e80daefe2d9971e357defde62
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-07 12:32:13 +00:00
Maximilian Schander 12217f2878 autoport: Fix nil pointer deref when run without bd82x6x
When autoport is run on a system without supported southbridge
it won't populate the coresponding data structure. By sanitiy
checking after PCI detection autoport can exit cleanly and
provide a sufficient error message.

Error was:
panic: runtime error: invalid memory address or nil pointer dereference
[signal SIGSEGV: segmentation violation code=0x1 addr=0x30 pc=0x4be595]
goroutine 1 [running]:
main.FIXMEEC(0xc42014af80, 0x14, 0xc42014afe0, 0x1a, 0xc4200a914f,
	0x4, 0xc4200a916f, 0xf, 0xc420149e60, 0x28, ...)
/coreboot/util/autoport/ec_fixme.go:14 +0x105

Change-Id: I6b0fcda76d33b0d3a0379c279f492160ce5add84
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07 12:31:21 +00:00
Jonathan Neuschäfer 67b3268fac RISC-V boards: Stop using the config string
RISC-V is moving towards OpenFirmware-derived device trees, and the old
functions to read the config string don't work anymore. Use dummy values
for the memory base and size until we can query the device tree.

Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:31:00 +00:00
Jonathan Neuschäfer 5a6e389747 arch/riscv: Use a separate trap stack
This is the lazy solution, as explained in the comment, but it works for
now.

Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:30:38 +00:00
Jonathan Neuschäfer c90f1d7be0 arch/riscv: gettimer: Don't use the config string
Accessing the config string doesn't work anymore on current versions of
spike. Thus return dummy pointers until we have a better solution.

Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:30:07 +00:00
Jonathan Neuschäfer 140a827daa arch/riscv: Drop mret workaround
Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.

Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:29:27 +00:00
Jonathan Neuschäfer 92f0513a0c arch/riscv: mprv_read_*: Mark result as earlyclobber
This fixes a case of mstatus corruption, where GCC generated code that
used the same register for the mprv bit and the result.

GCC inline assembly register modifiers are documented here:
https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html

Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:29:08 +00:00
Jonathan Neuschäfer 0c42cd3240 arch/riscv: Fix return type of mprv_read_u64
Change-Id: I3dc12feefe5f0762e27d2ad0234371e91313c847
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:28:37 +00:00
Patrick Rudolph 3dbd28470b lib/ramtest: Add comment
Add a comment about the tested RAM region size.

Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07 12:28:20 +00:00
Bill XIE 54f45c684c ec/lenovo/h8: Clear EC output queue before enablement
Sometimes (observed on Thinkpad T400s during cold boot) a few (only one
observed) garbage bytes may detained in the output queue of EC after power
up, and they should be cleared otherwise later communications will be
disrupted.

Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22181
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07 12:26:51 +00:00
Bill XIE eb4ded6925 ec/acpi: add mechanisms to clear EC output queue
EC's output could be considered as a queue, and sometimes (observed on
Thinkpad T400s during cold boot) a few (only one observed) garbage bytes
may detained in such queue after power up. Those garbage bytes should be
checked and discarded first before real interactions, otherwise they may
disrupt the interaction during EC's enablement, causing a locked rfkill.

Change-Id: Iee031306c02f5211a4512c6b4ec90f7f0db196ae
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07 12:26:42 +00:00
Julien Viard de Galbert c467334620 Microcode: add dependency to header files
When using microcode header and updating the header (due to a new
release of microcode during early development) the build system
doesn't detect the header change. This commit fixes this by adding
the appropriate dependency.

Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:16:58 +00:00
Denis 'GNUtoo' Carikli 76e387319b Makefile.inc: Cosmetics: Format blobtool commands similar to other tools
Change-Id: Iddb09d0838da119bfccd5443652ca7a6baa95c7b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/22126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-07 04:45:14 +00:00
Hal Martin 399d35fee0 cpu/intel: Add Intel FCBGA1023 socket support
This socket is used by 2nd and 3rd generation mobile SKUs from 2011-2013.

select SSE2 per review suggestion

Change-Id: I9306a3364ae15530c99ca3379cfa2057c5879681
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-07 04:39:14 +00:00
Marshall Dawson 3727708aef soc/amd/common/psp: Require PSP PCI definition in SOC
Remove the definition for the PSP PCI device from the common PSP
code.  Any APU using this source should have its own definitions,
and this allows for the device to move within the config space.

Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06 22:21:50 +00:00
Julius Werner 1ab8c01050 gru: Fix and export SPK_PA_EN GPIO for Scarlet
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.

This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.

Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-06 20:47:50 +00:00
Julius Werner 59e9080dcb endian: Fix bebitenc() to actually encode big-endian
bebitenc() just runs a downward loop over the same body as lebitenc().
That doesn't give you a byte-swapped result, it gives you the same final
value, just starting from the other side to fill it in. (Also, it
confused i++ and i--, so it really gives you a compiler error.)

The correct code needs to have the array index inverted relative to the
bit shift index to produce a big endian result.

Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06 20:46:37 +00:00
Bora Guvendik b202a01acd intel/cannonlake_rvp: enable CNVi bluetooth
Enable USB2 port 10 for CNVi bluetooth.

TEST=Boot to OS, verify bluetooth functionality.

Change-Id: I5f2390c149bf0de911efac09f54ccd641f51bbcd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-11-06 18:21:20 +00:00
Aaron Durbin 4239a1671c soc/amd/stoneyridge: consolidate addresses in iomap.h
Take the existing scattered around address space defines
and put them in iomap.h.

Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-06 16:11:23 +00:00
Aaron Durbin 733ad92c65 soc/amd/stoneyridge: start header file for iomap
Create a new header file, iomap.h, which serves as a single
place for providing the address space definitions. Remove
the amd_defs.h file that had a single define in it.

Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-06 16:10:45 +00:00
ren kuo 6d53c6bc6a mainboard/google/coral: Override VBT selection for astronaut
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.

Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)

CQ-DEPEND=CL:*496012
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
     Run on DUT and check panel sequence meets spec.

Change-Id: I580567decfccd78366c37181255015ac2cd76493
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-06 13:55:46 +00:00
Piotr Król 64f87f3541 util/docker: add support for crossgcc building params
In some cases users may want to build just one toolchain not all. This
patch introduces COREBOOT_CROSSGCC_PARAM, which by default is set to
all_without_gdb so previous behavior is not changed. Users can pass
different parameter eg. COREBOOT_CROSSGCC_PARAM=build-x64 to build just
x64 SDK.

Change-Id: I858ba09644b5b86a4b0e828e4f342aee5083be93
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-05 02:31:16 +00:00
Patrick Rudolph 0709dc0468 ec/lenovo/h8/acpi/thermal: Add ACPI fan control
Disengage the fan 10 degree below passive threshold as the automatic EC fan
control does not disengage the FAN even when CPU starts melting ...

* Add EC registers FAND and FANA.
* Add ACPI methods _AC0 and _AL0.
* Add fan device and PowerResource for fan control.

Tested on Lenovo T430:
* The fan disengages at 80°C and keeps running at full speed until temperature
  drops below 80°C.
* Fan can be disengaged using sysfs:
  /sys/devics/virtual/thermal/cooling_device0/cur_state
Tested on Lenovo T500:
* The fan disengages at 80°C and keeps running at full speed until temperature
  drops below 80°C.
* Fan cannot be disengaged using sysfs, but the current state can be read:
  /sys/devics/virtual/thermal/cooling_device0/cur_state

Change-Id: I075ff5c69676927db1c5e731294e18796884f97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21227
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 19:10:29 +00:00
Patrick Rudolph 3ab13a8691 ec/lenovo/h8/acpi/thermal: Add support for passive cooling
The ACPI spec requires _TSP, _TC1, _TC2 and _PSL for passive cooling.
_TSP already has been added in a previous commit.
Copy the coefficients used on google devices to activate the feature.

Tested on Lenovo T430:
 The CPU is throttled once the passive threshold has been reached.
Tested on Lenovo T500:
 The CPU is throttled once the passive threshold has been reached.

Change-Id: I922923a9029de77158988ac254bab4aad9536935
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-04 17:23:19 +00:00
Nico Huber 8b59b31514 cpu/intel/speedstep: Emit PPKG object for first package
Tested on Lenovo Thinkpad T500.

Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 17:23:11 +00:00
Nico Huber 4d211ac08d arch/x86/acpigen: Add function to write a CPU package
Emits a list of CPU cores, e.g.

  Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 })

Tested on Lenovo Thinkpad T500.

Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 17:23:06 +00:00
Aaron Durbin b2b2015be0 mainboard/google/kahlee: remove unused FILECODE macro
From what I can tell FILECODE isn't used at all in this file.
Remove it.

Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:59:32 +00:00
Aaron Durbin 3173d4444f soc/amd/stoneyridge: don't open code known literals
We have macros for register addresses. Use it for MMIO_CONF_BASE
instead of duplicating a literal again.

Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:57 +00:00
Aaron Durbin 174abc5180 soc/amd/stoneyridge: fix incorrect constants in macros
Hex constants need '0x' prefix. Clearly these weren't being used,
but they should be fixed properly.

Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:48 +00:00
Aaron Durbin 426dc8e827 soc/amd/stoneyridge: remove superfluous NULL field initialization
By definition in C, fields that are not explicitly initialized will
be zero'd out. Therefore, remove the redundant struture field
initialization.

Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:41 +00:00
Aaron Durbin 8dd4006161 soc/amd/common: remove superfluous NULL initializers on globals
Global variables that are unitialized in C programs reside
in the .bss section. By definition, this section is cleared
to 0. Therefore, remove the explicit NULL initialization because
it's completely unnecessary.

Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:35 +00:00
Aaron Durbin e3f7d44d3b soc/amd/common: remove use of LibAmdMemFill()
memset() exists for a reason. There's 0 reason to duplicate the
functionality but add extraneous parameters that do nothing. This
is just poor coding practices. Remove LibAmdMemFill() usage.

BUG=b:62240746

Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:28 +00:00
Lijian Zhao 7b2d1ae299 soc/intel/cannonlake: Add DSP support
Add dsp driver support for cannonalake, especially the scan_bus function
of Audio controller required.

TEST=N/A

Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04 00:44:03 +00:00
Lijian Zhao 9bb684a0ec soc/intel/cannonlake: Install common i2c
Add common i2c support for cannonlake.

TEST=N/A

Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 00:42:00 +00:00
Shaunak Saha f08ed7d790 src/mainboard/glkrvp: Fix ec_in_rw and wp
Change-Id: I513b26d39973d9714b531d1ab0755c66d19eb332
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:40:38 +00:00
Hannah Williams 96939ae694 soc/intel/apollolake: Fix nhlt blobs path for GLK
Change-Id: Iabea32654918575c952857145ee6edb165899baf
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04 00:38:25 +00:00
Aaron Durbin b1aa6114b1 cpu: assume SSE if SSE2 is selected
If the SSE2 Kconfig option is selected also select SSE.

Change-Id: I6ccba57d5ae13b8066f2f744cd739282ffd4fe73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-04 00:34:20 +00:00
Jonathan Neuschäfer 0781cbe1d3 sb and soc: Enforce correct offset of member "chromeos" in global_nvs_t
The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos").  Avoid this bug in the future.

Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04 00:33:26 +00:00
Jonathan Neuschäfer 7bd4715a70 commonlib/helpers.h: Include stddef.h
The definition of offsetof() uses size_t, which is declared in stddef.h,
according to POSIX. Include stddef.h directly to avoid relying on
implicit inclusion.

Change-Id: I221be02c332de55c9fcf7d86673709ed43dd5c3c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22230
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04 00:32:13 +00:00
Lijian Zhao ebd7c44d7b soc/intel/skylake: Update coding style for i2c
From comment from https://review.coreboot.org/#/c/22238/, the coding
style need to be update.

TEST=N/A

Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04 00:30:38 +00:00
Philipp Deppenwiese 86fd88407b include: Deactivate timestamp_get if kconfig option not set
If CONFIG_COLLECT_TIMESTAMPS not set all timestamp
functions should be deactivated by using a pre-processor
statement.

Change-Id: I8ac63ba7e4485e26dc35fb5a68b1811f6df2f91d
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:28:57 +00:00
Keith Hui 6b06abb461 asus/p2b: Move to EARLY_CBMEM_INIT
Change-Id: I0bf4d6318ade6e931db4f8b1af08db1f9f93c313
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-11-04 00:28:28 +00:00
Lijian Zhao 44e2abf38f soc/intel/apollolake: Move to common dsp driver
Move dsp driver implementation to common dsp driver.

TEST=Boot up and check dsp driver loaded or not in OS.

Change-Id: Ia2be1c9f18e0e110600bd56a0b6cb8d40ca5e01f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:27:24 +00:00
Lijian Zhao 7b6a8cec9b soc/intel/common: Add common dsp driver
Audio DSP pci driver can be common across different platforms.

TEST=N/A.

Change-Id: Ia9206657864b8795799dc71af54996017c1eec57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04 00:26:54 +00:00
Bora Guvendik af36f1d525 mainboard/intel/cannonlake_rvp: enable SD card
Set SCS SD enable FSP parameter and set card detect
gpio information.

Change-Id: Ic99466c0d2d59070418d765442ff6d217023803b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 23:59:52 +00:00
Maximilian Schander 17034d6f63 intelmetool: Print colored capabilities
In general more ME capabilities are considered harmfull, useless or
unwanted. Therefore an easy overview can be obtained by coloring in red
and green.

Taken from Change with id:
Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a
Add bootguard information dump support
https://review.coreboot.org/#/c/16328/

Change-Id: Ia911cc935d512174399aaf93bba982e071942212
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-03 23:58:41 +00:00
Maximilian Schander df5b83fe2b intelmetool: Do small cosmetic changes
Refining some of the code indentations and cosmetics to
build upon and import some in-review changes.

Change-Id: I0038a146bd899f150518c4832258a42792abaabb
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-03 23:58:08 +00:00
Paul Menzel 1812311645 southbridge: Remove trailing space in `dump_south()` output
Change-Id: I4df9f8ce1058a2bb219508d0c8d04e153d37131c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/5179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-03 23:54:41 +00:00