Commit Graph

288 Commits

Author SHA1 Message Date
Patrick Georgi f16fb73087 I thought that romfs infrastructure is done now, but there were some
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of
the different image layouts) for buildrom images. After the patch, these
issues are avoided by not adding payloads to the romfs image (they
wouldn't be read anyway). Both workarounds (in buildrom code for
romfs and vice-versa) aren't very pretty, but that's what our buildsystem
requires.
As I had to create a "communication channel" (via the romfs-support
files), I took the chance to also use it for compression
information, so if you configure lzma support, you'll get lzma
compressed payloads in romfs.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:17:05 +00:00
Patrick Georgi d107831182 The attached patch tries new style compression first and runs old
style compression if the command returned an error code (happens if
you run an old lzma with the new arguments)

Tested on new-style lzma only (as I lack a build environment with
old lzma), but I tested that the old lzma returns with an error code.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 15:57:58 +00:00
Patrick Georgi aed1f925a6 the attached patch is the last infrastructure change necessary for
romfs.
Everything else to make a target romfs aware happens in the targets.

What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file,
it's possible that the build of coreboot.rom fails in a romfs setup,
because the individual buildrom image is too small to host both coreboot
and payloads (as the payloads aren't supposed to be there). Thus, a
special case to replace the payload with /dev/null in case of a romfs
build.
There would be cleaner ways, but they're not easily encoded in the
Config.lb format.
3. config.g is changed to create rules for a romfs build

Targets should still build (they do for me)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 12:52:43 +00:00
Stefan Reinauer f834e20ba3 fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 17:17:30 +00:00
Robert Millan 420593e74d This fixes a shadowed declaration in multiboot.c.
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 14:11:19 +00:00
Myles Watson 2a63ea580a Kevin O'Connor said:
The bug is in src/arch/i386/boot/boot.c.  The inline assembly in
  jmp_to_elf_entry uses the "g" flag to pass in parameters.  However,
  "g" allows gcc to use stack relative addressing of parameters.

  Easiest fix would be to change "g" to "ri" - put the parameter either
  in a register or as an immediate value.

That's what this patch does.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20 18:29:49 +00:00
Stefan Reinauer b743885b43 Don't know if this is the correct fix, but it fixes compilation of the PPC
targets.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 15:15:15 +00:00
Stefan Reinauer efab4ba3bb This patch adds "high coreboot table support" to coreboot version 2.
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.

By moving the table to the high tables area (if it's activated), this problem
is fixed.

In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.

This patch also adds "table forward" support to flashrom and nvramtool.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 14:38:48 +00:00
Stefan Reinauer 6d07c932bb Fix all build problems on PPC except the _SDA_BASE issues caused by the
code expecting too old binutils(?).

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15 10:04:41 +00:00
Stefan Reinauer be7f79867e This, ladies and gentlement, is commit #4000.
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 15:42:27 +00:00
Myles Watson 47e42e5ebb Fix HIGH_TABLES introduced error when compiling without MP table
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-12 17:42:20 +00:00
Myles Watson 0b4c9f08c7 This patch makes the boards use a single amdk8_util.asl. There are only
whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.

It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 18:06:47 +00:00
Stefan Reinauer 43b29cf891 Fix mmconf (PCIe memory mapped config space access) support in v2. It was
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.

Create wrapper functions similar to the io pci config space ones.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:11:52 +00:00
Stefan Reinauer 8dcd50b155 fix a bunch of cast and type warnings and don't call the apic "nvram", that
doesn't make no sense. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:24:29 +00:00
Rudolf Marek 6b2e760f03 Small bug somehow slipped there. The method body length is incorrectly computed.
The attached patch fixes this. I did not spotted that because the return arg is
moved just outside of method and I have overseen the closing }
 
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-02 22:45:31 +00:00
Stefan Reinauer 36c83404a3 Some changes required to get yabel working on v2 (and they generally make
sense, too). Have one u64 instead of three.

In order to use the old bios emulator, you have to do nothing. (Default, if
CONFIG_PCI_ROM_RUN is enabled)

In order to use yabel in your target, you need to add the following lines to
your config:
  uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
  default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1

In order to use vm86 in your target, you need to add the following lines to
your config:
  uses CONFIG_PCI_OPTION_ROM_RUN_VM86
  default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01 10:16:01 +00:00
Stefan Reinauer 2b34db8d1d coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 20:10:20 +00:00
Stefan Reinauer 3c7f46b422 Generic approach of putting BIOS tables at the end of memory
(in addition to their low locations)

This adds the kontron 986LCD-M and the i945 as a sample.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27 23:09:55 +00:00
Carl-Daniel Hailfinger d58671c4bf Add QWord support to acpigen.
Add TOM2 to the K8 DSDT.

Thanks to Rudolf Marek for testing and fixing this patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 21:38:51 +00:00
Rudolf Marek f997b5554a Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 15:40:23 +00:00
Myles Watson 552b327ca3 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 21:30:06 +00:00
Myles Watson 94e340b22a Change 0x%p to %p. Thanks Stefan for catching the one I introduced in 3931.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-10 03:02:05 +00:00
Myles Watson c4ddbff706 Remove some warnings, mainly from format strings which didn't match the
arguments.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09 17:52:54 +00:00
Rudolf Marek 293b5f5225 Following patch adds dynamic ACPI AML code generator which can be used to
generate run-time ACPI ASL code.

Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
generated by new function k8acpi_write_vars (technically similar to
update_ssdt). But lot of nicer.
x
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-01 18:35:15 +00:00
Stefan Reinauer 94f17773ef fix inconsistent user interface naming. don't show compile paths to users
during bootup (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 19:21:47 +00:00
Stefan Reinauer 26d431a616 fix coding style (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 19:17:51 +00:00
Stefan Reinauer fc2e8edc23 Trivial stuff:
* fix a warning that should not be one.
* fix capitalization typo

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 19:17:11 +00:00
Patrick Georgi 4dad150849 Ignore some more sections, created by newer toolchains
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-11 00:35:30 +00:00
Rudolf Marek 79e532560c The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.
The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 17:34:15 +00:00
Myles Watson 43bb9cdddd This patch gets rid of all the implicit definition warnings for serengeti except get_nodes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 18:24:11 +00:00
Stefan Reinauer 045c348cf3 Move mainboard specific changes to the coreboot memory table into the
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13 20:51:34 +00:00
Robert Millan 81af3d4a00 [PATCH] coreboot-v2: Add multiboot support
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 20:20:54 +00:00
Jens Rottmann 5e5bef5fbd Speed up copying coreboot to ram by using "movsl" instead of "movsb".
Also use different console messages for copying and uncompressing, like
it's already done in similar code in other places.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 22:24:47 +00:00
Jens Rottmann 9a9e61b7ec Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not
getting assigned.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 22:20:48 +00:00
Carl-Daniel Hailfinger 2ee6779a64 The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 12:52:52 +00:00
Stefan Reinauer 830b17d3e3 fix ppc mainboards (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-27 08:51:11 +00:00
Michael Xie 06755e404e Patch for AMD RS690 chipset.
All the PCIe slots are enabled in this patch except power management.

Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:07:20 +00:00
Stefan Reinauer 912857ec6c fix lots of warnings for cache as ram builds (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03 10:35:06 +00:00
Stefan Reinauer 7a4f688f4f fix warnings, make mptable struct members explicitly packed, as they're
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:31:08 +00:00
Roman Kononov 96e3022cd4 This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai.
The change in tables.c protects the legacy x86 BIOS data segment
(0x400-0x4ff) from being used for storing coreboot tables. Some
bytes from the segment are used by the kernel and should not be
garbled.

The change in coreboot_table.c is not strictly necessary. It removes
some redundancy and confusion.

Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 23:22:59 +00:00
Patrick Georgi c2e8fd42b0 Adds a field to the serial port descriptor about the configured line speed.
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 06:41:12 +00:00
Marc Jones(marc.jones df22f780f1 Don't check exclusive IRQ fieldin the PIR table.
This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs. 

Signed-off-by: Marc Jones(marc.jones@amd.com)
Acked-by: Stefan Reinauer <stepan@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07 17:49:57 +00:00
Nikolay Petukhov 9c2255c66c Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*

This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.

Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.

I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.

The pirq.patch for IRQ routing logically consist from of two parts:

First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.

Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.

IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.

Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 16:59:27 +00:00
Ed Swierk 4f83d7ed96 oops. sorry, wrong checkin. This patch backs out r3155 and instead contains the
code it should have contained.

This patch updates the PCI IDs for Intel 3100 devices.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:43:04 +00:00
Ed Swierk 791265a367 This patch updates the PCI IDs for Intel 3100 devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>                                                                                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:27:50 +00:00
Yinghai Lu f327d9f954 Route device IRQ through PCI bridge instead in mptable.
Don't enable pin0 for ioapic of io-4.

1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
   for device under them in mptable.

Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20 17:41:38 +00:00
Patrick Georgi 3bbf2ff789 Add a new record type "console" for lbtable, and insert one record
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 14:12:54 +00:00
Patrick Georgi 8c2a0c1445 This patch adds a new record type for lbtable to provide information
about a serial port. If a port is defined in the board configuration,
add it to lbtable.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 18:28:18 +00:00
Stefan Reinauer ca374d455c rename linuxbios_* files, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:16:45 +00:00
Stefan Reinauer f8ee1806ac Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:08:58 +00:00
Stefan Reinauer 7e61e45402 Please bear with me - another rename checkin. This qualifies as trivial, no
code is changed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 10:35:56 +00:00
Rudolf Marek e6409f218c This patch adds support for MCFG table, which allows OS to find the
MMCONFIG for memory mapped PCIe config.

However this patch is not enough to enable it on Linux, Linux do not trust
BIOSes too much, so a small patch to kernel to disable the check if this
region is e820 reserved.

PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-03 12:50:26 +00:00
Stefan Reinauer 0dff6e3fa9 fix a whole bunch of warnings. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23 22:17:45 +00:00
Uwe Hermann a9838cf796 Add a common/global failover.c file which can be used by all
(or at least most) mainboards. This should put and end to
copy-paste'ing the same file again and again for every mainboard.

Fix the build for the MSI MS-6178 target (wrong location of the common
failover.c file).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13 08:38:24 +00:00
Peter Stuge 0888c3613c Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-07 09:17:00 +00:00
Yinghai Lu 47cb7c71c9 next part of YhLu's large patch. I am not sure whether the tables.c
changes are correct. If someone could look into this, thank you.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 20:27:40 +00:00
Yinghai Lu c29b546eb1 Part IV
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:59:11 +00:00
Yinghai Lu 30b4abeedc Part III of YhLu's patch from January 18th
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:57:42 +00:00
Yinghai Lu 21332b80d0 This is part of the outstanding mcp55 commit from January 18th. It will
likely break the build, since it is only a small part, but it needs to
go in at some point and doing it directory by directory makes things
easier.

Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:49:05 +00:00
Stefan Reinauer ba43064d32 Trivial patch:
* Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c
  and references to it.
* move config option decision to preprocessor instead of code
  since config options can not change during runtime
* slightly more verbose output in built_opt_tbl.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 12:14:51 +00:00
Carl-Daniel Hailfinger a81bb03b79 This patch splits console.c into 3 different files to get a better
overview of the code, facilitate future cleanups and reduce the
diff to Yinghai's tree at the same time.
No functional changes, only moving lines between files.
Copyright headers will be added later. Right now we benefit from
keeping the diff as small as possible.

Most of the work was done by Yinghai Lu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02 14:21:09 +00:00
Roman Kononov 57e700f4f4 great check-in message:
Linuxbios boots an Opteron motherboard with 1GB memory.

Linuxbios directly loads a recent linux kernel.
The memory layout is like this:

BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
   BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
   BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
   BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
   BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)

The f0000-f0400 region contains IRQ and ACPI tables.

At some point the kernel builds a resource table containing
all physical address ranges and type of hardware the addresses
are mapped to. The table is accessible via /proc/iomem:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
e0000000-efffffff : PCI Bus #03
    e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
    f4000000-f4ffffff : 0000:03:00.0
    f5000000-f5ffffff : 0000:03:00.0
    f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
    f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
    f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
    f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

As you can see, the 00000000000f0400-0000000040000000
region is not listed.

It is not listed because the kernel unconditionally adds
"000f0000-000fffff : System ROM" first (look for
"request_resource(&iomem_resource, &system_rom_resource)"),
and then the attempt to add f0400-40000000 range fails
because of overlapping.

The kernel does not care that the range is not listed there.
Kexec does. It uses the /proc/iomem file to instruct the
kexec system call how to place the segments of a new kernel
in the physical memory. Kexec fails to start a new kernel
because it cannot locate enough physical memory.

This must be fixed either in linux or linuxbios.

Assuming that linuxbios is to be fixed, I cooked a patch
which provides this memory layout:

BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
   BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
   BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
   BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
   BIOS-e820: 0000000000100000 - 0000000040000000 (usable)

The /proc/iomem contains:

# cat /proc/iomem 
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
00100000-3fffffff : System RAM
    00100000-00203c61 : Kernel code
    00203c62-00248c3f : Kernel data
e0000000-efffffff : PCI Bus #03
    e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
    f4000000-f4ffffff : 0000:03:00.0
    f5000000-f5ffffff : 0000:03:00.0
    f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
    f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
    f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
    f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

Kexec is happier with the patch.

Regards,

Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01 00:44:27 +00:00
Uwe Hermann 96206510e3 Change 'ram' to 'RAM' in user-visible output (closes #60).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-16 11:56:35 +00:00
Ed Swierk be13dc72d9 Apply linuxbios-rename-other-payload-options.patch
(Patch 2, refs #14)

Signed-off-by: Ed Swierk <eswierk@arastra.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 12:56:28 +00:00
Ed Swierk 1a7a5b49c5 Apply linuxbios-rename-compressed-payload-options.patch, refs #14
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 11:42:16 +00:00
Uwe Hermann 218e7ed10a Use the common LinuxBIOS license header (trivial). Refs #5.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-05 15:27:46 +00:00
Yinghai Lu ab9f49d2fa init.o
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-05 06:24:21 +00:00
Yinghai Lu 5f9624d211 CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in
serengeti_cheeatah


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 22:56:21 +00:00
Yinghai Lu 93a5a194c5 failover_failover apc lds
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 21:05:23 +00:00
Yinghai Lu d4b278c02c AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 20:46:15 +00:00
Ronald G. Minnich 53f486a3ea fix some really yuck stuff.
now things might work.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14 16:31:14 +00:00
Carl-Daniel Hailfinger cba07dd682 additions and mods for lzma.
Signed-off-by: Carl-Daniel Hailfinger
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14 15:12:36 +00:00
Stefan Reinauer 87f194dd9e this code is for writing the mp table, so only execute it when
we actually have one. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-19 16:58:43 +00:00
Stefan Reinauer 4f1cb23426 move mptable to 960k to 1M
https://openbios.org/roundup/linuxbios/issue55

This patch is a little bit enhanced, it keeps the ppc table consistent,
which Yinghai's original patch did not.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-19 15:32:49 +00:00
Stefan Reinauer e26d66e9dd fix handling of mkelfImage'd binaries
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-11 09:04:52 +00:00
Stefan Reinauer ead73689db add automatic payload compression method to LinuxBIOS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02 12:05:13 +00:00
Richard Smith 2a7352cb9d Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()
Default is 255.

This allows mainboard configs for working across various groups
of boards that differ a device that may not loaded.

If you search for a device that is not loaded and max buses is 255
then there can be up to a 8 second delay to search the entire PCI space.
Board configs that know thier max bus can limit this search space.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-23 23:12:21 +00:00
Yinghai Lu 9a791dffea new cache_as_ram support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03 20:38:34 +00:00
Stefan Reinauer d6edf7a904 update comments
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-05 00:19:52 +00:00
Yinghai Lu 6c02eb2cb5 indirect jmp with *
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-14 23:13:13 +00:00
Stefan Reinauer bd25fe979b applied 1202_ldscript.diff from issue 45. This fixes images smaller than 64k
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-03 23:12:07 +00:00
Stefan Reinauer 4bd0de0b2e add cmos checksum range to linuxbios table
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-03 22:39:23 +00:00
Stefan Reinauer 7ce8c54e2b 1201_ht_bus0_dev0_fidvid_core.diff
https://openbios.org/roundup/linuxbios/issue41
Lord have mercy upon us.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-02 21:52:30 +00:00
Stefan Reinauer 806e146e75 Applying 11_26_car_tyan.diff from Yinghai Lu.
NOTE: This will break the tree so it can be fixed up later



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-01 10:54:44 +00:00
Stefan Reinauer f622d598db - Apply 11_24_a_s1_core.diff from
https://openbios.org/roundup/linuxbios/issue24
- fix up for via epia-m



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-26 16:56:05 +00:00
Stefan Reinauer e0e137844a fix typos reported by Martin Ley
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-24 10:25:46 +00:00
Ronald G. Minnich 43225bc804 EPIA-M fixup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-22 00:07:02 +00:00
Stefan Reinauer 0d304c18e2 comment and unify lb_uint64 handling as discussed on the mailinglist
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-14 23:04:55 +00:00
Stefan Reinauer 2fd467ce3c reverting rev 2082
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-03 08:13:39 +00:00
Eswar Nallusamy ed00937103 ppc970 initial porting.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-02 17:32:49 +00:00
Greg Watson 8d4edc2fcd changes to support new ppc arch
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-20 01:44:21 +00:00
Greg Watson aa9ef4195a trying to compile...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 21:55:47 +00:00
Greg Watson 5fc3aa73eb get include files right
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 20:32:05 +00:00
Stefan Reinauer 6ab43fcc48 Updating FSF address in the code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-05 18:17:45 +00:00
Steven J. Magnani eccc357ea0 Abort cpu_initialize if we detect that we've lost a race.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:53:45 +00:00
Steven J. Magnani d94e1d6e9d Relocate the GDT to reserved memory, so it won't get clobbered by elfboot(), etc.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 18:41:30 +00:00
Li-Ta Lo 3d291aa6a2 more removal for obsolete VGABIOS support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-10 22:51:55 +00:00
Jason Schildt 043b409904 Undoing all HDAMA commits from LNXI from r2005->2003
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-10 15:16:44 +00:00
Jason Schildt 6e44b422b3 - Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.
- Special version for HDAMA rev G with 33Mhz test and reboot out.
        - Support for CPU rev E, dual core, memory hoisting,
        - corrected an SST flashing problem. Kernel bug work around (NUMA)
        - added a Kernel bug work around for assigning CPU's to memory.

 r2@gog:  svnadmin | 2005-08-03 08:47:54 -0600
 Create local LNXI branch
 r1110@gog:  jschildt | 2005-08-09 10:35:51 -0600
 - Merge from Tom Zimmerman's additions to the hdama code for dual core
   and 33Mhz fix.
 
 
 r1111@gog:  jschildt | 2005-08-09 11:07:11 -0600
 Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
 r1112@gog:  jschildt | 2005-08-09 15:09:32 -0600
 - temporarily removing hdama tag to update to public repository.  Will
   reset tag after update.
 
 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-09 21:53:07 +00:00
Li-Ta Lo 09952c1970 move x86 CAR related stuff to arch/i386/Config.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-26 18:27:13 +00:00