Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.
Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set DDI port 2 type to Display Port.
Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Inform AGESA to setup an I2S codec instead of an Azalia codec.
This is step one for audio to work. ASL to connect the
driver and the hardware is in a follow-on patch.
Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/19841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
AFAIR from reviews, writing the PMIR (aka. ETR3) register never turned
out to do anything useful.
Change-Id: I119fb1212f360a59b695e2dfef68e19c330d01ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The save_timestamp_to_cmos code was used at Sage before the early
cbmem was available. Update it to use the standard timestamp calls,
based on the rangeley implementation.
Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
For x86, we place the .id section at 4GiB - CONFIG_ID_SECTION_OFFSET.
To take effect, we have to guard the conflicting default placement in
`program.ld`. Also, as we only include the .id section into the boot-
block, guard it by ENV_BOOTBLOCK too.
Change-Id: Idc7cbd670ce4f75b7790ff8d95578683e355ba7e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20810
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The previous pre-commit script generates an error when a commit doesn't
actually generate a patch file. This happens in rare instances when the
only change in a patch is to update file permissions.
Update the pre-commit script to verify that there's actually a patch
before calling checkpatch. Also print that we're running checkpatch
so that it doesn't look like odd failures come from lint-stable.
Fixes Bug #132 - Problem with `lint-stable` when changing mode of file
Change-Id: I142610b6fc984b2b14fd6c634bc4e7f2880ba987
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In S3 resume, wifi is one of the wake sources.
If elog is enabled in config, then log wifi wakes in elog.
BUG=b:36992859
TEST= Build for Soraka. Do WoWlan during S3. Verify elog having update
on wake due to Wifi.
Change-Id: I7d42c5c81e0a3f7a3f94c3f6b7d2ebdf029d1aff
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This excludes files which are mostly spaces, which I felt should be
handled separately.
Change-Id: I33043a3090e2fc6e9d2fd81e8a5e46fb6cb0aa35
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add support for dumping Intel Software Guard Extension (SGX)
status. --sgx or -x is the command line switch to get SGX status.
The code iterates through all cores and reads MSRs to check if SGX is
supported, enabled and the feature is locked.
Change-Id: I1f5046c1f6703f5429c8717053ffe9c981cedf6f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20758
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As per discussion with CSME team, ME is NOT using PCI Config
Space register HFSTS2 Bit 10 to update ME power-gated status.
ME goes to CM0-PG state after ME device becomes idle after
Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C)
is being set.
And to retrieve the PG status of ME, one should read from the
PWRMBASE+offset 0x590 (which should give the value 0xF9) and
PWRMBASE+offset 0x594 (which should give the value 0xFF).
But, also it needs some time for the ME FW to go to idle state
and reflect these values in PWRMBASE registers after D0i3 bit
is being set. This does not happen instantly.
So, in coreboot, if we read the ME PG state in finalize.c, which
happens just after FSP Notify phase, where actually ME D0i3 bit
is set, we do not read the correct PG state values (i.e, 0xF9
and 0xFF).
But, once it boots to Kernel, if we read those same registers
through iotool mmio_read32 command, we get correct values.
So, removing the ME PG state prints from coreboot, since it is
actually showing wrong information, although ME Power Gating is
successful.
Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bettong board with the standard configuration is not capable of
running nvramui with the default size.
malloc error happens on PDC_makelines(). Resulting in:
Booting from CBFS...
Run img/nvramcui
Calling addr 0x00100000
initscr(): Unable to create stdscr.
exited with status 1
Change-Id: I56a0fb3319fe77599bf3dd6c328a0b70be60a348
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/20681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The functionality of the FAN controller is extended to provide a
lowest startup speed of the FAN. Add the parameter "fanmin" to
the fan_ctrl_t structure and initialize the value.
Change-Id: Ib2e093ed6f5fc29bbea879779eb4777eb371b937
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The parameter shall be FANStartSpeed instead of FANStartpeed.
Change-Id: I977da687ba8d9d0bad4c184cd0945ecaa52286ad
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ASL for the Elan touchpad driver connection in ChromeOS.
This is based on the Auron and Rambi ASL. The AMD ACPI code
doesn't have the auto table generation the newer Intel
Chrome SOC use.
Device visible to OS: /sys/bus/acpi/devices/ELAN0000
Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the ASL whitespace and formatting to match the iasl -d
style as other parts of coreboot.
Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD internal A-link (AAHB device) doesn't support an IRQ,
so remove it. This solves a conflict with the GPIO IRQ required
for touchpad operation.
Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.
TEST=Wifi card is detected and connect to an AP.
Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet.
Set continuous mode until the quiet mode feature is available. This
allows keyboard and other EC based interrupts through.
Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19840
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly
report in the FADT.
Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19836
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update GPIO settings based on the schematic.
Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update for a single DIMM with an SPD at address A0.
Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee does not use the AMD IMC. Remove the files and calls.
Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19832
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update for the Stoney Ridge FT4 package and the on chip UART.
Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19831
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the unused support code from the old multi-device hudson
SD controller. The binaryPI blob contains the correct steps
for setting up SD and the public BKDG doesn't completely document
the controller.
The sd.c file was using device IDs not associated with the Stoney
Ridge APU. The hudson_enable() code removed was also looking for
incorrect device IDs and the PM_MANUAL_RESET register doesn't
behave as the source indicates.
The SD default settings may be overridden. Future improvements
may include a few Kconfig options and a weak call to the mainboard
for overriding additional defaults.
BUG=chrome-os-partner:62580062
Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig selects for vboot and update the makefile to pick up
files to be used in verstage.
Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19756
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The format of the D14F3xA0 SPI Base_Addr register is different
than a traditional BAR. Change the function to preserve any
enables already in place. Change the AND mask to remove the
reserved field and the enables.
Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.
Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
AHCI spec explicitly states that we may poll.
TEST=Ran FILO on kontron/bsl6 and observed that the controller
always becomes ready during the first delay.
Change-Id: If34694abff14d719d10d89bc6771dbfa12065071
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is (thankfully) not done by coreboot any more for recent chipsets.
Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant
power management of the processor package. An active RAPL algorithm
leads to negative effects with our real time software.
Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Apollo Lake SoC supports configuration of Running Average Power Limits
(RAPL) for package domain. This feature is not required for all APL
mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power
Limiting Control it is not necessary to enable the RAPL algorithm per
default. For that reason make the RAPL configuration selectable.
Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If we dont have a constant TSC rate, timestamp table
has odd leaps and may appear to run backwards. Add
functionality to apply a factor such that all stamps
are in the same timebase.
Change-Id: Idab9c2c00e117c4d247db8cc9a2897640fa01edd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Marc Jones