Commit Graph

43547 Commits

Author SHA1 Message Date
Jakub Czapiga 6f3fd6358f tests: Add lib/cbfs-verification-test test case
This commit adds test case for lib/cbfs verification mechanisms.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 00:31:02 +00:00
Julius Werner 6813d561b2 cbfs: Make sure all cases of single file header corruption are isolated
The new CBFS stack was written to try to isolate cases of single file
corruption as far as possible and still make other files avaialble (at
least as long as verification is disabled and they can still be found at
all). For most cases of header corruption, it will just continue trying
to parse the next file. However, in cases where parts of the file extend
beyond the end of the rdev, we have been relying on the range checking
of the rdev API rather than doing it explicitly.

This is fine in general, but it causes the problem that these errors
cannot be distinguished from I/O errors, and I/O errors always make the
whole cbfs_walk() fail. That means we will not return a successful
result from cbfs_mcache_build(), and leads to an odd discrepancy in how
certain kinds of corrupted CBFSes are treated with and without mcache.
This patch adds an explicit range check to make the behavior consistent.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ice2b6960284bd0c19be35b0607e5e32791e7a64c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-09-01 23:57:14 +00:00
Jakub Czapiga 7c6081e02b tests: Improve test output readability
When running multiple tests, e.g. by using unit-tests target, it is hard
to differentiate, which output comes from which file and/or
configuration. This patch makes the output easier to analyze and
understand by using new wrapper macro cb_run_group_tests(). This macro
uses __TEST_NAME__ value (containing test path and Makefile test name)
as a group name when calling cmocka group runner.

Example:
 Test path: tests/lib/
 Makefile test name: cbmem_stage_cache-test
 Test group array name: tests
 Result: tests/lib/cbmem_stage_cache-test(tests)

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-01 19:38:09 +00:00
Karthikeyan Ramasubramanian c2310a16ad soc/amd/cezanne: Increase the FSP_M_SIZE configuration
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.

BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.

Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:36:20 +00:00
Jakub Czapiga c35659d930 libpayload: Move EXTRA_CFLAGS to enable option override
Before this patch EXTRA_CFLAGS were placed before many other options.
This made overriding impossible even, when necessary. This patch moves
EXTRA_CFLAGS to be placed after original CFLAGS, thus making option
overriding possible.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:34:20 +00:00
Wisley Chen b8461aab52 mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.

BUG=b:191931762
TEST=With CBI FW_CONFIG field set to 0x8,
set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree

dmidecode -t 11
OEM Strings
   AUDIO-MAX98390_ALC5682I_I2S_4SPK

Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01 19:32:43 +00:00
Furquan Shaikh b9c22e0965 util/sconfig: Compare probe conditions for override device match
When the override functionality looks for device match, check that
the probe list for both the devices matches exactly if probe list
exists for the base device. This ensures that if there are two devices
with same identity (e.g. I2C address or USB port #) but using
different properties (registers) controlled by different probe
statements, then the two devices are not incorrectly matched as the
same device.

The check for base device having a probe list is performed before
comparing the probe lists because a base device might not really have
any probe requirements at all. So, when overriding such a device,
there is no need to check for the probe list match.

BUG=b:187193527
TEST=Verified by adding two I2C devices in the override tree with the
same I2C address and chip but different probe statements and confirmed
that both the devices are present in generated static.c file.

Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-01 19:20:05 +00:00
Furquan Shaikh bf42db6eb7 mb/google/volteer: Move hda device enabling to override tree
This change moves the hda device enabling from baseboard device tree
to override tree for the variants that did not provide any hda
specific nodes. This ensures that the probe statements are correctly
selected by the variant depending upon the configurations it
supports.

Change-Id: Ib7b36468f17fbd65eb3d7d9355fcf78148aeb44a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57123
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:19:53 +00:00
Furquan Shaikh ae20d4c78f mb/google/volteer: Fix USB4 enabling for volteer family
volteer baseboard was currently enabling TBT(USB4) devices in
baseboard devicetree and also selecting the Kconfigs required for
resource allocation above 4G for the USB4 controllers. However, not
all volteer devices have USB4 support. This change fixes USB4 enabling
for volteer family by making the following udpates:
1. TBT devices are moved from baseboard devicetree to individual
override trees for the variants that actually support USB4.
2. When moving TBT devices to override tree, tbt_pcie_rp0 is marked as
on instead of hidden for all variants other than volteer
reference. This is because volteer reference is the only device that
has an asymmetric support for USB4 (i.e. does not support USB4 on C0
port).
3. Kconfig selection for PCIEXP_HOTPLUG is moved to Kconfig.name for
these variants.

Change-Id: If380dcb1ea1633b3a1d6932e769cb6ed0a2761c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57112
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:19:42 +00:00
Sugnan Prabhu S 9c348a7b7e soc/intel/alderlake: Fix processor hang while plug unplug of TBT device
Processor hang is observed while hot plug unplug of TBT device. BIOS
should execute TBT PCIe RP RTD3 flow based on the value of
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.

BUG=b:194880254

Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 16:46:27 +00:00
Wisley Chen 7517c39c9e mb/google/brya/var/redrix: adjust uid for Maxim amp
DEV0 - 0x3a   i2c-MX98390:00:  Right Speaker
DEV1 - 0x3b   i2c-MX98390:01:  Left Speaker
DEV2 - 0x38   i2c-MX98390:02:  Right Tweeter
DEV2 - 0x39   i2c-MX98390:03:  Left Tweeter

This is to consist with other 2 speakers configs, and m/c driver design.
uid0/1 = regular speakers.
uid2/3 = tweeter

BUG=191931762
TEST=FW_NAME=redrix emerge-brya coreboot

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01 16:45:54 +00:00
Johnny Lin 15fc6cf3c6 Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.h
It would be easier for people to find the defined variables.

Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-09-01 15:22:05 +00:00
Arthur Heymans de374e5028 drivers/intel/fsp1_1/romstage.c: Remove MCU update
On Braswell this is done in the bootblock before C code is executed.

Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-09-01 00:53:20 +00:00
Martin Roth 7266c5ec84 soc/amd/common: Change default spi speeds to 33MHz
In CB:56884 we discussed changing the default fast_read speed from
66MHz, which some platforms may not be capable of running, to 33MHz,
which should be generally suitable for all platforms.  This same
change has been applied to the default for all SPI speeds.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 00:52:20 +00:00
Ricardo Quesada ff236ef832 cbfstool: add buffer_end() to common.h
Add buffer_end() function to common.h. This function returns a
pointer to the end of the buffer (exclusive).

This is needed by elogtool util. (See the next CL in the chain).

BUG=b:172210863

Change-Id: I380eecbc89c13f5fe5ab4c31d7a4fef97690a791
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-31 21:18:18 +00:00
Arthur Heymans 83eb22e3b1 arch/x86: Implement cpu_info in C code
Change-Id: Ic7396b8429e29739e18a189dacea3a76e571cd58
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57049
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:58:58 +00:00
Ian Feng c33dbc3a40 mb/google/dedede/var/cret: Modify Wifi SAR condition
Using tablet mode of fw config to decide to load custom wifi sar or not.

BUG=b:194163604
TEST=build and test on cret and cret360

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ie94c2a07ad43fe1cb426e543dd97ed0434c42f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-31 15:56:22 +00:00
Felix Held 50528281fb soc/amd/*/include/soc/gpio: remove GPIO_2_EVENT
commit de7262f82c (soc/amd: remove special
GPIO_2 override soc_gpio_hook) removed the workaround that needed those
definitions, so remove the now unused GPIO_2_EVENT definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:27:03 +00:00
Angel Pons be2e2bbba5 smbios.c: Move function definition near call-site
The `smbios_get_device_type_from_dev()` function is only called once
from the `smbios_walk_device_tree_type41()` function. Put the former
function's definition above the latter function's, instead of having
them a thousand lines apart.

Change-Id: Idc6175324ca8a14841eaf7d6904712efb75f2d26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57205
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:15:58 +00:00
Mark Hsieh e8982d1be8 mb/google/brya/var/gimble: Include SPD for K4UBE3D4AA-MGCR
Add SPD support to gimble for LPDDR4 memory part K4UBE3D4AA-MGCR.

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ida21fd50129412af59a341dea45232fd0f9931ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57253
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:14:08 +00:00
Angel Pons ab11f46219 mb/razer/blade_stealth_kbl: Disable UART #0 in devicetree
FSP-S disables UART #0 as per the `SerialIoDevMode` settings.

Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mimoja <coreboot@mimoja.de>
2021-08-31 15:13:29 +00:00
Angel Pons bbfb18c410 mb/google/caroline: Enable I2C #2 in devicetree
Commit 98ec53bdf1 (mb/google/caroline:
Re-enable I2C2 / fix digitizer) enabled I2C #2 in the `SerialIoDevMode`
array, but left the device disabled in the devicetree. Enable it.

Change-Id: I67eec1c753bfd2a78ed0c1e0a78057cd4a3d4153
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-31 15:12:58 +00:00
Angel Pons 085649440b mb/google/poppy: Do not let FSP-S init UART 0
FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy
boards only enable UART 0 because it's function 0 of PCI device 30, and
the PCI specification requires that function 0 of multifunction devices
be implemented if other functions are implemented as well.

Nautilus got remedied in commit 8a1f095e50
(mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by
using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the
SerialIO device. This way, it remains enabled and the GPIO settings will
not be overwritten by FSP.

However, not all variants do this, but use some UART 0 pads as GPIOs. To
prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the
variants.

Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:12:45 +00:00
Zheng Bao 481661e313 amdfwtool: Add flag for multi FW level to the struct amd_cb_config
This change can make the code be more flexible. And later we will use
amd_cb_config to transfer parameters.

Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:06:03 +00:00
Zheng Bao dac446165e amdfwtool: Copy string in a safer way
The issue is reported by Coverity. Using strcpy or strcat copying
string without checking length may cause overflow.

BUG=b:188769921

Reported-by: Coverity (CID:1438964)
Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:05:48 +00:00
Felix Held fd2982ec8a soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz
Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.

TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30 19:46:17 +00:00
Martin Roth ce5813fdc5 mb/(amd,google): Remove spi configuration from devicetree
Now that the SPI configuration has been moved into Kconfig, it is no
longer needed in devicetree.

BUG=b:194919326
TEST=Build & boot guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30 18:54:40 +00:00
Martin Roth fd078d85d0 soc/amd: Show SPI settings in bootblock
BUG=b:194919326
TEST=See SPI settings in bootblock

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30 18:54:16 +00:00
Martin Roth e582e710b8 soc/amd/common: Show current SPI speeds and modes
This patch adds code to print the current SPI speeds for each of the 4
different speeds, Normal, Fast-read, Alt-mode, & TPM.  It also displays
the SPI mode and whether or not SPI100 mode is enabled.

BUG=b:194919326
TEST: Display the speed, change speeds, show that new speeds are the
expected values.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30 18:53:56 +00:00
Karthikeyan Ramasubramanian 0032bfa5c5 soc/amd/cezanne/early_fch: Perform early SPI initialization
Add the fch_spi_early_init call in fch_pre_init to perform early SPI
initialization which enables SPI ROM and setting the speed & read modes.

BUG=b:194919326
TEST=Build and boot to OS in Guybrush.

Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30 18:53:34 +00:00
Martin Roth b5b1c5a7da soc/amd/common: Update SPI based on Kconfig & EFS instead of devtree
Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.

BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-30 18:34:48 +00:00
Felix Held f363ad4acf soc/amd/common: move GPIO register state save struct to gpio_banks.h
The common_i2c_save struct isn't specific to the I2C code and since it
contains the state of the GPIO control & status register and the state
of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and
rename it to soc_amd_gpio_register_save.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-30 16:30:45 +00:00
Felix Held db3337d929 soc/amd/common/fsp/Makefile: drop strip_quotes call in FSP-M size check
No need to strip the quotes of the FSP-M file path in the size check and
it's always a good idea to not remove the quotes around file paths that
will get passed as parameters to shell programs so that spaces in the
path can't cause malfunction.

TEST=All cases still behave as expected for Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-30 13:44:36 +00:00
Cliff Huang 73ed5991bc mb/intel/adlrvp_m: Fix to Enable PCIe x1 Slot
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0

TEST = show device command:
    $ lspci -s 00:19.0
    expect this:
    00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30 12:20:28 +00:00
Eric Lai ced18c6777 mb/google/brya/var/felwinter: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30 04:34:15 +00:00
Eric Lai d94c935910 mb/google/brya/var/felwinter: Update device tree
Based on latest shcematic to update the device tree.

BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30 04:25:46 +00:00
Deepti Deshatty e5221a26d9 mb/google/brya: Enable TCSS
Enable flag SOC_INTEL_COMMON_BLOCK_TCSS.

BUG=b:187385592
TEST=type-C pendrive/Gen-2 SSD detected as Super speed.

Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54090
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30 04:25:09 +00:00
Frank Wu 91472fe535 mb/google/dedede/var/driblee: Configure thermal sensor setting
According to schematics, TSR2 thermal sensor is not present in driblee.

BUG=b:191732473, b:197180925, b:195868075
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30 04:09:11 +00:00
Frank Wu f04a912818 mb/google/dedede/var/driblee: Configure audio setting
Update the combination audio CS42L42 and amp. MAX98360.

BUG=b:195619349, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-30 04:08:38 +00:00
Felix Held 79f28249cd soc/amd/cezanne/chip: add functionality to power down eMMC interface
Power down the eMMC controller via the AOAC interface when it's not
enabled in the devicetree.

BUG=b:184978118
TEST=On guybrush the unused eMMC controller is disabled in AOAC after
applying this patch. Before this patch it was enabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-08-29 20:58:51 +00:00
Bill XIE a11eca149a superio/nuvoton/nct6776: Correct the definition of NCT6776_GPIOBASE
NCT6776's data sheet does say that the virtual LDN of GPIO base should
be 0x308, and most mainboards using it usually correctly config it in
devicetree.cb under the path 2e.308, but in nct6776.h it used to be
defined as 8 from the beginning (an ancient commit 1e3a22649a, lately
revived in commit f95daa510d), identical to the LDN of WDT, which
eliminates the definition of value 2e.308, and makes related resource
allocations unable to take effect. (in log we can find "PNP: 002e.308
missing read_resources" if 2e.308 is enabled and assigned with
resources)

In this commit, NCT6776_GPIOBASE is set to a value consistent with the
data sheet.

With this commit, resources under 2e.308 of NCT6776 can be allocated
successfully.

Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-29 16:41:12 +00:00
Mariusz Szafrański f3c84024b1 mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cb
This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db
soc/intel/denverton_ns: Ensure CPU device has a valid link

Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-28 21:27:46 +00:00
Felix Held f8df08213d soc/amd/common/fsp/Makefile: check if CONFIG_FSP_M_FILE is defined
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size
call evaluates to an empty string, so the file-size call will run
"cat | wc -c" which will cause make to get stuck in there. Also print a
message when no FSP-M file is specified that the resulting image won't
boot successfully.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-28 18:47:05 +00:00
Felix Singer 30bfcaba39 mb/google/{dedede,hatch}: Remove unneeded documentation
This documentation doesn't add any more value. Thus, remove it.

Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28 18:21:57 +00:00
Felix Singer 0dcdb217cf soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.

If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.

Also, add a release note for the upcoming 4.15 release.

Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28 18:21:26 +00:00
Casper Chang 621ae7c701 mb/google/brya/variants/primus: update USB 2.0 controller Lane Parameter
Modify USB 2.0 port5 parameter to improve SI diagram measurement.

BUG=b:187992881
TEST= Pass USB 2.0 SI Eye diagram measurement.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1eff05a7ad6563898744c24f9657e28625319873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28 17:44:51 +00:00
Wisley Chen 0d753e5108 mb/google/dedede/var/drawcia: Add fw_config probe for ALC5682-VD/ALC5682-VS
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:194356991
TEST=ALC5682-VD/ALC5682-VS audio codec can work

Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28 17:44:34 +00:00
stanley.wu b4481e0bd4 mb/google/dedede/var/boten: Generate SPD ID for supported part
Add supported memory part in the mem_parts_used.txt and generate the
SPD ID for the part. The memory part being added is:
MT53E512M32D1NP-046 WT:B

BUG=b:194223174
BRANCH=dedede
TEST=Build the boten board.

Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28 17:44:15 +00:00
Wisley Chen 54598a6ba5 mb/google/brya/var/anahera: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

MT53E1G32D2NP-046 WT:A
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
MT53E512M32D2NP-046 WT:E
H9HCNNNCPMMLXR-NEE
K4UBE3D4AA-MGCR
H9HCNNNFAMMLXR-NEE
MT53E2G32D4NQ-046 WT:A
MT53E512M32D1NP-046 WT:B
MT53E1G32D2NP-046 WT:B

BUG=b:197850509
TEST=build pass

Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28 17:44:03 +00:00
Frank Wu 1693f6e09a mb/google/dedede/var/driblee: Configure I2C ports and touchpad
Update the I2C ports and touchpad based on the schematic.

BUG=b:195622489, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 17:43:27 +00:00