Since there are two cameras on Nami and only one camera on Vayne.
We need to disable rear camera on all Vayne sku.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera shown on Vayne
Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets the wake for EC to proper gpios.
BUG=77605178
TEST=Test that lidopen wakes up the system from S3.
Change-Id: Icbf30007403191005396027e74b9b6fb7319e006
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25539
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with
kernel 4.9. This code is based on the output of autoport.
Working:
- S3 suspend/resume
- USB
- Gigabit Ethernet
- integrated graphics
- PCIe
- SATA
- eSATA
- PS/2 port (only a mouse has been tested)
- hardware monitor
- onboard audio
- front panel audio
- native raminit (2 x 4GB + 2 x 8GB, DDR3-1333)
- native graphics init with libgfxinit
- EHCI debug. The debug port is the port closest to the HDMI port.
- flashrom, using the internal programmer. Tested with coreboot,
untested with the vendor firmware.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for graphics init
- PCIe graphics
- S/PDIF audio
Not working:
- "clear CMOS" button
The CPUTIN sensor on the Super I/O is not connected. The PECI agent is
likely connected instead to give CPU temperature readings. However,
there does not appear to be enough information in the publicly available
datasheets to fully set up the PECI agent. As a result, there is
currently no accurate, automatic fan control via the Super I/O.
Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/24971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP 2.0 needs to set the ac_loadline and dc_loadline for
each VR config. Without it, the Loadline is considered to be
0 mOhm and this causes CPU temp to jump all over the place
whenever the CPU is used.
This is necessary since there are no VR_CONFIG icc mappings for
Skylake SKUs, only KabyLake.
These values were copied from the Google Poppy devicetree.
Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Set the Thermal Control Circuit (TCC) activaction value to 95C
even though FSP integration guide says to set it to 100C for SKL-U
(offset at 0), because when the TCC activates at 100C, the CPU
will have already shut itself down from overheating protection.
This was tested on Purism Librem 13 v2. A bisect showed that the
immediate shutdowns happened after commit [1] was merged which led
to this solution.
[1] ec5a947b (soc/intel/skylake: make tcc_offset take effect)
Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Although VmxEnable is currently ignored by FSP, a forthcoming patch
explicitly enables it in coreboot, so set it in anticipation of that.
Enable Intel SpeedStep to ensure the ACPI tables are generated for
the C-states/P-states which are required for the xen-acpi-processor
module to be loaded. Without it, the Qubes 4.0-rc4 installer will
complain at boot about modules that could not be loaded.
Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the GPIO to match the TPM-enabled motherboards, and add TPM
support in devicetree and enable the config.
After changing the GPIO table, the librem 13v2 and librem 15v3 now
have the same GPIOs, so use a single gpio.h file instead of one
file per variant.
Change-Id: I425654c1c972118aa81c27961246238c2eef782d
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/23683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6).
BUG=b:77290144
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace
Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.
BUG=b:72875858
TEST=Build Gardenia.
Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The WP signal to the AP isn't inverted as it is on other platforms, so
it was reporting incorrectly. Change the ACPI table to be active low,
and invert the signal when reporting it to everything else.
BUG=b:74946358
TEST=Boot grunt with battery inserted, WP signals both report 1. Remove
battery, WP_CUR reports 0, WP_BOOT still reports 1.
Change-Id: Ic1369dbda609e34b308af308880449643be6af39
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets PL1 value to ~6W. Here, 8W setting gives
a run-time 6W actual measured power.
Also, this patch sets PL2 value to 15W.
BUG=None
BRANCH=None
TEST=Build and read the MSR 0x610.
Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/25341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch selects `HAVE_APCI_RESUME` to enable S3 resume. This
has a dependency on EC to store the hash.
BUG=b:72472969
TEST=suspend and resume from S3 should work.
Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25390
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new variant of Poppy for the Atlas board.
BUG=b:75454415
TEST=tested on a P0 board. System boots and is mostly
functional, though some peripherals are not ready so there
are no touchpad/touchscreen devices configured yet.
Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change updates devicetree and GPIO configurations to match the
schematics:
1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and
deemphasis_enable for [2] need to be set instead of [0].
2. WLAN power enable, wifi disable and PERST# GPIOs need to be
configured correctly.
BUG=b:76180142
TEST=Verified that wlan0 scan works.
Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the sandybridge both smm setup and smihandler code to a
common place.
Tested on Thinkpad X220, still boots, resume to and from S3 is fine
so smihandler is still working fine.
Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This enables ThunderPeak WiFi card on M.2.
TEST=Verify wlan card shows up in lspci
Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/24931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch disables debug consent in the devicetree. When debug
consent is set to DBC by default, it prevents some clocks from turning
off during S0ix. This blocks S0ix entry.
This patch also enables S0ix from the devicetree.
BUG=b:76163091
TEST=enter S0ix and check if slp_s0 is asserted
Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25312
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8).
BUG=b:76086834
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25379
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an SPD for this particular Hynix memory type to the poppy board
so it can be used by poppy variants.
BUG=b:75454415
Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Current emmc tuning parameters for octopus were copied over from other
boards and result in failure to boot from emmc. This change gets rid
of the emmc tuning parameters in devicetree. Once emmc tuning tests
are run for octopus, these parameters can be added back.
BUG=b:75986903
BRANCH=None
TEST=Verified that octopus boots from eMMC without any errors in
depthcharge.
Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC needs to set the PPCM value depending on whether
Turbo is enabled or not, and the values differ between
Broadwell (0, 1) and Skylake (1, 2) platforms.
Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The LPC I/O ports for EC communication were not set properly,
causing ectool to fail to read the Index I/O from the EC.
The EC Index I/O is on port 0x380 and the LPC I/O port needs to be
decoded by the PCI device for it to be accessible.
Correct the value for the Librem 13v1, 13v2 and 15v3.
Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change remove work-around code for the power issue of MIPI and
USB cameras on previous board revision. With the work-around code,
PMOF ACPI method cannot turn off MIPI camera. So we need to remove
it.
BUG=b:74214248
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7becaf61de364f82976ec0be7f8c9e4ef1a7aedd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/25337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The code is based on autoport and that for revolve_810g1
Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Onboard USB2 interfaces (wlan slot, wwan slot, camera, smart card)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.17-1 within Debian GNU/Linux testing, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
Not working well:
- EHCI debug on port SSP2,(The USB port on the left, wired to ehci
before OS) it has always-on enabled by default (maybe via EC),
which disturbs FT232H's own power up, requiring a very critical
timing to plug it in for it to work.
Change-Id: I52e549ec18e8aa661a506a16dbc7f83417c0da78
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/25218
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=build
Change-Id: I32d185741ce20a3a82e6895de3026ade52d0bcc8
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h
TEST = Build for octopus.
Change-Id: I2239aa70cb708e6e1c06339ca9d517e7eaa198ed
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25310
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h
TEST = Built and booted glkrvp, verified warm and cold
reboot and suspend resume.
Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds a new Kconfig option for mainboard octopus "HAS_TPM"
that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA
is not selected.
BUG=b:76203913
TEST=Compiles fine with mocktpm.
Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always report that EC is in RO mode. This is a temporary workaround
for a hardware issue that is causing EC to appear to be in RW mode
when it is not. This change will be reverted once transition is made
to newer hardware.
BUG=b:74215817
BRANCH=master
TEST=Verify meowth can boot to recovery's insert screen.
Change-Id: Ib3705bba0bb1f351da79e599566fbffab94428f3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory
SPD data for channel0 and channel1. Set the UserBd UPD to
BOARD_TYPE_DESKTOP for kblrvp8.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
Reviewed-on: https://review.coreboot.org/25194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase
it was idle.
Google CFM add-in card is going to use this I2C bus so it needs to be
re-enabled.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is
working properly.
Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/25258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This creates a bip variant for octopus. Nothing is set in the variant
files here-- everything is picked up from baseboard.
BUG=b:75976864
TEST=None
Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to
read the sku id. In order to support "-1", we need to use
uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type.
Otherwise, tools/scripts will read 65535 instead of -1.
Another reason to change this is that sku_id can be
supported by ec up to 4 bytes.
BUG=b:73792190
TEST=mosys output "Platform not supported" for -1 sku id
arc-setup read -1 sku id
Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
