due to overridetree.cb set disable_xhci_lfps_pm = 0,
need correct condition expression to let function work.
BUG=b:155955302
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ia047c75611a35aafd15f2481bf64049e13d4a2ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42860
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, for Stoneyridge and Picasso mainboards, pads that are
configured for SCI/SMI/WAKE need to have multiple entries in the
configuration table - one for PAD_GPI and other for the special
configuration that is required. This requires a very specific ordering
of pads within the table and is prone to errors because of conflicting
params provided to the different entries for the same pad. This also
does not work very well with the concept of override GPIOs where the
entry in base table is overridden with the first matched entry from
the override table.
This change updates the way GPIO configuration is handled for special
routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of
soc_amd_gpio structure in the macros performing these
configurations. Also, program_gpios() is updated to perform a write to
GPIO control register instead of read-modify-write. This is because
mainboard is expected to provide only a single configuration entry for
each pad within a given table. Thus, there is no need to preserve
earlier configuration.
Mainboards that were providing multiple entries for a single pad are
updated accordingly.
BUG=b:159944426
Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
H1 is not a wake source and hence there is no need to configure SCI
GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9
i.e. H1_PCH_INT_ODL.
BUG=b:159944426
Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value
Change-Id: I6438547e09a3ff3a1c01addfcc01383e89f5b435
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use defines found in <cpu/x86/smm.h>.
Change-Id: Ib75df13021120fb2c056782c252e97d6b036c7da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.
Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Due to faffy has PL-2303 connect to USB2 port6(count from port0),
needs to enable it.
BUG=b:159760559
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort
connectivity. While Dali can either be fused-down PCO or RV2 silicon,
Pollock is always RV2 silicon.
Since we have all boards using this code in tree right now,
soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku().
Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 1408798637.
Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause.
BUG=b:159370566
BRANCH=None
TEST=boot up device and make sure when kernel is booted, backlight comes up.
Change-Id: I643854c6c805d262539bbb482808e8c322059a49
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which
it doesn't.
Change-Id: Ib5839a42f5133f5f84e1e1e4e587801b916ca571
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently, Reset Power Cycle Duration is set with default value (4s).
This adds around ~5 seconds of delay during power cycle or global reset.
So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s
to minimize the delay.
Delay with Power Cycle or Global Reset:
Existing behaviour:
S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch:
S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert.
The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width
to 98ms not 2s.
Test=Verified on Hatch and Puff boards
BUG=b:158634281
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
BUG=b:159615125
TEST=Build and boot volteer. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I68eb51c6a0af77982c060767993265764a2bc926
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
due to overridetree.cb set disable_xhci_lfps_pm = 0,
need correct condition expression to let function work.
BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I53621d7674a531adfa40e8703cb2cd01c50376b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42564
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.
A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change replaces variant_wifi_romstage_gpio_table() with
variant_pcie_power_reset_configure() to handle the reset and power
sequencing for WiFi devices pre- and post- v3 version of schematics.
These are the requirements that need to be satisfied:
1. As per PCI Express M.2 Specification Revision 3.0,
Version 1.2, Section 3.1.4 "Power-up Timing", PERST# should stay
disabled until `TPVPGL` time duration after device power has
stabilized. Value of TPVPGL is implementation specific.
2. For Intel WiFi chip, it is known to get into a bad state if the
above requirement is violated and hence requires a power cycle.
3. On pre-v3 schematics:
- For both dalboz and trembyle references, GPIO42 drives
WIFI_AUX_RESET_L which is pulled up to PP3300_WIFI.
- For both dalboz and trembyle references, PP3300_WIFI is controlled
using GPIO29. This pad gets pulled high by default on PWRGOOD
because of internal pull-up. But, at RESET# it is known to have a
glitch. When GPIO29 gets pulled high, it causes WIFI_AUX_RESET_L to
be pulled high as well. This violates the PCIe power sequencing
requirements. Hence, for pre-v3 schematics on both dalboz and
trembyle, following sequence needs to be followed:
a. Assert WIFI_AUX_RESET_L.
b. Disable power to WiFi.
c. Wait 10ms to allow WiFi power to go low.
d. Enable power to WiFi.
e. Wait 50ms as per PCIe specification.
f. Deassert WIFI_AUX_RESET_L.
4. On v3 schematics:
- For trembyle: WIFI_AUX_RESET_L is driven by GPIO86 which has an
internal PU as well as an external PU to PP3300_WIFI.
- For dalboz: WIFI_AUX_RESET is driven by GPIO29. This is active
high and has an internal PU. It also has an external 1K PD to
overcome internal PU.
- For both dalboz and trembyle references, PP3300_WIFI is
controlled by GPIO42 which has an internal PU and external
PD. Trembyle schematics have a comment saying strong PD of 2.2K but
the stuffed resistor is a weak one (499K). ON dalboz, it uses a
weak PD (which doesn't look correct and instead should be a strong
PD just like trembyle). Having a strong PD ensures that the WiFi
power is kept disabled when coming out of G3 until coreboot
configures GPIO42 as high.
- Thus, for v3 schematics, following sequence needs to be followed:
a. Assert WIFI_AUX_RESET{_L} signal.
b. Enable power to WiFi.
c. Wait 50ms as per PCIe specification.
d. Deassert WIFI_AUX_RESET{_L} signal.
BUG=b:157686402, b:158257076
TEST=Verified that QCA and AX200 cards both continue working. Tested
QCA on Dalboz and Trembyle. Tested AX200 on morphius.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532131ee911d5efb5130d8710f3e01578f6c9627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42738
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the baseboard GPIO table in ramstage to match
v3 version of dalboz reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Auto-Submit: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the baseboard GPIO table in ramstage to match v3
version of trembyle reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates variant_romstage_gpio_table() and
variant_wifi_romstage_gpio_table() to support v3 version of schematics
for dalboz and trembyle reference designs. gpio_set_stage_rom and
gpio_set_wifi are divided into two groups:
a) Pre-v3 (GPIO table for pre v3 schematics):
* gpio_set_stage_rom_pre_v3
* gpio_set_wifi_pre_v3
b) v3 (GPIO table for v3+ schematics):
* gpio_set_stage_v3
* gpio_set_wifi_v3
Currently, both _v3 is a copy of _pre_v3, but will be updated in
follow-up CLs to make it easier to identify what changed from _pre_v3
to _v3.
BUG=b:157088093, b:154676993, b:157098434, b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I444875d93100c2f2abdb6dec4312861fd89d9b78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251390
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RAM_ID GPIOs are configured by ABL based on the information added to
APCB. coreboot does not need to configure these pads. This change
drops the RAM_ID configuration from trembyle baseboard. Dalboz never
really configured RAM_IDs in coreboot.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the GPIOs that need to be configured for early
access in coreboot to early_gpio_table[] in
gpio_baseboard_common.c. These GPIOs include:
* Pads to talk to EC
* Pads to talk to TPM
* Pads to talk to serial console
These should be configured in the first stage that runs coreboot
i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as
part of verstage (which starts on PSP), else it should be done as part
of bootblock (which is the first stage that runs on x86).
This change drops GPIO_137 from early_gpio_table since that is not
really required in early stages.
BUG=b:154351731
TEST=Verified that trembyle still boots.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add UPD xhci0_force_gen1 for Trembyle and Ezkinil.
The default setting is set to disable, and set enabled for Ezkinil.
Trambyle -> set default as disable.
Ezkinil -> set enable by request.
BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle.
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1) Based on malefor schematics, disable unused I2C port, USB port, TBT
PCIe
2) Add audio device to the tree
BUG=b:150653745, b:154973095
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the devices' function worked properly.
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the volteer2 variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
Modified to alphabetize and update to duplicate latest volteer changes
currently in the review and merge pipeline.
Added the following missing files from the variants/volteer2/ folder:
- gpio.c
- include/variant/acpi/dptf.asl
- acpi/mipi_camera.asl
- Makefile.inc
- memory/dram_id.generated.txt
- memory/Makefile.inc
- memory/mem_list_variant.txt
- overridetree.cb
BUG=b:159135047
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLTEER2
Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the delbin variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158797761
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_DELBIN
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create the wyvern variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158269582
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_WYVERN
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the faffy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
V.2: Manually modified to keep Kconfig sorted.
BUG=b:157448038
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_FAFFY
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.
BUG=b:149714955
TEST=lid/base touch screen works correctly
Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Here we consolidate some of the mainboard.c duplication between
Puff and it's variants.
Customizations can be done later via introducing a devicetree
parameterisation.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove an unneccessary comment and group the variant_early_gpio_table
together based on GPIO group.
Changed static variable name gpio_table to override_gpio_table to be
more descriptive.
BUG=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer to kernel.
Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the following volteer-specific devices from baseboard's
devicetree.cb into volteer's overridetree.cb file:
- Goodix Touchscreen
- ELAN Touchscreen
- ELAN Touchpad
- SAR0 Proximity Sensor
Adjust the other variant's overridetree.cb files to correspond to
the changes made to the baseboard's devicetree.cb in this change.
BUG=b:159241303, b:154646959
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer to kernel and verify that the trackpad works.
Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update fw_config definition in devicetree.cb to match current
definition for volteer.
BUG=b:159157584
TEST=none
Change-Id: I761893818231880d86fd13cfa61319157d06a7d5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42331
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pass through mode (SW CM) RTD3 is not supported until QS platform.
D3Cold is needed to be disabled along with upstream TBT firmware
signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix.
This temporary patch will need to be reverted once PM RTD3 support is
validated on QS platform.
BUG=b:159050315
TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4)
are available for TGL-U. They are dependent upon the SKU of the CPU
that the mainboard is running on. Volteer is updated here to use these
new limits.
To accomplish this, the SoC chip config's power_limits_config member
was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE
macros. Just before power limits are applied, the correct set of them
is chosen from the array based on System Agent PCI ID. Therefore, a
TGL board should have two sets of power limits available in the
devicetree.
BUG=b:152639350
TEST=On a Volteer SKU4 (4-core), verified the following console output:
CPU PL1 = 15 Watts
CPU PL2 = 60 Watts
CPU PL4 = 105 Watts
Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
