Commit Graph

44512 Commits

Author SHA1 Message Date
Angel Pons 779d0c66df device/azalia_device.h: Guard macro parameters
Add parentheses around macro parameters to avoid operation order issues.

Change-Id: Ic984a82da5eb31fc2921cff3265ac5ea2be098c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-04 00:22:46 +00:00
Guodong Liu 09cbb064fc soc/mediatek/mt8186: Add GPIO drivers
Add GPIO drivers to let other module control GPIOs.

TEST=build pass
BUG=b:202871018

Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 18:57:27 +00:00
Kevin Chiu b8fa1d389a mb/google/trogdor: Mark kingoftown as supporting Parade PS84640
BUG=b:204272905
BRANCH=master
TEST=emerge-trogdor coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03 18:56:29 +00:00
Rex-BC Chen 5db9fa7433 soc/mediatek/mt8186: Initialize watchdog
MT8186 requires writing speical value to mode register to clear
status register. The flow of clear status is different from other
platforms, so we override mtk_wdt_clr_status() for MT8186.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 18:52:23 +00:00
Rex-BC Chen a23d76a8bc soc/mediatek: Add an overridable function for WDT clear status
mtk_wdt_clr_status is different for MT8186 and MT8195,
so we move this function to soc folder.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 18:51:24 +00:00
Felix Held 9559c68b3c soc/amd/cezanne/include/aoac_defs: drop leading newline
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03 18:38:02 +00:00
Felix Held 5807da4729 soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards
Somehow missed renaming those when creating the coreboot support for
Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03 18:37:53 +00:00
Felix Held 28a0a14b5b soc/amd/*/cpu: handle mp_init_with_smm failure
When the mp_init_with_smm call returns a failure, coreboot can't just
continue with the initialization and boot process due to the system
being in a bad state. Ignoring the failure here would just cause the
boot process failing elsewhere where it may not be obvious that the
failed multi-processor initialization step was the root cause of that.
I'm not 100% sure if calling do_cold_reset or calling die_with_post_code
is the better option here. Calling do_cold_reset likely here would
likely result in a boot-failure loop, so I call die_with_post_code here.

BUG=b:193809448

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03 18:37:28 +00:00
Arthur Heymans c435038c55 cpu/amd/mtrr: Remove topmem global variables
The comments are not correct anymore. With AGESA there is no need to
synchronize TOM_MEMx msr's between AP's. It's also not the best place
to do so anyway.

Change-Id: Iecbe1553035680b7c3780338070b852606d74d15
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-03 18:36:15 +00:00
Arthur Heymans b0db82dd24 cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS
Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2021-11-03 18:34:46 +00:00
Arthur Heymans ca87532a07 cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
AGESA sets up MTRRs so these functions are now unused.

Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-03 18:32:49 +00:00
Felix Held 0a36178fa4 soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_count
The line length is no longer limited to 80 characters, so there's no
need for that line break any more.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03 16:55:15 +00:00
Michael Niewöhner 6b93866f5e soc/intel/xeon_sp: disable PM ACPI timer if chosen
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL, CNL, DNV in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.

Disabling is done in `finalize` since FSP makes use of the PMtimer.
Without PM Timer emulation disabling it too early would block.

Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
2021-11-03 09:33:47 +00:00
Bora Guvendik f6f1258673 soc/intel/alderlake: Allow devicetree override to leave some VR settings as default
Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default.

Test=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03 09:33:12 +00:00
Arthur Heymans 7e27202441 cpu/amd: Always fetch CPU addr bits at runtime
All supported AMD CPUs support getting the physical address size from cpuid so
there is no need for a Kconfig default value.

Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-03 09:03:35 +00:00
Raul E Rangel 4c8c8442ab lib/list: Add list_append
This method will add a node to the end of the list.

BUG=b:179699789
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03 08:29:16 +00:00
Rex-BC Chen 74a0629660 mb/google/corsola: Add MediaTek MT8186 reference board
Add mainboard folder and drivers for new reference board 'Corsola'.

TEST=build pass
BUG=b:200134633

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-03 08:26:28 +00:00
Rex-BC Chen 73e6b8e3eb soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
Add new folder and basic drivers for Mediatek SoC 'MT8186'.

Difference of modules including in this patch between MT8186 and existing SoCs:
Timer:
	Similar to MT8195, MT8186 uses v2 timer.
EMI/PLL/SPI:
	Different from existing SoCs.

TEST=boot from SPI-NOR and show uart log on MT8186 EVB
BUG=b:200134633

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 08:26:17 +00:00
Rex-BC Chen f50bf60bff soc/mediatek/mt8195: move timer enum variables to timer_v2.h
Some enum variables of timer v2 are the same between MT8195 and MT8186,
so we move them to common timer_v2.h.

TEST=emerge-cherry coreboot
BUG=b:200134633

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 08:26:07 +00:00
Alan Huang 5826c591bf device/include: Fix potential build error
Add include guard for usbc_mux.h

BUG=none
BRANCH=none
TEST=Build Pass

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03 08:24:15 +00:00
Raul E Rangel 940953e823 tests/Makefile: Remove ./ prefix when running tests
If ran with obj=/absolute path, then tests were failing to execute
because the recipe tried running `.//absolutepath/...run`.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c3638b1af7531dbe8e956dcbe168250a235ead4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-11-03 08:22:12 +00:00
Werner Zeh e4b2d7da4f mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.

In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.

Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 08:22:05 +00:00
Flora Fu 5cd1871929 soc/mediatek/mt8195: add apusys init flow
Set up APU mbox's functional configuration registers.

BUG=b:203145462
BRANCH=cherry
TEST=boot cherry correctly

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 03:31:03 +00:00
Jeremy Soller b44202b29a mb/system76/oryp8: Add System76 Oryx Pro 8
https://tech-docs.system76.com/models/oryp8/README.html

Tested with TianoCore (UeifPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack*
- S3 suspend/resume
- Booting to Pop!_OS Linux 21.10 and Windows 10 20H2
- Flashing with flashrom

Not working:

- Discrete/Hybrid graphics

Not tested:

- Thunderbolt functionality
- S/PDIF output

Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 20:48:37 +00:00
Jeremy Soller fdaccd875d mb/system76/bonw14: Add System76 Bonobo Workstation 14
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 20:48:29 +00:00
Jeremy Soller f74e42a542 mb/system76/kbl-u: Add Galago Pro 2 as a variant
Change-Id: Ia277b3ad50c9f821ab3e1dcb8327314ba955fa79
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 20:31:12 +00:00
Jeremy Soller be43b13543 mb/system76/kbl-u: Add Galago Pro 3 as a variant
Change-Id: Ie203883cc9418585da4f9c7acd89e7624234caf1
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 20:30:03 +00:00
Jeremy Soller 9037f0a831 mb/system76/kbl-u: Add System76 Galago Pro 3 Rev B
Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:23:15 +00:00
Tim Crawford e747bdda1b mb/system76/gaze15: Add Gazelle 14 as a variant
Change-Id: Ib455951d1d26ddfa010d4eb579905235bd1385a9
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:22:26 +00:00
Tim Crawford 0893b871c6 mb/system76/gaze15: Convert to variant setup
Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:22:05 +00:00
Jeremy Soller c840bc4e32 mb/system76/oryp6: Add Oryx Pro 7 as a variant
Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:21:41 +00:00
Tim Crawford c1481e0863 mb/system76/oryp6: Convert to variant setup
The Oryx Pro 6 has the same board layout as the next model in series,
Oryx Pro 7. The primary difference between the two is the dGPU (20
series to 30 series). Convert oryp6 to a variant setup in preparation
for adding the oryp7.

Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:21:27 +00:00
Patrick Georgi 6dad77d64a util/crossgcc/Makefile: Clean up .PHONY definitions
Order functionally:
 * first "all" and build-$tools
 * followed by clean
 * followed by the architecture targets

The order was chosen this way because the architecture targets are
the mostly likely to continue to grow.

While at it, also fix the build_nasm mention (it was build-nasm)
and add build_make.

Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58796
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 17:36:23 +00:00
Arthur Heymans ba15a598b0 soc/intel/denverton_ns: Fetch addr bits at runtime
Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-02 16:03:29 +00:00
David Wu 67d62fdfed Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"
This reverts commit 287cc02c00.

Reason for revert: it will break s0ix.

BUG=b:201266532
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 16:02:54 +00:00
Felix Held 43cf27d3a7 include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine
the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and
PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and
PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in
the code where the defines are used to clarify which ID is used on which
hardware generation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02 15:50:03 +00:00
FrankChu 0d7e2a461a mb/google/volteer: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:171365305
TEST=manual test on Volteer:
Volume Up/Down and Power buttons, Tablet Mode switch

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 08:22:39 +00:00
Anil Kumar 49ebce6777 mb/intel/adlrvp: Configure EC in RW GPIO
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status
trusted (LOW: in RO) or untrusted (HIGH: in RW).

Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 08:22:10 +00:00
Jason Glenesk c47835d599 mb/google/guybrush: Update STT coefficients
Update guybrush STT (Skin Temperature Tracking) configuration settings
to values provided by power team after tuning.

BUG=b:203123658

Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02 08:21:51 +00:00
Tim Crawford dd30f4b112 mb/system76/*: CMOS: Drop power_on_after_fail option
Our boards do not boot if power_on_after_fail=Disable. Drop the option
and use the default of powering on.

Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02 08:20:54 +00:00
Raul E Rangel 55fea11f2f soc/amd/common/block/cpu: Add support for cbfs_cache region
This change adds the cbfs_cache region into the x86 memlayout. The SoC
or mainboard can decide how big the region should be by specifying
CBFS_CACHE_SIZE.

BUG=b:179699789
TEST=Build guybrush and verify cbfs_cache region wasn't added.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-02 08:18:29 +00:00
Kangheui Won fab6e44a95 psp_verstage: convert relative address in EFS2
Addresses in AMD fw table with EFS gen2 are relative addresses, but
PSP doesn't accept relative addresses in update_psp_bios_dir().

Check for EFS gen2 and convert them as needed.

BUG=b:194263115
TEST=build and boot on guybrush and shuboz

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I95813beba7278480e6640599fcf7445923259361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-02 08:17:32 +00:00
xuxinxiong cb3745c407 google/trogdor: Add backlight support for Parade ps8640
Add backlight support in ps8640 through the AUX channel using eDP
DPCD registers.

BUG=b:202966352
BRANCH=trogdor
TEST=verified firmware screen works on homestar rev4

Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-02 08:17:21 +00:00
Varshit B Pandya 73161c644e mb/google/brya: Correct AT24 NVM address size
Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.10 kernel logs the message below:

	at24 i2c-PRP0001:01: Bad "address-width" property: 14

The valid size of the AT24 NVM is 16 bits so modify the value from
0x0E to 0x10.

TEST=Boot brya and check the kernel log and see "Bad address-width"
error message is not shown.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-02 08:16:30 +00:00
Zhuohao Lee fe3189dc91 mb/google/brask: add the mkbp device
In order to let the ec passing the key event like recovery and power key
to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP
device.

BUG=b:204519353, b:204512547
BRANCH=None
TEST=pressed recovery key and power button in the OS and checked the UI
     behavior.

Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 08:15:45 +00:00
Werner Zeh d6798e96fc mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this
mainboard and are not routed either, so remove them from the devicetree
completely. PCIe root port #7 (00:1c.6) is connected and used. Add the
missing settings for L1 substates and latency reporting to disable these
features for this port as well.

Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 08:14:05 +00:00
Werner Zeh fec936659c mb/siemens/mc_ehl1: Clean up devicetree
There are a bunch of devices in the devicetree that are disabled in
FSP-S and not used on this board. Having them around in the devicetree,
even if disabled, is not necessary and leads to a message in the log
(left over static devices...check your devicetree).

This commit cleans up devicetree.cb and removes all unused and disabled
devices.

Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-02 08:13:50 +00:00
Subrata Banik 3306f37fd6 lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
Add DDR5 and LPDDR5 memory type checks while calculating bus width
extension (in bits).

Additionally, update all caller functions of
smbios_bus_width_to_spd_width() to pass `MemoryType` as argument.

Update `test_smbios_bus_width_to_spd_width()` to accommodate
different memory types.

Create new macro to fix incorrect bus width reporting
on platform with DDR5 and LPDDR5 memory.

With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit
primary bus width per Ch showed the Total width as:

Handle 0x000F, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0009
	Error Information Handle: Not Provided
	Total Width: 80 bits
	Data Width: 64 bits
	Size: 16 GB
	...

BUG=b:194659789
Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`.

Change-Id: I79ec64c9d522a34cb44b3f575725571823048380
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02 08:13:25 +00:00
Frank Wu 35bcf5071c mb/google/zork/var/vilboz: Generate new SPD ID for new memory parts
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Hynix H5ANAG6NCJR-XNC
2. Micron MT40A512M16TB-062E:R
3. ADATA 4JQA-0622AD

BUG=b:199469240
BRANCH=firmware-zork-13434.B
TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-02 08:12:22 +00:00
Patrick Georgi dba7736104 util/kconfig: Uprev to Linux 5.15's kconfig
Upstream's changes only affect a script that we don't use.
Still, this keeps us in sync with the official version.

Change-Id: I39cbbfb8dc816b4f36f92e6bd53f40c733691242
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 08:10:47 +00:00