Commit Graph

38788 Commits

Author SHA1 Message Date
Tan, Lean Sheng 7d6df608ff soc/intel/elkhartlake: Update SerialIO devices details
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS.
Also update device function number for GSPI #2 in asl file.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If166fefe567a857ca29527d0367197139efbf6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 05:46:21 +00:00
Tan, Lean Sheng d14918f6d0 soc/intel/elkhartlake: Update HECI Control Status Register settings
For EHL, SpiProtectionMode is added to HFSTS register #1.
The original Manufacturing Mode is detected via FpfSocConfigLock
instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode,
and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 05:46:13 +00:00
Tan, Lean Sheng 3cf8a03730 soc/intel/elkhartlake: Update PCI device definition
This change updates PCI device definition according to EHL EDS.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 05:46:04 +00:00
Yongqiang Niu 92fa1d9663 soc/mediatek/mt8192: Add ddp driver
Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46577
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 04:02:52 +00:00
Huijuan Xie b169f294b5 soc/mediatek/mt8192: Enable dsi driver
Enable dsi driver for display.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com>
Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46574
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 03:55:41 +00:00
Yidi Lin a18307951b soc/mediatek/mt8183: Move dsi driver to common/
The mt8183 dsi driver can be shared with mt819x SoC.
Move dsi.c to common/ folder and rename it to dis_v2.c to
differentiate it from mt8173's dsi driver.

TEST=emerge-kukuki coreboot

Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-14 03:55:37 +00:00
Qii Wang cd83bf8874 soc/mediatek/mt8192: add i2c driver support
Add I2C controller for MT8192, and revise the common I2C driver
to support I2C controller running in APDMA async mode. In that
case we have to initiate a different handshake protocol and reset
I2C differently.

BUG=b:155715435
TEST=Asurada boots up to shell

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-14 03:55:13 +00:00
Felix Held 9ef72ca7db mb/google/kahlee: move SMI/SCI GPIO setup to ramstage
SMIs and SCIs aren't used before ramstage or the OS, so there should be
no need to already set them up in romstage. Not using this GPIO
configuration functionality allows untangling the GPIO and smi_util code
and only linking smi_util in ramstage in follow-up patches. In romstage
the pins get initialized as inputs with pull-up, so that at least that
part still matches the configuration before this patch.

BUG=b:175386410

Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-13 22:20:13 +00:00
Felix Held 815efe16cb soc/amd/*/include/spc/gpio: fix pin numbers in comments
Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-13 22:18:50 +00:00
Felix Held 4bbcf60556 soc/amd/common/block/gpio: use all-y in Makefile
Change-Id: Ib77e3d088cc07da4e43a63afb863bb90796f9a37
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-13 22:18:19 +00:00
Felix Held dffdea8a76 soc/amd/cezanne: add caching setup in bootblock
The code can likely be factored out to common code, but since I'm not
entirely sure yet that there will be no differences, I'll copy for now
instead.

Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-13 22:18:03 +00:00
Angel Pons 7584e550cc nb/intel/sandybridge: Clean up program_timings
Clarify the clock, command and control programming sequence.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47770
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-13 00:11:28 +00:00
Kyösti Mälkki e8aa3c7f19 soc/amd/common: Remove SMBus host word accessors
SMBus controller has byte-wide registers. Remove
the word accessors.

Change-Id: If396108308bc8303d84458039b9529ecd83276c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-12 19:49:14 +00:00
Kyösti Mälkki cd8d0e6ce6 soc/amd/common: Refactor ACPIMMIO posted writes
Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12 19:48:49 +00:00
Kyösti Mälkki 6a8c96f169 Revert "src/amd/common: Exclude biosram from psp_verstage"
This reverts commit f38af663d2.

The build error was a spurious ENV_X86 guard in <cbmem.h> that
called for a different clean up.

Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43067
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12 19:48:23 +00:00
Angel Pons 964d91f7d7 nb/intel/sandybridge: Clean up stepping logic
Do not combine the host bridge device ID with the CPU stepping because
it is confusing. Although Sandy/Ivy Bridge processors incorporate both
CPU and northbridge components into the same die, it is best to treat
them separately. Plus, this change enables moving CPU stepping macros
from northbridge code into the CPU scope, which is done in a follow-up.

Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-12 14:34:56 +00:00
Angel Pons 927b1c0161 nb/intel/sandybridge: Fix blunder in MR2 shadow code
Commit 7f1363d9b4 (nb/intel/sandybridge: Program MR2 shadow register)
has a bug where the system locks up and power cycles when booting Linux,
but is still able to pass memtest86+ with flying colors. The issue will
occur when the following conditions are true:

- CPU is Ivy Bridge
- Memory speed is not greater than 1066 MHz (DDR3-2133 or slower)
- System contains dual-rank DIMMs
- The second rank of the dual-rank DIMMs is mirrored
- All DIMMs support Extended Temperature Range
- At least one of the DIMMs does not support Auto Self-Refresh

If all of these conditions are met, the final value of the MR2 Shadow
registers configures the memory controller to issue a MRS command to
update MR2 before entering self-refresh mode, but indicates that rank
mirroring is not required (the first rank on a DIMM is never mirrored).
Before the memory controller enters self-refresh, it sends MRS commands
to all ranks to update MR2, but the missing address and bank mirroring
means DRAM chips on mirrored ranks instead clobber MR1 with junk data.
With garbage in MR1, the mirrored ranks no longer function properly,
which ultimately leads to all hell breaking loose (undefined behavior).

The condition is backwards, since only odd ranks can be mirrored. To
avoid this problem completely, simply remove the condition. The final
register value will still be correct, since the bits are always ORed.

Tested on Asus P8Z77-V LX2, fixes booting Linux with dual-rank DIMMs.

Change-Id: Iceff741eb85fab0ae846e50af0080e5ff405404c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-12 14:22:27 +00:00
Subrata Banik 33cd957866 mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6
2. CLK 6 is using free running CLK
3. Make LAN CLK 7 as unused as GbE is disable

TEST=Able to detect PCIE SD card on 0x1 slot.

Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12 04:03:48 +00:00
Bill XIE f880eb061b drivers/ipmi: Handle the condition when (dev->chip_info == NULL)
Some former commits (e.g. Ieb41771c75aae902191bba5d220796e6c343f8e0)
blindly assume that dev->chip_info is capable to be dereferenced,
making at least compilers complain about potential null pointer
dereference. They might cause crash if truly (dev->chip_info == NULL).

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I1d694b12f6c42961c104fe839d4ee46c0f111197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-12 00:47:48 +00:00
Zheng Bao 5caca947b2 amdfwtool: Register APCB and APCB_BK respectively
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.

Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11 20:04:02 +00:00
Marshall Dawson 13ec029145 util/amdfwtool: Fix EFS generation polarity
The DWORD used to indicate the Embedded Firmware Structure's generation
uses 1 to indicate a first-gen structure, e.g. a SPI device's erased
value of 0xffffffff.  A 0 in bit 0 is how Client PSPs will interpret
the structure as designed for second-gen.

This change and the original addition should have no effects on
any current products as none interpret offset 0x24.

BUG=b:158755102
TEST=inspect EFS in coreboot.rom

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11 19:36:23 +00:00
Jakub Czapiga 5446bdb270 lib/fmap: Add null parameters handling
Prevent null-pointer access when passed as parameter.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie712d040b1c2383dcc8884e5f779c3591ccf0163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-12-11 19:15:25 +00:00
Michael Niewöhner 71f639f123 mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads
There is a whole bunch of pads being configured by the vendor firmware
that are either unconnected due to unpopulated resistor pads, only
connected to test points for vendor debugging purposes or just used as
strap. Configure them as NC with an appropriate pull to disable the
RX/TX functions.

The pads have been determined by dissecting a dead board.

This patch has been tested thoughroughly on a machine, normally used
productive, to see if any issues arise. No problems occurred at all.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I06b942e3182469f87e41914c893e5b485ccca420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11 18:52:38 +00:00
Joe Tessler 0b04d1bf88 hatch: enable genesis PCIe/USB devices
Updates PCIe registers and GPIO CLKREQ lines to match the schematic.

BUG=b:173566597,b:173567124,b:173566890
TEST=build AP firmware; flash device
BRANCH=none

Change-Id: Ibf519b812022839f749e503436f097d3b48c4383
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11 18:04:30 +00:00
Jason Glenesk fe09a6fd47 soc/amd/picasso: Add data fabric read helper function
Add new helper function to support reading a register from the data
fabric.

BUG=b:155307433
TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and
confirm read values match expected values.
BRANCH=Zork

Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 17:47:57 +00:00
Felix Held 44f41537af soc/amd/cezanne: add 0xcf9 reset
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 17:44:42 +00:00
Felix Held e04a18fc25 soc/amd/picasso: move chipset_handle_reset to common
The FSP integration code needs this function to be present. It's not
supposed to be called, but if it is, it'll print an error and call the
SoC's cold reset function.

Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11 17:44:19 +00:00
Tim Wawrzynczak 2f917e6cee mb/google/volteer: Clean up romstage and ramstage UPDs
Move the manual calls to fw_config_probe() into the devicetree; the
AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are
already guarded with probe statements in the baseboard devicetree, so
the code in romstage.c was redundant. The variants seem to have their
USB4 probe statements correct as well, so the manual UPD setting in
mainboard.c was also unnecessary.

BUG=none
TEST=abuild google/volteer

Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11 16:59:49 +00:00
Tim Wawrzynczak 17689367d5 mb/google/volteer: Make use of fw_config_is_provisioned()
In cases when a volteer device is unprovisioned, the safest thing to do
for GPIOs that will normally be used for audio codec buses is to leave
them disabled (configured as PAD_CFG_NC). This patch adds support for
that.

BUG=none
TEST=add debug print to new if branch; remove fw_config from CBI and
see print on console

Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47972
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 16:59:42 +00:00
Tim Wawrzynczak 473bc8c892 fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisioned
A mainboard might want to configure some things differently when a
device is in an unprovisioned state. In the case when fw_config comes
from the Chromium EC, an unprovisioned device will not have a FW_CONFIG
tag in its CBI. This patch will set the fw_config value to
UNDEFINED_FW_CONFIG in the case of an error retrieving the value, as
well as adding a function, `fw_config_is_provisioned()` to indicate the
provisioning status.

BUG=none
TEST=remove fw_config from chromium EC CBI, add code to mainboard to
print return value of fw_config_is_provisioned() (`0`), add
fw_config back to CBI, run same test and see `1`.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib3046233667e97a5f78961fabacbeb3099b3d442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47956
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 16:59:35 +00:00
Marc Jones 5258f4f93e soc/intel/common/block/acpi: Skip UART debug table if not used
Skip the ACPI UART debug table if common block UART isn't selected.

Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48247
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 15:59:49 +00:00
Marc Jones cf3dcd6d29 Kconfig: Show console debug options if loglevel override is set
Show console debug options that would only be available if console
SPEW was selected when the override loglevel option is selected.

Change-Id: I2fb22562688d6b0bc9235c9ebe5d427dc2a67767
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-11 15:58:24 +00:00
Marc Jones 1403b917ac soc/intel/common/block/lpc: Move southbridge_write_acpi_tables declaration
Move the southbridge_write_acpi_tables declaration from acpi.h to common
lpc_lib.h, as common LPC is always the caller. This removes a duplicate
declaration since all soc/intel devices use common LPC, but not all use
common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c
with the other acpi functions.

Note that this would have the reverse problem if there is ever a non-common
LPC device.

Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 15:57:44 +00:00
Angel Pons 79b2a150c7 sb/intel/x/smbus.c: Factor out common code
Since common smbus.c gets built for romstage as well, create a new file
to hold this common code. Account for ICH7 not having a memory BAR, too.

Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 15:12:47 +00:00
Angel Pons 30ff00650a sb/intel/bd82x6x: Drop invalid SATA registers
Code was copy-pasted from older chips and has no effect on bd82x6x.

Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47099
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 11:30:14 +00:00
Jingle Hsu 32d0549a6b mb/ocp/deltalake: Update GPIO configurations according to schematics
On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH
(C621A) by util/inteltool and generate the header file by util/intelp2m.
The DVT and EVT GPIO configurations are the same.
The initial value of GPP_B20 (POST complete) should be high, otherwise
BIC would get incorrect sensor readings and see events like PCH prochot.

Tested=On OCP Delta Lake DVT, dump GPIO configurations
by Intel ITP and verify the results match with the header file.

Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229
Reviewed-by: Tim Chu <Tim.Chu@quantatw.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 07:35:13 +00:00
Michał Żygowski 7ed4039703 util/cbfstool/fit.c: Add support for adding Boot Guard manifests
Change-Id: I8221590cad16cffea3f8b50dd880a77934b78ea8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-11 07:33:51 +00:00
Angel Pons 520003a558 device/Makefile.inc: Do not require hda_verb.c
A mainboard-level hda_verb.c may not exist for variant setups.

Change-Id: If2c92d9498cba7c084ef4c7065bc4ae83c7da761
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-11 07:33:22 +00:00
Angel Pons a7db40eae5 sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm`
There's no need to compare the vendor ID.

Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45258
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 07:33:06 +00:00
Kyösti Mälkki 254142a11d Drop many cases of .previous directive use
Since most assembly files are no longer concatenated together
but built separately, section changes with .previous at the
end of the files have become spurious.

TEST=BUILD_TIMELESS

Change-Id: I2970eed2b114a53475ba385eec4e97bb7ae7095c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-11 07:32:36 +00:00
Arthur Heymans 70d608fc70 Makefile.inc: Remove the CBNT bootblock flag
At the moment this was only used for aligning the bootblock to 64
bytes. At the moment this automatically done with
CONFIG_C_ENV_BOOTBLOCK_SIZE.

Change-Id: I0c879119e525b512eebe3f4c5ff9b2f426c6b6ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-11 07:32:08 +00:00
Furquan Shaikh 339269d587 Docs/cbfstool: Add details about memory mapped window handling
This change adds details memory mapped window handling in cbfstool
required for x86 platforms. It also captures the details about the
newly added support for multiple decode windows.

BUG=b:171534504

Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-11 01:11:16 +00:00
Kevin Chang 3c0b52fb72 mb/google/volteer/variant/lindar: Correct IOM port configuration
Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip.

BUG=b:173093980
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.

Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11 01:10:55 +00:00
FrankChu 71761a3838 mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs
to be overridden.

port#1
PortUsb20Enable=1
Usb2PhyPetxiset=3
Usb2PhyTxiset=2
Usb2PhyPredeemp=7
Usb2PhyPehalfbit=1

BUG=b:173676539
BRANCH=None
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11 01:10:43 +00:00
Alex Levin ecf06e5e75 mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_table
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset
bluetooth on reset.

BUG=b:171085081
TEST=volteer2 boots; scope shows assertion of the signal

Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a
Signed-off-by: Alex Levin <levinale@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-12-11 01:05:37 +00:00
Felix Held 8485637287 soc/amd/picasso: factor out write_resume_eip to common code
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11 00:44:31 +00:00
Felix Held d3e977112a soc/amd/picasso: move UART console code to common folder
Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11 00:43:51 +00:00
Felix Held 6f8f9c969b soc/amd/picasso: move UART Kconfig options to common folder
The actual UART initialization code will be factored out in follow-up
commits.

Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11 00:43:16 +00:00
Felix Held 0dfaf33a13 soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UART
This allows factoring out the common initialization for the integrated
UARTs.

Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 00:42:32 +00:00
Felix Held e7a0202ed0 soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc
all-y will also add a compilation unit to the verstage on PSP build that
runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't
have verstage on PSP support yet, but since it'll eventually land it
doesn't hurt to already add the comment now.

Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11 00:41:53 +00:00