Commit Graph

38289 Commits

Author SHA1 Message Date
Angel Pons 7f5a97ce98 nb/intel/sandybridge: Rename `read_training` function
Given that it sets the receive enable mode bit in the GDCRTRAININGMOD
register, it's clear that this is about receive enable calibration.

Remove a potentially-outdated comment. Proper documentation will be
written once code refactoring and various improvements are complete.

Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 20:31:45 +00:00
Angel Pons 58b609bf30 nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
Tested on Asus P8H61-M PRO, still boots.

Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 20:30:33 +00:00
Angel Pons 737f111d2c nb/intel/sandybridge: Use bitfield for GDCRCMDPICODING
This register's layout makes no sense, so use bitfields for clarity.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22 20:22:38 +00:00
Angel Pons 8137806326 nb/intel/sandybridge: Move constants out of for-loop
Most per-channel registers are programmed with the same values.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: Ifddff3043b68113058859cef08625b90012ca424
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22 19:55:55 +00:00
Angel Pons 7a61274943 nb/intel/sandybridge: Use bitfields to program MCMAIN timings
Tested on Asus P8H61-M PRO, still boots.

Change-Id: I9a996de5d596cdb541c8b327f119425243724007
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22 19:54:11 +00:00
Angel Pons 593f4ca10b nb/intel/sandybridge: Clean up TC_OTHP writes
ODT stretch is configured for both slots in `dram_odt_stretch`. Also
drop an unjustified OR, which is setting ODT stretch for one slot.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 19:22:15 +00:00
Angel Pons 59996e0377 nb/intel/sandybridge: Use one sequence for write leveling
In order to run a write leveling test, one needs to unset the Qoff bit
in MR1, then run the test, and finally set Qoff again. The current IOSAV
sequence uses two subsequences to perform the test, while the other two
are unused. It is possible to perform the two necessary MR1 updates in
the same sequence, which can potentially improve runtime (not measured).

Since `write_mrreg` is no longer used, it is necessary to handle address
mirroring explicitly. This can be accomplished with the recently-added
`ddr3_mirror_mrreg` function, which is also used in `write_mrreg`.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 19:18:57 +00:00
Kevin Chiu d029a579ba mb/google/zork: update berknip CHTC thermal setting
Update APU CHTC thermal temperature protection point:
Temperature limit(C'): 90

Update system config=2 to meet TDP 15W design.

BUG=b:162377903
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check CHTC temperature by AMD utility

Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-22 17:36:25 +00:00
Felix Held 9065f4f8ed soc/amd: move non-CAR linker scripts to common directory
AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.

TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.

Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-22 17:35:20 +00:00
Angel Pons 53ed3e501f sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs
These two IDs are for Cougar Point and Panther Point, the previous
generation of Platform Controller Hubs. So, drop their device IDs.

Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-22 14:25:30 +00:00
Felix Held ea3417b5eb util/amdfwtool: add missing zero-initialization for local variable
Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21 19:40:33 +00:00
Felix Held ea3402213f soc/amd: factor out vbnv_cmos_failed() into soc/amd/common/vboot
Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47584
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21 19:40:20 +00:00
Subrata Banik 65d9a7ae31 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11
List of changes:
1. FSP-M Header:
- Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx

Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21 13:52:22 +00:00
Yidi Lin aad4651e3e mb/google/asurada: Get RAM code from ADC 3
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Asurada the RAM code can be
read from ADC channel 3.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21 13:36:23 +00:00
Julius Werner 1e37c9ca46 cbfs: Add metadata cache
This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer
that stores the headers of all CBFS files. Similar to the existing FMAP
cache, this cache should reduce the amount of SPI accesses we need to do
every boot: rather than having to re-read all CBFS headers from SPI
flash every time we're looking for a file, we can just walk the same
list in this in-memory copy and finally use it to directly access the
flash at the right position for the file data.

This patch adds the code to support the cache but doesn't enable it on
any platform. The next one will turn it on by default.

Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-21 10:43:53 +00:00
Angel Pons 7d11513ab3 nb/intel/sandybridge: Introduce `disable_refresh_machine` function
The same IOSAV sequence is used in both loops, so there's no need to
reprogram it again in the second loop.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21 02:07:02 +00:00
Julius Werner 8360946c8e intel/socket_441: Increase bootblock size
One mainboard using this socket has less than 20 bytes of space left in
its bootblock, hindering development. Double the bootblock size to solve
the problem.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I620c13eab53c3326a4f4660b63ed1dd0fc81f563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47585
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21 01:53:18 +00:00
Julius Werner d656d08f5e Update vboot submodule to upstream master
Updating from commit id 4c523ed1:
    vboot2: Add support for modexp acceleration

to commit id 9d4053df:
    Revert "Reland: Clean up implicit fall through."

This brings in 32 new commmits. Among the changes are restored support
for older GCC/clang versions that do not support
__attribute__((fallthrough)).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21 00:35:46 +00:00
Kevin Chiu f73580f624 zork: Create gumboz variant
Create the gumboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:173536689
BRANCH=zork
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_GUMBOZ

Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21 00:19:30 +00:00
Kevin Chiu d5ffc75fa0 mb/google/zork: update DRAM table for dirinboz
Add Hynix DDR4 DRAM, index was generated by gen_part_id
H5ANAG6NCJR-XNC

BUG=b:173480390
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21 00:15:21 +00:00
Kevin Chiu 324b1ee09e util: Add new DDR4 H5ANAG6NCJR-XNC for zork boards
Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.

BUG=None
TEST=Compared generated SPD with data sheets and checked in SPD

Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21 00:14:23 +00:00
Kane Chen 9d86866109 mb/google/zork: update telemetry settings for Woomax
Update Woomax to improve the performance.

BUG=b:168073070
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-21 00:07:23 +00:00
Felix Held 07c85ad11c include/device/pci_ids: add PCI IDs for new AMD SoCs
Change-Id: I0caea5627045b7855e2c5f3cb01d4fa21332788b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-21 00:04:29 +00:00
John Su e59f70a4d9 mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10
Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC)
activation.

BUG=b:171531244
TEST=build and verify by thermal team

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 23:08:21 +00:00
Angel Pons 96a06dd464 nb/intel/sandybridge: Rename loop variable
The `discover_edges_real` function actually tests a range of values for
DQS PI and evaluates how the system responds. Rename the loop variable.

Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 22:07:56 +00:00
Martin Roth cdd7d18120 mb/google/zork: Remove 50ms WIFI delay
As a part of trying to get our boot time as low as possible, any delays
in the code should try to be refactored out.  This removes the 50ms
delay in the WIFI sequence by enabling power and putting the wifi module
into reset in bootblock, then bringing it out of reset in ramstage.
This is significantly longer than the 50ms requirement.  The reset GPIO
was already being set high in ramstage, so that code didn't need to be
added.

BUG=b:171513520
TEST=Boot on boards with different module types, WIFI works on both.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20 19:30:48 +00:00
Johnny Lin 5b47d77047 intel/fsp2_0: Add soc_validate_fsp_version for FSP version check
Only need to check this once so check it at romstage where
the console is usually ready. Also define union fsp_revision
to avoid code duplication.

Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-20 18:58:54 +00:00
Wisley Chen 982f64d1b7 mb/google/volteer/var/elemi: Update gpio
1. Config EN_PP3300_SSD (GPP_B2) to gpo
2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11
3. WLAN_PERST_L (GPP_H10) change to GPP_H10

BUG=b:172630765, b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc
Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 16:34:49 +00:00
Wisley Chen e928391f74 mb/google/volteer/var/elemi: enable Genesys Logic GL9763E
Enable Genesys GL9763E as PCI-to-eMMC bridge.

BUG=b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I858c12151df5b6fc19132869317edfa1b090335d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20 16:34:35 +00:00
Paul Menzel bb1ada6d3a mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESA
Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing
the connected network device also to be missing.

This is caused by not configuring the third of the four PCIe General
Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be
exposed as one to four PCIe devices.

So, enable it in AGESA but disable enumeration in coreboot. Otherwise,
the serial console stops working in romstage after

    […]
    PCI: 00:15.1 bridge ctrl <- 0013
    PCI: 00:15.1 cmd <- 06
    PCI: 00:15.2 bridge ctrl <- 0013
    PCI: 00:15.2 cmd <- 07

and the system hangs in the payload (SeaBIOS banner is shown on VGA
attached monitor).

TEST=Serial console and payload works, and Linux 5.10-rc2 configures
     PCIe bridge. Output of `lspci -t`:

    -[0000:00]-+-00.0
               +-00.2
               +-01.0
               +-01.1
               +-10.0
               +-10.1
               +-11.0
               +-12.0
               +-12.2
               +-13.0
               +-13.2
               +-14.0
               +-14.2
               +-14.3
               +-14.4-[01]--
               +-14.5
               +-15.0-[02]--
               +-15.1-[03]----00.0
               +-15.2-[04]----00.0
               +-18.0
               +-18.1
               +-18.2
               +-18.3
               +-18.4
               \-18.5

Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46527
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 16:01:16 +00:00
Maxim Polyakov 33f4ec8217 Makefile.inc: Add CARRIER_DIR to component discovery
The idea is to split the “mainboard” category into “variants” and
“carrierboards”, in the case when we use the COMe module together
with the Carrier Board instead of a single monolithic motherboard.
Previously, the “variants” category defined the type of motherboard,
which has a number of differences from the base one, for example, it
differed in the size or type of memory, and in the configuration of
the interfaces. Thus, there is no need to create a separate directory
in src/mainboard for a board that is similar in configuration to the
base board. But for a COMe module, “variants” contains different
variants of only this module, and the entire Carrier Board configuration
is allocated to a separate category - “carrierboards”, and each of the
variants can be used with one of the many boards in “carrierboards”.

For example, in the case of the Kontron mAL10 COMe module, variant
refers to the COMe-mAL10 or COMe-m4AL10 module type. They differ in the
type of memory (DDR3L or DDR4), and maybe they differ in some chips (see
more in https://www.kontron.com/products). However, all variants contain
the same type of processor/SoC.

The "carrierboards" directory can be able contain both the Kontron's
Evalution carrier boards (such as Eval Carrier2 T10 and COMe
Ref.Carrier-i T10  TNI) and third party vendor backplanes that are
compatible with the COMe modules from “variants”.

Thus, the src/mainboard/<module-name> directory contains the common
configuration code for all variants from src/mainboard/<module-name>/
variants, which can be supplemented/redefined with a configuration from
src/mainboard/<module-name>/carrierboard/<vendor-carrierboard-name>.

This architectural solution will be able to systematize and simplify
understanding of the code structure for COMe modules and will allow
vendors to add/maintain their code in a separate directory.

This work is also the first step towards to union of all carrierboards
into the global category in src/carrierboard on a par with all boards
from src/mainboard.

The patch takes this into account in the build system and adds
CARRIER_DIR component to use the “carrierboards” category, as it has
done for VARIANT_DIR.

TEST = Build ROM image for Kontron mAL10 COMe module together with T10
TNI carrier board (https://review.coreboot.org/c/coreboot/+/39133).

Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 15:37:58 +00:00
Felix Singer 8db0a22677 vc/intel/fsp2/denverton_ns: Remove unused files
The Denverton-NS SoC uses the header files from the FSP git repository.
Therefore, remove these from coreboot source.

Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 15:25:11 +00:00
Angel Pons 5c186c6777 Documentation/releases: Update for 4.13
Fill in some blanks for 4.13, mark it done, add template for 4.14.
Also update the list of vboot supported boards.

Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 12:01:35 +00:00
Felix Singer d959a20114 mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3

WIP:
- Documentation

Not working:
- EC ACPI (e.g. Fn keys, battery and power information)

Boots Arch Linux (Linux 5.8.12) successfully.

Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20 11:57:11 +00:00
Arthur Heymans 3622c0bf10 soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER
The PCH IOAPIC is not PCI discoverable.
Linux checks the BDF set in DMAR against the PCI class if it is a PIC,
which 00:1F.0 for instance isn't.

The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR
3, MINOR 7 if the BUS number is 0.

Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:57 +00:00
Arthur Heymans 3d802535cb soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF
Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.

Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:46 +00:00
Arthur Heymans 6e425e1275 soc/intel/xeon_sp: Use common P2SB functions to generate HPET IOAPIC
Change-Id: I700df8fe5243db46fa8458757b4e5596c4b9f404
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:34 +00:00
Arthur Heymans 054026cdb8 soc/intel/apollolake: use P2SB function to generate DMAR IOAPIC
Change-Id: If088d5bf701310e54b14965145229627f3a50417
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:25 +00:00
Arthur Heymans a1f65bed10 soc/intel/common/block/p2sb: Add ioapic BDF functions
This allows to get/set the IOAPIC bus device function.

Change-Id: Ib5bb409efbcbc5729cf0e996655c7ac3f6a78223
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47534
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:18:12 +00:00
Arthur Heymans 695dd2977b soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.

Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:17:56 +00:00
Arthur Heymans 281868e55f soc/intel/apollolake: use P2SB function to generate DMAR HPET
Change-Id: I68f63c79d04cb2cddb92c9f6385459723f8858bd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47532
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:17:33 +00:00
Arthur Heymans f629f7b78b soc/intel/common/block/p2sb: Add hpet BDF functions
This allows to get/set the HPET bus device function.

Change-Id: I8d72da8bc392aa144d167d31cde30cc71cd1396e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:17:22 +00:00
Arthur Heymans a8798a3179 soc/intel/common/p2sb: Add helper function to determine p2sb state
Change-Id: I1d6f9c18160806e289e98c2fa5d290c61434112f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47530
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:13:31 +00:00
Frans Hendriks 7ba970aa78 drivers/intel/fsp1_1/cache_as_ram.S: Use _car_stack area for stack
Top of Temp RAM is used as bootloader stack, which is the
_car_region_end area. This area is not equal to CAR stack area as
defined in car.ld file.

Use _ecar_stack (end of CAR stack) as starting stack location.

Tested VBOOT, Vendorboot security and no security on Facebook FBG1701.

Change-Id: I16b077f60560de334361b1f0d3758ab1a5cbe895
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47737
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 09:21:45 +00:00
Yidi Lin 2832d11dd1 mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.

TEST=verified with SPM WIP patch.
     SPM PC stays at 0x3f4 after SPM firmware is loaded.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: If6e803da23126419a96ffc0337d35edd0e181871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-20 08:40:58 +00:00
Po Xu f06dd678e6 soc/mediatek/mt8192: Enable MT8192 auxadc driver
Enable reading from auxadc on MediaTek 8192 platform.

Reference datasheet: RH-A-2020-0070, v1.0

Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: Ic4c965fc3571637d882eb297e405a5d9e6f77dd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20 08:40:35 +00:00
Po Xu 3f11803075 soc/mediatek: Move auxadc driver from MT8183 to common
The auxadc (auxiliary analogue-to-digital conversion) is a unit
to identify the plugged peripherals or measure the temperature
or voltages.

The MT8183 auxadc driver can be shared by multiple MediaTek SoCs
so we should move it to the common folder.

Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20 08:40:19 +00:00
Maulik V Vaghela 0fd62f5b79 vc/google/chromeos/sar: Make "SAR not found" log a debug message
coreboot might not store wifi SAR values in VPD and may store it in
CBFS. Logging the message with 'error' severity may interfere
with automated test tool.

Lowering severity to BIOS_DEBUG avoids this issue.

BUG=b:171931401
BRANCH=None
TEST=Severity of message is reduced and we don't see it as an error

Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-20 08:36:26 +00:00
Tim Chu 957a36397a vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:51:03 +00:00
Arthur Heymans 051ee4e3ad soc/intel/xeon_sp: Lock down DMICTL
This is required for CBnT.

Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47449
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:47:05 +00:00