The cmd_response field in the pspv2_mbox struct is the buffer used to
pass data to the PSP and back to the x86 side, so rename it to buffer.
This also aligns the code a bit more with the reference code. Also
rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those
definitions from the common psp_def.h to the specific psp_gen[1,2].c
files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch enforces disabling of the CSE device if CSE stays in
SOFT TEMP DISABLE state. The recommendation is to make CSE function
disable to avoid receiving any CSE commands from the OS layer.
BUG=b:228789015
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for
heci1_disable(), once by caller (from various SoC) and again inside the
callee (heci1_disable) function.
As all callers of heci1_disable() function are doing
DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check
inside the callee can be dropped.
BUG=b:228789015
TEST=Able to build and boot google/redrix with this change. CSE PCI
device is getting function disabled upon selecting
DISABLE_HECI1_AT_PRE_BOOT from SoC config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.
BUG=b:228789015
TEST=Able to build google/redrix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.
Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.
Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The header file <inttypes.h> includes <stdint.h> and defines some
additional PRI* macros. Since elog.h and elog.c do not use any of the
PRI* macro, we should include <stdint.h> directly.
Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The ITE EC used on Nereid can take a long time to update, and especially
too long to erase. There is a 1 second timeout enforced on the EC erase
command, but Nereid's IT81302 will typically take about 5 seconds to
complete erase, and could take as long as 30.
Since this affects any Nissa variant using an ITE EC and it's nice to
make the entire Nissa project consistent, this change disables early
sync for all Nissa boards.
BUG=b:222987250
TEST=EC software sync is no longer attempted (and thus does not fail) on
Nereid.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I55d36479e680c34a8bff65776e7e295e94291342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This patch enables TBT PCIe root port 3.
BUG=b:230464233
TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and
ensure 07.3 is in the list.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Read the EEPROM to detect the DDI type.
BUG=b:225139014
TEST=Boot chausie and correctly detect display card type
Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for the chausie EC. Use EC to configure default board GPIO
settings.
Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Chausie uses the spi1 pads for eSPI
Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To read data from an I2C EEPROM that uses 2 byte offsets or any other
I2C device that uses 2 byte offsets, first the two offset bytes are sent
to the device and then the data bytes are read from it. The main
difference to the existing i2c_read_bytes is that that function will
only send one offset byte to the I2C device.
TEST=Reading the contents of an EEPROM on the AMD Chausie board works
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.
This fixes building when some debug options are enabled.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is plenty of cache available to increase DCACHE_RAM_SIZE to
allow the use of cbfs mcache.
Tested on Gigabyte GA-D510UD, still boots and resumes.
Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()"
significantly reduced the size of the bootblock. This makes the space
saving options, required to make to bootblock fit in the 32K SOC
limit, unnecessary.
TESTED: with configs/config.google_octopus_spi_flash_console the .text
size is 0x29c8 bytes which is still well below the 0x8000 SOC limit.
Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
Additionally, this patch enforces SA lockdown configuration for SKL
and ICL as well.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit 211be9c03 (soc/intel/cmn/{block, pch}: Migrate GPMR driver)
drops `dmi` prefix from `lockdown_cfg` function name.
This patch adds the `gpmr` prefix to the lockdown_cfg function to make
it meaningful.
BUG=b:211954778
TEST=Able to build google/brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idaa0e089131ab125348e2430355041c4ee7971de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig
to skip FSP notify API (Post PCI Enumeration) and make use of native
coreboot driver to perform SoC recommended operations prior booting to
payload/OS.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.
[INFO ] coreboot skipped calling FSP notify phase: 00000020.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch performs locking of the PMC soft strap message interface.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC
MMIO register 0x104c is set as below.
> localhost ~ # iotools mmio_read32 0xfe00104c
0x00000001
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This area is used for storing AP RO verification data.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout
BRANCH=none
Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
MT62F1G32D4DR-031 WT:B
MT62F512M32D2DR-031 WT:B
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The unit of dram speed is MT/s so append it on variable name.
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I83c780440613050c0202f95d5f64991b61d9c280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
- enable CPU PCIe VGPIO for PEG60
- enable GPP_C3/ GPP_C4 native function
- set unused GPIO to NC
BUG=b:229584785
BRANCH=none
TEST=build and boot into kernel v5.10
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.
BUG=b:229549930
BRANCH=none
TEST=build and pass memory training
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
BUG=b:229547171
BRANCH=none
TEST=pass memory training with error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If6acf8cb9474f816374743fd1e800da46958993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
If set OEM string as "", it shows "Not Specified" with dmidecode.
Use default string if it is empty.
BUG=b:230039300
TEST=set OEM string "" and show google with dmidecode -t 2.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I097e1be696ae974aadc47feb8d0c1dae672a5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Camera LED flicker 3 times or so as sensor is being probed
during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot preventing camera LED flicker.
Corrects that by explicitly sequencing the reset GPIO and power GPIO
BUG=b:219644184
TEST=Build and boot on vell, observe whether camera LED flickers
Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set native function (SD_AUX_RESET_L), and drive it high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There is a bug floating around where communciation with the PMC fails
after transitions through S3/S4/S5. This CL does not address that issue.
However in working with error cases presented by a failing PMC, we're
forced into an early return in read_pmc_lpm_requirements(), which sets
up _DSM buffers in the SSDT for the PEP device.
The function itself returns void, so the error is swallowed regardless.
However returning early is not the appropriate action because it causes
the size of the buffer written into the _DSM method to change. This causes
the SSDT to change size and layout across an S3 or S4 transition, which
results in mayhem in the kernel, as the kernel is not expecting these
tables to change out from under it.
Instead of returning early, it's better to simply print the error and
keep going, attaching a zeroed out buffer for the substate requirements.
This results in an empty requirements mask for all states. From what I
can see in the kernel this is no more broken than today's behavior, as
this buffer seems to only be used for printing a debugfs file.
In fact in this particular case the kernel doesn't even notice, as this
buffer is copied out at boot, and not refreshed at resume.
BUG=b:230031158
TEST=hibernate and resume on Primus4ES
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ibe35d50b350b1b96dea313dfcbd00745970c16ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
We need to include the SMM handler to enable SCI events when ACPI is
enabled.
With this enabled we now see we have EC timeout problems while in SMI:
[SPEW ] SMI# #1
[WARN ] SMIx88 => 0x800
[DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG] Chrome EC: UHEPI supported
[ERROR] Timeout waiting for EC QUERY_EVENT!
[DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
[ERROR] EC returned error result code 1
[DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb
We still need to debug that. I suspect we have problems reading from
the ACPI IO decodes 0x62 or 0x66.
BUG=none
TEST=Verify SMI handler runs
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
* Use GPE 24 since it doesn't conflict with any existing GEVENTS.
* Remove IRQ 12 mapping since it's not used.
* Unmask IRQ1 in PM registers.
* Use the new SMITYPE_ESPI_SCI_B SCI.
BUG=b:227282870
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Felix Held