This reduce the difference with linux v5.19-rc7.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I04e58aca4a30e82f3da0cda08403d0daf3b5fb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This reduce the difference with linux v5.19-rc7.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I79170a45cd8184ebc816b4f16656a3cfdc257f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This reduce the difference with linux v5.19-rc7.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I222e3378ded4cd73d0141cd1e38ac3282d311cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This reduce the difference with linux v5.19-rc7.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bd68e9a6609a3dfa7dc856f24e4b616714d9990
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This reduce the difference with linux v5.19-rc7.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia7d4b0176bad849e79f037f74c3d99ce9eb061c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Commits that fix a recently-introduced regression can be submitted early
to minimise the impact of said regression. However, it is important that
the commit message properly reflects what is being fixed and what commit
introduced the issue.
Change-Id: Ifd49582ae1cbcfe6ee3816e0658dbd0432801161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63780
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Add support for hardware watchdog event logging
BUG=b:221393157
TEST=Validated on qualcomm sc7280 development board by manually
triggering watchdog event and event was logged at next bootup.
Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com>
Change-Id: I94971ab583f49c8a5ac232833215dbdad3a4d272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65528
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ported back from commit ceaf9d1169 ("soc/intel/alderlake:
Allow possible options for MP Init")
This patch creates choice that lists all possible options to perform
MP Init as below for Intel Meteor Lake platform:
1. MTL_USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP
runs feature programming based and selects MP_SERVICES_PPI_V2 config.
2. MTL_USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP
init and feature programming) using native implementation.
Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot
is expected to run MP Init.
Refactor SoC code to allow required FSP UPD override based on
selected MP Init option.
Additionally, added `FIXME` comment to ensure Intel MTL FSP can bring
back SkipMpInit UPD in MTL to let coreboot override this UPD and ensure
independent MP Init flow.
BUG=b:219053812
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic917e4e03e24d73190cfc72c6ed8e59af427bedf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65743
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables coreboot doing Multiprocessor Initialization (MP)
for Meteor Lake CPU using the native coreboot drivers and passes the
MP PPI data structure to let FSP to perform CPU feature programming
(anything that is restricted) as part of FSP-S.
Additionally, modify the kconfig inclusion order alphabetically.
BUG=b:219061518, b:219053812
TEST=Able to bring all APs from reset by coreboot and successfully
able to perform all CPU feature programming using MP PPI services.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2781ee0b39e42aa579b72d3d4ee6586d5a89a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures Intel Meteor Lake can enable the X2APIC feature.
While debugging Intel Meteor Lake (MTL) based platforms it seems like
enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to
bring the application processors (APs) from reset using X2APIC mode.
[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[ERROR] Not all APs checked in: 0/3.
[DEBUG] 0/3 eventually checked in?
[ERROR] MP initialization failure.
[ERROR] MP initialization failure.
Note: The AP bring up flow between XAPIC and X2APIC are the same
except the way to access those LAPIC registers. X2APIC expects to
access all LAPIC registers using MSR (base with 0x800).
The correct flow to enable X2APIC on MTL would be as follows:
1. Let BSP bring all APs in XAPIC mode.
[INFO ] LAPIC 0x10 in XAPIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x11 in XAPIC mode.
[INFO ] LAPIC 0x0 in XAPIC mode.
[INFO ] LAPIC 0x80 in XAPIC mode.
2. Call enable_x2apic() function on all CPUs (BSP and APs)
And at the end of #2 above, all cores will now switch to X2APIC
from XAPIC.
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device a06a0
[DEBUG] Clearing out pending MCEs
[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[DEBUG] CPU: vendor Intel device a06a0
[DEBUG] Clearing out pending MCEs
[INFO ] LAPIC 0x11 switched to X2APIC mode.
Note: Intel MTL FSP also follow the same steps for x2APIC enablement
while coreboot selects USE_INTEL_FSP_MP_INIT config instead
MP_SERVICES_PPI_V2.
BUG=b:219061518, b:219053812
TEST=Able to perform coreboot doing AP init with
DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into
any hang issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes a missing header file compilation issue when coreboot
selects MP_SERVICES_PPI_V2 config from MTL SoC.
The `MpServices2.h` file doesn't exist in the upstreamed EDK2 repo
(integrated with `edk2-stable202111` stable tag).
Currently MpServices2.h file is being copied from the
`edk2_stable202005` stable tag.
BUG=b:237960384 ([Intel FSP][EDK2011] MpServices2.h header is missing
in upstream EDKII git)
TEST=Able to fix the compilation issue on Google/Rex (Meteor Lake)
when MP_SERVICES_PPI_V2 kconfig is enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib7c406ff51439c93c6d15f3a69808b4d1590cfa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65624
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel Meteor Lake SoC expects to select late x2APIC enablement where
AP bring up will use xAPIC and later x2APIC gets enabled using CPU init.
This patch provides an option where SoC code choose the correct
LAPIC access mode using choice selection.
BUG=b:219061518, b:219053812
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6b50a0f5e39a95c25cd2c72219d2b402550a6fad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65786
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add option to do AP bringup with LAPICs in XAPIC mode and
switch to X2APIC later in CPU init.
Change-Id: I94c9daa3bc7173628f84094a3d5ca59e699ad334
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65766
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit e54a8fd432 (soc/intel/meteorlake:
Add entry for GSPI2 device) added an entry for the GSPI2 device in the
devicetree, but did not add any other entries. Ensure that the rest of
the code is aware of the GSPI2 device to avoid any problems.
Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0
Found-by: Coverity CID 1490681
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The `IMAGE_ALIGN` macro is unsafe because its value is compound and is
not enclosed in parentheses, which can cause operation order problems.
However, as this macro is unused, remove it instead of fixing it.
Change-Id: I099c291f44d5a2c9d32c9ff071374016ed27eee8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Messages shown with the '$(info ...)' Make command could be shown twice
because the entire Makefile stack was evaluated twice at MAKELEVEL 0.
The first time was to generate the build/util/kconfig/Makefile.real
file. The second time was to do the rest of the build. Adding the
kconfig Makefile.real file to the nocompile list prevents all the rest
of the coreboot makefiles from being read in during that first step,
which prevents the messages from being printed twice.
You can see this behavior by running "make clean; make -d" and searching
for the text:
"Successfully remade target file 'build/util/kconfig/Makefile.real'."
This breaks when the build target is 'tools', so add an exception for
just that target.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If29c3a84c7c82ea099ef9610f4ecaa599f0d8649
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
It probably was supposed to be *making these names conistent …*, but
short that a little, and add a missing article.
Change-Id: If88ff6d7b0a61aa83d5822b5e1c0b5b4c9d3bb3c
Fixes: ac136250b2 ("commonlib: Substitude macro "__unused" in compiler.h")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65884
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"else" is unuseful after a "break" or "return".
Change-Id: I7273b9af46a2310c9981ffd20afe2c8c7e061479
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60910
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
These enums & macros will be used to report resources with acpigen_*
functions (Currently those resources are reported in northbridge.asl,
but follow-up CLs will remove this file and add the need acpigen code).
BUG=b:148759816
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: I5b95c9b8370db63537eb48b640ad8f0e750efd69
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65768
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use correct HID names instead of the CID names for the touchpad devices.
Drop the now unneeded UID for the gaze15 TP devices.
Tested on a gaze15 with a Synaptics device. Windows does not crash on
boot and the touchpad is still detected as an I2C HID device.
Change-Id: I5b6ab1a23ce667754d0c5757062385a721c5113f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. Add wifi sar table for osiris
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:234951991
TEST=build FW and checked SAR table can load by WiFi driver.
Cq-Depend: chrome-internal:4871098
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Configure the dGPU power and reset pins in bootblock instead of
ramstage. This fixes a conflict with our downstream driver, which
configures these pins to enable dGPU power in romstage. Behavior remains
unchanged without the driver as the dGPU is left powered off.
Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Elyes Haouas