Commit Graph

43653 Commits

Author SHA1 Message Date
Felix Singer 0dcdb217cf soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.

If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.

Also, add a release note for the upcoming 4.15 release.

Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28 18:21:26 +00:00
Casper Chang 621ae7c701 mb/google/brya/variants/primus: update USB 2.0 controller Lane Parameter
Modify USB 2.0 port5 parameter to improve SI diagram measurement.

BUG=b:187992881
TEST= Pass USB 2.0 SI Eye diagram measurement.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1eff05a7ad6563898744c24f9657e28625319873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28 17:44:51 +00:00
Wisley Chen 0d753e5108 mb/google/dedede/var/drawcia: Add fw_config probe for ALC5682-VD/ALC5682-VS
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:194356991
TEST=ALC5682-VD/ALC5682-VS audio codec can work

Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28 17:44:34 +00:00
stanley.wu b4481e0bd4 mb/google/dedede/var/boten: Generate SPD ID for supported part
Add supported memory part in the mem_parts_used.txt and generate the
SPD ID for the part. The memory part being added is:
MT53E512M32D1NP-046 WT:B

BUG=b:194223174
BRANCH=dedede
TEST=Build the boten board.

Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28 17:44:15 +00:00
Wisley Chen 54598a6ba5 mb/google/brya/var/anahera: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

MT53E1G32D2NP-046 WT:A
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
MT53E512M32D2NP-046 WT:E
H9HCNNNCPMMLXR-NEE
K4UBE3D4AA-MGCR
H9HCNNNFAMMLXR-NEE
MT53E2G32D4NQ-046 WT:A
MT53E512M32D1NP-046 WT:B
MT53E1G32D2NP-046 WT:B

BUG=b:197850509
TEST=build pass

Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28 17:44:03 +00:00
Frank Wu 1693f6e09a mb/google/dedede/var/driblee: Configure I2C ports and touchpad
Update the I2C ports and touchpad based on the schematic.

BUG=b:195622489, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 17:43:27 +00:00
Frank Wu ba1091a0e6 mb/google/dedede/var/driblee: Configure USB port settings
Update the USB port configuration based on driblee schematic.

USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 1
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: None

USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None

BUG=b:195622487, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 17:43:07 +00:00
Martin Roth dd6c7331ac mb/(amd,google): Update SPI Kconfig settings based on devicetree
This takes the devicetree SPI settings and moves them into Kconfig.

BUG=b:195943311
TEST=boot guybrush & majolica and verify spi settings.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28 17:42:22 +00:00
Sumeet Pawnikar f032221bd1 mb/google/brya: Add two sensors for DPTF functionality
Add two thermal sensors for fan and wwan for DPTF based thermal control.

BRANCH=None
BUG=b:181271666
TEST=None

Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
2021-08-28 17:39:54 +00:00
Bernardo Perez Priego 4b53474d23 mb/intel/adlrvp_m: Enable touchscreen
This will add ACPI information to enable WACOM touchscreen.

TEST=Boot DUT and issue command:
     $ ls -al /sys/bus/i2c/devices
     WACOM PWB-D893 device should be listed and touchscreen should be functional.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-28 01:24:35 +00:00
Ian Feng c375feecc5 mb/google/dedede/var/corori: Generate RAM ID and SPD file
Add the support RAM parts for Corori.
Here is the ram part number list:

DRAM Part Name                 ID to assign
H9HCNNNBKMMLXR-NEE             0 (0000)
K4U6E3S4AA-MGCR                0 (0000)

lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR

BUG=b:196744958
BRANCH=keeby
TEST=emerge-keeby coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 01:24:19 +00:00
Ian Feng b26e613bed mb/google/dedede/var/corori: Configure thermal sensor setting
According to schematics, TSR2 thermal sensor is not present in corori.

BUG=b:197281317
BRANCH=keeby
TEST=FW_NAME="corori" emerge-keeby coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Id69f9d6ace738ef1e792addd782d05c2d03d2b3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57110
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 01:23:55 +00:00
Ian Feng aed85c0757 mb/google/dedede/var/corori: Configure I2C ports and touchpad
1. Support Elan touchpad.
2. Follow schematic to disable I2C1, I2C2 and I2C3.

BUG=b:197052531
BRANCH=keeby
TEST=FW_NAME="corori" emerge-keeby coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ideef57c275432e21f8580d4c5c937909b168d91f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57031
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 01:23:38 +00:00
Ian Feng 611b5e2bb2 mb/google/dedede/var/corori: Configure audio setting
Select the drivers for ALC5682 codec and MAX98360A spk amp

BUG=b:197037090
BRANCH=keeby
TEST=FW_NAME="corori" emerge-keeby coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I0659a05fbcc28702d922a23d74885ba65a4254f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57015
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 01:23:13 +00:00
Ian Feng a55f4065c8 mb/google/dedede/var/corori: Configure USB port settings
Follow schematic to modify USB port settings.

USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: Integrated Bluetooth

USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None

BUG=b:196998272
BRANCH=keeby
TEST=FW_NAME="corori" emerge-keeby coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28 01:22:58 +00:00
Ian Feng be2858e22e mb/google/dedede/var/corori: Configure GPIO settings
Updated the GPIO pins based on the latest schematic.

BUG=b:196867404
BRANCH=keeby
TEST=FW_NAME=corori emerge-keeby coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28 01:22:43 +00:00
Wisley Chen 20b2d8a52c mb/google/brya: Create anahera variant
Create the anahera variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:197850509
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANAHERA

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28 01:22:16 +00:00
Angel Pons 1f4e78f651 mb/google/butterfly: Put braces around `else` branch
Ensure braces are consistent on all branches of a conditional statement,
as per the coding style.

Tested with BUILD_TIMELESS=1, Google Butterfly remains identical.

Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-27 20:01:55 +00:00
Felix Held 5bdc7c8850 mb/amd/majolica/Kconfig: add EFS SPI settings
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100
case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to
Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config
for the EM100 emulator case that has limited SPI frequency support.

Tested on Majolica by Martin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 18:26:26 +00:00
Angel Pons 2d45322639 broadwell: Drop weak `mainboard_fill_spd_data` definition
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define
this function accordingly.

Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 16:04:33 +00:00
Angel Pons 2bc7a6b3d2 soc/intel/broadwell: Move `mainboard_fill_spd_data`
Move the `mainboard_fill_spd_data` function out of romstage, in
preparation to confine `pei_data` usage to as few files as possible.

Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 16:04:10 +00:00
Angel Pons 887b779c11 Broadwell boards: Do not assign unused SPD addresses
The `pei_data` struct is already zero-initialised.

Change-Id: If539cddc007f32a04389bc3b3b06c43cb5c86e10
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55804
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 16:03:50 +00:00
Angel Pons 19f1e9104a mb/google/auron: Refactor memory-down SPD handling
Variants only need to provide the SPD index and whether said index
corresponds to a dual-channel configuration, which can be achieved
without using `pei_data`. Add two functions that return the values
and use them in `spd.c` at mainboard level.

Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-27 16:03:32 +00:00
Ariel Fang 3533808a6d mb/google/brya/variants/primus: Enable SaGv support
This patch enables SaGv support for primus.

BUG=b:196286180

Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I00074e348dd6347602c18dcfd231a890153b4685
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27 16:01:20 +00:00
Furquan Shaikh ba936ce5db soc/intel/denverton_ns: Ensure CPU device has a valid link
This change calls `add_more_links()` in `denverton_init_cpus()` if
`dev->link_list` is NULL. This condition can occur if mainboard does
not add any APIC device in the device tree.

Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the
same SKU and steping (Intel Atom C3538)."

Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 15:58:42 +00:00
V Sowmya c398a204b4 mb/intel/adlrvp: Enable SaGv support
BUG=b:187446498
TEST=Boot and verify memory trains at all the SaGv points through FSP
debug logs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-27 04:36:33 +00:00
Trevor Wu 1d19432e1e mb/google/cherry: Support audio codec RT1011
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011.
Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can
spearate code for the specific codec by config.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I18939a2a2caae0444ce17f4712764647975121ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:54:22 +00:00
Yu-Ping Wu 52889c9c9f libpayload: cbgfx: Clear screen by sequential access
Currently clear_screen() calls set_pixel() to set all pixels. However,
the actual order of pixels being set depends on the framebuffer
orientation. With NORMAL orientation, the framebuffer is accessed
sequentially; with LEFT_UP/RIGHT_UP orientation, it is accessed back and
forth, leading to performance drop (>1 second on bugzzy).

Therefore, ensure sequential access to the framebuffer, regardless of
the orientation.

BUG=b:194967458
TEST=emerge-cherry libpayload
BRANCH=dedede

Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57104
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:53:38 +00:00
Johnny Lin b69d1dea47 Doc/mb/ocp: Update Delta Lake documentation for RAS features
Change-Id: I71b97930f1a1ca4a60f830a90d80af6ca0236c8e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-08-27 02:51:59 +00:00
Frank Wu 5d797a6b54 mb/google/dedede/var/driblee: Configure GPIO settings
Updated the GPIO pins based on the latest schematic.

BUG=b:191732473, b:195619827
BRANCH=keeby
TEST=FW_NAME=driblee emerge-keeby coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I20baeb6b13c8c0a70c7555aa8f7f5557768c0083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56996
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:51:32 +00:00
Martin Roth c47155da3a soc/amd/common/block/spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree.  We'd like to have everything in one place.  Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig.  Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.

BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:51:05 +00:00
Wisley Chen 3412d28b45 mb/google/dedede/variant/drawcia: Include SPD for MT53E512M32D1NP-046 WT:B
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B.
This part is already in global_lp4x_mem_parts.json.txt, and use
/util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs.

BUG=b:196951879
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage

Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:50:31 +00:00
Zhi Li d59c950379 mb/google/dedede/var/sasukette: Add FW_CONFIG probe for EXT_VR
commit df520855 (soc/intel/jsl: Add disable_external_bypass_vr config)
Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC.

BUG=b:190727416
BRANCH=dedede
TEST=test for enter S0ix and resume normally by powerd_dbus_suspend

Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I15ab30f14df9dc02157009091aa8398e2fa75188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56804
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:47:13 +00:00
Felix Held 8d268e9bda soc/amd/common/fsp/fsp_validate: add runtime check for FSP-M binary size
When modules are added to the FSP and they won't fit into the FSP binary
any more, the size can be increased in the FSP build. Especially in the
case of debug builds the increased size might not fit into the memory
region it gets decompressed into which starts at FSP_M_ADDR and has a
size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header
function that ends up being called by the FSP driver in romstage to do
some additional checks on the FSP binary's header that includes the
version number and the image size. We can use the image size field to
check if it fits into the reserved region. Since the FSP-M memory region
is located after romstage loading it won't clobber the romstage code
where we do the check.

This runtime check is added in addition to the build-time check to also
cover the case when the FSP binaries in CBFS get replaced with ones that
don't fit into the reserved memory region after the coreboot build.

BUG=b:186149011
TEST=Mandolin still boots fine with the patch applied. When as a test
the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000
which is by far not enough for the decompressed FSP-M binary to fit into
it prints the newly added error message on the console and then stops.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:32:11 +00:00
Ricardo Quesada 2e0b5c4007 elog: Define constant for RW region name
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the
hardcoded "RW_ELOG" value. This constant will be used also by elogtool
(see CL in the commit chain).

BUG=b:172210863

Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26 18:50:56 +00:00
Ricardo Quesada e929a75fbe elog: move functionality to commonlib/bsd
This commit moves some drivers/elog/ functionality to commonlib/bsd
since they will be called from util/cbfstool/.

In particular:
 * elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event()
   were moved to commonlib/bsd/elog
 * elog_fill_timestamp() receives the time parameters and updates the
   event based on the "time" arguments.

The original elog_*() functions were written by Duncan Laurie
(see CB:1311) and he gave permission to re-license the code to BSD.

BUG=b:172210863

Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 18:50:29 +00:00
Sheng-Liang Pan 778380ac74 mb/google/octopus: add CBI SKU RAM ID 5
add CBI sku RAM ID 5 for 4GiB Capacity with dual channel and dual rank
with 4gb dram density.

BUG=b:178665760
BRANCH=Octopus
TEST=build fw and flash to the dut with RAMID 5, dut can boot up successfully.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I922a518cffc4dac71caec68e6f7a55c6c5717438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56982
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26 18:25:32 +00:00
Seunghwan Kim 11f966df23 mb/google/dedede/var/bugzzy: Configure USB ports
Override USB port configurations based on the latest bugzzy schematics.

BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image

Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-26 18:24:57 +00:00
Tim Wawrzynczak 58966086cd soc/intel/tigerlake: Lock PAM registers in finalize
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.

Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 18:23:52 +00:00
Tim Wawrzynczak 091dfa1ca0 soc/intel/alderlake: Lock PAM registers in finalize
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.

TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 18:23:40 +00:00
Tim Wawrzynczak d87af79ace soc/intel/common/block: Add PAM locking function
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit
instead of the FSP, therefore add a function in the common code to do
this. Source: ADL & TGL FSP integration guides

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 18:23:24 +00:00
Wisley Chen 30c6ca9838 mb/google/var/redrix: Correct the WWAN_PERST_L setting
WWAN_PERST_L (GPP_E0) is wrongly configured to NC in ramstage.
So, remove it.

BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: If8e96045a0d78a942f77d8d8e371ab75dff0c202
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26 18:22:25 +00:00
Wisley Chen 9413f4ef1b mb/google/brya/variant/redrix: Correct MAX98390 AMP setting
4 MAX98390 Speaker Amps are connected to i2c0 and device addresses are
0x38/0x39/0x3a/0x3b

BUG=b:191931762
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ie8f01e6a7e09e18f6d34f3ceb1db8e2e238197bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57114
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26 15:19:28 +00:00
Felix Held 42df9af4c4 drivers/intel/fsp2_0: rename soc_validate_fsp_version
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it
can not only be used to check the version info in the FSP-M binary's
header, but also to check every other field in the binary's header. This
is a preparation for a follow-up patch that implements this function to
check the FSP-M binary's size.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 15:19:06 +00:00
Felix Held e44dad3096 soc/amd/common/fsp/Makefile: check if FSP-M is larger than FSP_M_SIZE
The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.

BUG=b:186149011

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26 15:18:58 +00:00
Julius Werner 5ff1808f20 device/mipi: Move to drivers/mipi
Sounds like we prefer to have this under drivers/ instead of device/.
Also move all MIPI-related headers out from device/ into their own
directory.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26 15:18:45 +00:00
Bhanu Prakash Maiya 7d41491e76 mb/google/guybrush: Create dewatt variant
Create the dewatt variant of the guybrush reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:196460993
BRANCH=None
TEST=util/abuild/abuild -p none -t google/guybrush -x -a
make sure the build includes GOOGLE_DEWATT

Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26 14:24:39 +00:00
Julius Werner ab91407735 tests: Fix function mocking for clang
clang seems to like to do some aggressive optimizations that break our
approach of mocking functions for test by using objcopy to turn them
weak after the fact on individual compiled object files. For example, in
CB:56601 the function cbfs_get_boot_device() is mocked this way. When
compiling the cbfs_boot_lookup() function in src/lib/cbfs.c with clang,
it will generate a normal callq instruction to a relocation for
cbfs_boot_lookup(), which can then later be pointed to the mocked
version of that function. However, it will also somehow infer that the
version of cbfs_boot_lookup() in that file can only ever return a
pointer to the static local `ro` variable (because CONFIG_VBOOT is
disabled in the environment for that particular test), and instead
generate instructions that directly load the address of a relocation for
that variable into %rdi for the following call to cbfs_lookup(), rather
than using the real function return value. (Why it would do that is
anyone's guess because this seems unlikely to be faster than just moving
the function return value from %rax into %rdi like a normal compiler.)

Long story short, this optimization breaks our tests because
cbfs_lookup() will be called with the wrong pointer. clang doesn't
provide many options to disable individual optimizations, so the only
solution seems to be to make clang aware that the function is weak
during the compilation stage already, so it can be aware that it may get
replaced. This patch implements that by marking the mocked functions
weak via #pragma weak lines in the per-test autogenerated config header.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1f9011f444248544de7a71bbefc54edc006ae0cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-08-25 20:54:16 +00:00
Felix Singer 2b59fa7a8e mb/roda/rv11/acpi: Use lower case format for hex values
Change-Id: I3bea9e1f9cc25a4476ddbaa8bd8e434609eb28f7
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25 20:52:51 +00:00
Felix Singer ed52488b59 mb/roda/rv11/acpi: Use Printf ()
Change-Id: Iec6ec8bbf3cc5c9230ba6bcb0126ff6085f26464
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25 20:52:46 +00:00