To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Most of the components of this laptop are tested to work,
which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
New port based on autoport.
Autoport worked with minor tweaks, but fan speeds went almost
immediately to the maximum. They are controlled by the NPCD379
Super I/O which isn't supported by coreboot.
But coreboot already has code for NPCD378,
which HP Compaq 8200 SFF makes use of.
So SuperIO configuration was copied from the 8200 SFF port.
It seems to work without any issues in "normal" use.
Most importantly, fan speed control seems to work correctly.
However this means that some of the SuperIO LDNs may be configured
incorrectly. See the comments on Gerrit for more information.
The following is tested and is working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
* GRUB (with Libreboot config)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui
Untested:
* mSATA slot. The SATA port needs to be enabled on devicetree
too, but I'm unable to test due to lack of hardware
* Line in, mic input
* MXM graphics card
* EHCI debug
Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
maybe it just isn't present
* PS/2 keyboard wake from S3
Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of the code is taken from 2570p, adjusted with autoport, SuperIO
from 8470p and inteltool, GPIO config from inteltool via autoport.
The laptop works well under coreboot with SeaBIOS 1.16.1 payload,
running Debian GNU/Linux with kernel 6.1.15.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I854104516d5b6fbd78ee2989197000a7dbb85136
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73856
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for z220_series.
[1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1
BUG=b:235293589
TEST=./util/abuild/abuild -t HP_Z220_CMT_WORKSTATION -a \
# with VBOOT enabled and a custom FMDFILE with RW_NVRAM region
Change-Id: I1c60a44fb12fd093f45cf54ef2f9e0e02afc80bd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
HP Z220 series has PCI slot(s) but Interrupt Routing Table in ACPI
used to be missing, so one is added.
Note that the values within the added one are obtained from my own SFF
variant. If other variants have different values, please add them in a
manner similar to mb/gigabyte/ga-b75m-d3h/acpi/pci.asl.
Test result:
Log lines like
pci 0000:00:1e.0: can't derive routing for PCI INT A
ath9k 0000:04:00.0: PCI INT A: no GSI
disappeared from dmesg.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I8522b25ac46db2054302c8f2418927c722b157e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68334
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without these, all SuperSpeed ports are wired to EHCI #2.
"superspeed_capable_ports" and "xhci_switchable_ports" should fit both
CMT and SFF variants, while "xhci_overcurrent_mapping" should be
consistent with the first 4 elements of mainboard_usb_ports[].
With this commit, SuperSpeed devices plugged in SuperSpeed ports are
wired to the XHCI on my own Z220 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files contain no creative content, and therefore have no
copyright. This effectively means that they are in the public
domain.
This commit updates the unlicensable empty (and effectively empty)
files with the CC-PDDX identifier for license compliance scanning.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Move configs for PCIe ports not present on z220_sff_workstation
from the devicetree.cb of base board to the overridetree.cb of
z220_cmt_workstation.
- Add a note for ME/AMT Flash Override jumper, for it is hard to
flash from OEM firmware either internally or externally without
closing this jumper.
- Add a side note for similar HP Compaq Elite 8300 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apparently all nine HP Sandy/Ivy laptop variants select
MAINBOARD_USES_IFD_GBE_REGION. So let's move it to the COMMON section.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I48e0d03c59d3ba013b479b59df8a15a0f8d23c50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I9593c24f764319f66a64715d91175f64edf10608
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is based on previous work done by a good friend of mine.
The notable differences between this board and the SFF variant is that:
- CMT has 4 more PCI/PCIe ports than SFF.
- CMT has 2 more SATA ports than SFF.
TESTED on Z220 CMT Workstation (boots to payload)
Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No functional change, just refactoring to make room for CMT variant.
Built with BUILD_TIMELESS=1 and no config included before and after.
$ diff master.rom build/coreboot.rom
$
TESTED: boots to SeaBIOS on HP Z220 SFF
Flashed bios region internally, mainboard also has FDO
(flash descriptor override) jumper that allows r/w to whole flash.
Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.
Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.
Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All Skylake mainboards use the default value for the setting `SataMode`.
Thus, drop it from their devicetree.
Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to common GNVS. No additional fields to those being present in
common GNVS are used by any SKL/KBL device. Thus, they're dropped
completely.
Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:
config VGA_BIOS_FILE
default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200
Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.
Also, update autoport to not generate `VGA_BIOS_FILE` defaults.
Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_MAX` Kconfig symbol once.
Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The `ASSERT` macro is already defined in `src/include/assert.h`, and
AGESA's definition is never used. On Asus A88XM-E, toggling the value of
the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary
when using reproducible builds. Attempting to use AGESA's definition of
the `ASSERT` macro results in build errors:
In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info':
src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value]
#define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
Given that coreboot's definition of `ASSERT` is more useful, drop
AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro.
Also remove the `IdsAssert` function, as it is no longer used anywhere.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
