SMMINFO is already set up in S5, so it should be skipped in S3 resume
BUG=b:194990818
TEST=Build guybrush
Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The separate FMD file for Kano is no longer required, as it was
only required for early prototype testers, and those devices will
be retired soon, therefore switch back to the original FMD file.
BUG=b:226018550
TEST=Build pass.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Ti50 FW under 0.15 is not support board cfg command which causes I2C
errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed.
Add workaround for the old Ti50 chip.
BUG=b:224650720
TEST=no I2C errors in coreboot.
[ERROR] cr50_i2c_read: Address write failed
[INFO ] .I2C stop bit not received
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Precision is a Mid Tower chassis platform with very similar mainboard
to OptiPlex 9010. It has one more PCIe port and a PCI port. It also
incorporates C216 chipset instead of Q77 and enables DRAM ECC support.
Other changes are related to subsystem ID and fan control
initialization.
TEST=Boot Dell Precision T1650 and launch Debian 10.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
New boards like Dell Precision T1650 will be added as variants, in
subsequent commit. They share most of the code, except some EC
initialization tables, PCIe port configuration and subsystem ID.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
The patch add APIs to check CSE Region's write protection information.
Also, adds helper functions to get the SPI controller's MMIO address
to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read
protection details.
During the coreboot image build, write protection is enabled for CSE RO.
It is enabled through a Intel MFIT XML configuration.
TEST=Verify write protection information of CSE Region
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The Realtek RT8168 and RTL8111K have a similar programming interface,
therefore add the PCI device ID for the RTL8111K into driver for support.
BUG=b:226253265
TEST=emerge-brask coreboot chromeos-bootimage.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
The "Getting started" section is not an appropriate place for the
documentation license. It should rather be listed in the main menu.
Thus, move it there.
Change-Id: I8bfc4f52da8a93d78a62e3a68fd6f1dc8ae4d335
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
coreboot needs to propagate the CnviDdrRfim value info of the feature
enable/disable state into the CNVi via the WiFi DSM ACPI object. This
will be consumed by the Wi-Fi driver and it will act according to
CB enablement configuration. This patch adds _DSM method for that.
Add support for following 2 functions in _DSM method
- Function 0: Function Support Query Returns a bitmask of functions
supported.
- Function 3: RFI enablement 0 Feature Enable 1 Feature Disable
Note: Wifi Dsm already has provision for SAR. This patch will add
additional support to return RFIM structure based on UUID.
BUG=b:201724512
TEST=Build, boot brya0 and dump SSDT entries
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x09
})
}
If ((Local1 == One)){}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03))
{
Return (Zero)
}
Return (Buffer (One)
{
0x00
})
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This will allow configuring the concerned config through an external
defconfig file.
BUG=None
TEST=Ensure that AMDFW_CONFIG_FILE is configurable.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the two load line slope settings for the telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD scale: 73331 -> 94623
VDD offset: 1893 -> 1847
SOC scale: 31955 -> 29904
SOC offset: 852 -> 756
BUG=b:217963719
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
pass AMD SDLE/Stardust test
Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Backlight GPIO was set to HIGH, when it should have been set LOW to
enable the backlight in the embedded display.
BUG=b:224618411
TEST=load on Skyrim proto1, observe backlight
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change settings according to thermal team test results
BUG=b:215033682
TEST=build and tested fan works normally on taniks
Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.
Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Fix the HWM sequence matching to the chassis. HWM sequence for SFF
was incorrectly passed to MT chassis HWM initialization.
Vendor code also applies a fix-up for MT/DT chassis. This fixup was
missing one register read compared to the vendor code. Add the missing
read and guard the fixup depening on the returned value to match the
vendor code behavior. Not doing so resulted in increased fan speeds
on Dell Precision T1650 compared to Dell's firmware.
TEST=Boot Dell Precision T1650 and hear the fans are as silent as on
Dell's firmware
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.
BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.
Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable/disable LTE function based on LTE field of FW_CONFIG.
1. GPIO control
2. USB port setting
BUG=b:213582491
BRANCH=dedede
TEST=FW_NAME=beadrix emerge-dedede coreboot
Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62801
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds TCSS XHCI device ID for ADL-N CPU which is required
for USB3 port enumeration.
Document Reference: 645548 revision 1.0 (Chapter 2.3)
BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0
Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Windows 11 installer expects the TPM to reside under \\_SB_.PCI0 in
ACPI device hierarchy, otherwise the TPM is not detected. Hardcode
the path to fix the issue.
TEST=Boot Windows 11 on Clevo NV41MZ and see the TPM is detected
correctly
TEST=Boot Ubuntu 20.04 on Clevo NV41MZ and see the TPM is detected
correctly
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:224648680
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 2500 cycles passed on primus
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Originally, dram size is hard-coded to 4GB by default. To support
different dram size, calculate it from the mem chip info stored
in CBMEM.
BUG=b:206014043
TEST=Output "dram size: 0x100000000" on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Store dram info in cbmem for ramstage or payloads to use.
BUG=b:206014043
TEST=Build pass on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Update iPXE stable from commit id ebf2eaf515:
Mar 18 10:24:08 2019 +0000
[intel] Add PCI ID for I219-V and -LM 6 to 9
to commit id 6ba671acd9:
Jan 17 16:17:17 2022 +0000
[efi] Attempt to fetch autoexec script via TFTP
This brings in 424 new commits and fixes the build with coreboot-sdk
2021-09-23_b0d87f753c.
TEST=Build PC Engines apu2 board and boot it over network with the
iPXE
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide12a3a3082f9ea027e180518a80e6c0772b1232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Prevents bad things from happening later when these new nodes are used.
This issue is hard to observe because:
1. Heap is zero-initialized, so you need to use allocated memory
filling it with non-zero values, free, allocate it again, use
uninitialized.
2. Most of allocated memory is not freed.
3. Implementation of free() does something only for one last malloc'ed
block, making most of freed memory unavailable for future
allocation.
Change-Id: I38a7ec1949d80f7a2564fac380ce94de6056a0c7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 5a0ad1186 missed one chip config member that got converted to
snake case in commit 215a97ee1.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.
BUG=b:225206079, b:220685274
BRANCH=firmware-brya-14505.B
TEST=boot on brya0 and see:
[INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf
BUG=b:220814038
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf
BUG=b:219891328
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.
TEST=On Mandolin both IOAPICs are still correctly detected by Linux.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they also have the same exclusive ID.
BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.
BUG=b:210094309
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
GL9763e doesn’t support L0s state, so disable L0s at the root port.
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
This change provides config for devicetree to control ASPM per port
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The workaround causes the eMMC controller to not enter its L1
during the boot process
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.
BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>
"Total time" calculation changed after CL 59555 to include
"1st timestamp" value in the calculation. This patch restores original
Total Time calculation where "1st timetamp" is subtracted from
"jumping to kernel". If pre CPU reset timestamps are added (negative
timestamps), "Total time" calculation still includes the pre-reset time
as expected.
1) Before https://review.coreboot.org/c/coreboot/+/59555:
0:1st timestamp 225,897
1101:jumping to kernel 1,238,218 (16,316)
Total Time: 1,012,281
2) After https://review.coreboot.org/c/coreboot/+/59555:
0:1st timestamp 225,897
1101:jumping to kernel 1,238,218 (16,316)
Total Time: 1,238,178
3) After this patch:
0:1st timestamp 225,897 (0)
1101:jumping to kernel 1,238,218 (16,316)
Total Time: 1,012,281
BUG=none
TEST=Boot to OS, check cbmem -t on Redrix board
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The APCB files that provide the firmware components running on the PSP
some mainboard-specific information like the DRAM interface
configuration. Those files aren't yet in the upstream 3rdparty/blobs
repository, so only add those files if they are present and print that
no APCB was added and the image won't boot if they aren't present.
TEST=Both cases behave as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since CB:62741, the EC values are backed up to the CMOS when entering
S3, S4 and S5. Consequently, they don't need to be stored when they're
changed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If0ea392afae4a4d3c605cdea3c5896fbff606215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The EC values will be changed when entering S3, S4 or S5, so move
the function that stores the current settings outside of logic
that restricts it to S4 or S5. This means the state isn't lost
when entering S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.
Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add WiFi SAR table
BUG=b:225285426
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8fa833409bd69e080fda735c89015b9548252190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Fred Reitberger