Use 0x016llx to print device resource info so that both 64bit and
32bit resources could be displayed correctly.
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Change-Id: I0ec4c47cca4a09ceb7dc929efaa5630b1f9df81c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The check was recently removed to allow callers to pass `count == 0`.
Dereferencing the `msg` array is invalid in that case, though. Linux,
where we borrowed the i2c interface from, also treats this with -EINVAL.
Change-Id: I1eec02dd3a3fcf2d477a62cc65292fca40e469d3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
We actually want the bus driver to process the 1 zero-length write
we are passing. So set the count to 1.
Change-Id: I5a41abb68c27a83715b6baec91ece9fa90b66a8c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66337
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Some definitions are the same in dramc_soc.h for MT8192, MT8195 and
MT8186, so we move them to dramc_soc_common.h
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Retrieve the SKU ID for Geralt via CBI interface. If that failed
(or no data found), fall back to ADC channels for SKU ID.
- The RAM code is implemented by the resistor straps that we can read
and decode from ADC.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new config FSP_TYPE_IOT to add the IoT FSP option so that
respective mainboard Kconfig can use IoT FSP if needed.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I01d891348c039269138e64290ae3d6ec75d3c687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The latest master adds the missing MemInfoHob.h to IOT ADL-P &
ADL-S folders.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8ef998b2e414d3d63494e6177b4fde2dc26e9d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:240600260
TEST=emerge-draco coreboot
verified by thermal team
Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
UFS storage devices require the bRefClkFreq attribute to be set to
operate correctly in high speed mode. The correct value is determined by
what the SoC / board supports. For the ADL UFS controller, it is
19.2 MHz.
a) Introduce a new ACPI property "ref-clk-freq".
b) Add support to configure this property using an SoC Kconfig.
Kernel patch:
https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/
20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/
BUG=b:238262674
TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel
correctly parses ref-clk-freq as 19.2 MHz.
Scope (\_SB.PCI0)
{
Device (UFS)
{
Name (_ADR, 0x0000000000120007) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
/* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"ref-clk-freq",
0x0124F800
}
}
})
}
}
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Switching off the pads of the internal crystal oscillator that connect
to the crystal on the board in S0i3 saves a little power, so enable it.
No measurements to quantify the power savings have been made. PPR #57243
revision 1.59 was used as a reference.
BUG=b:237647468
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
- Add support for edp aux read and write.
- Update edp panel properties based on edid read.
- Configure edp controller and edp phy.
Panel details:
Manufacturer: SHP Model 1523 Serial Number 0
Made week 53 of 2020
EDID version: 1.4
Digital display
8 bits per primary color channel
DisplayPort interface
Maximum image size: 31 cm x 17 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4
Default (sRGB) color space is primary color space
First detailed timing is preferred timing
Supports GTF timings within operating range
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 5a8780a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 653880a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Hex of detail: 000000fd003090a7a7230100000000000000
Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock
350MHz
Hex of detail: 000000fc004c513134304d314a5734390a20
Monitor name: LQ140M1JW49
Changes in V2:
- Remove Misc delays in edp code.
- Move mdss soc code to disp.c
- Update EDID read using I2C write & read.
Changes in V3:
- Remove unrelated delays.
- Misc changes.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Change-Id: If89abb76028766b19450e756889a5d7776106f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This patch adds a function to calculate best rational approximation
for a given fraction and unit tests for it.
Change-Id: I2272d9bb31cde54e65721f95662b80754eee50c2
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66010
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gcc 12 fails the build with the warning below:
CC romstage/lib/cbfs.o
src/lib/cbfs.c: In function 'switch_to_postram_cache':
src/lib/cbfs.c:31:32: error: comparison between two arrays [-Werror=array-compare]
31 | if (_preram_cbfs_cache != _postram_cbfs_cache)
| ^~
src/lib/cbfs.c:31:32: note: use '&_preram_cbfs_cache[0] != &_postram_cbfs_cache[0]' to compare the addresses
Instead of following gcc’s suggestion, disable the warning for gcc as
requested by Julius [1]:
> Can we just set -Wno-array-compare instead? There's nothing illegal
> about that expression and as we can see in this case, there are
> perfectly reasonable cases where you might want to do something like
> that. On the other hand, I don't really see a realistic scenario where
> this warning could prevent a real problem (anyone who doesn't know
> that array1 == array2 doesn't compare the array elements in C
> shouldn't have any business submitting code to coreboot).
[1]: https://review.coreboot.org/c/coreboot/+/62827/1
Found-by: gcc-12 (Debian 12-20220313-1) 12.0.1 20220314 (experimental) [master r12-7638-g823b3b79cd2]
Found-by: gcc (Debian 12.1.0-7) 12.1.0
Change-Id: I322f7cc57dcca713141bddaaaed9ec034898754d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.
BUG=b:180458099
TEST=Boot DDR5 to kernel
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Follow latest schematic, GPP_A17 is used to enable AMP power.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check I2C scan can see the AMP return ACK.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Use the new "detect" method instead of "probed". Fixes an uncommon issue
where i2c-hid fails to initialize the device on Linux.
Tested on: gaze15, gaze16-3060, lemp10, oryp8
Tested:
- Linux: Touchpad works across 50 reboots
- Windows: Touchpad is still detected as an I2C HID device
- Windows: Extra I2C HID devices are not shown in Device Manager
Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
the missing `; \` at the end of the line meant subsequent lines
were no longer run from $project_dir, so Logo.bmp was silently
failing to restore. This led to the working dir being dirty,
and on subsequent runs, any change to a different branch in the
same repo would fail.
Change-Id: I17a323bc2dda19b69d809e398b273f24e14b43af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66321
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copy the constraint from ADL-S to ADL-P.
Fixes the following warning in Linux on System76 oryp9, which has an
NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack track on every boot.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000bf549647>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: I550c80105ff861d051170ed748149aeb25a545db
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure eMMC DLL tuning values for Craask board.
BUG=b:238985924
TEST="Use the value to boot on Nivviks and Craask successfully."
Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The first CSE Lite SKU is available, therefore enable the Kconfig
option to have the CSE reboot the system into its RW FW during a cold
boot.
BUG=b:240228892
TEST=TBD
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve
FW slot boot information like (tries count, current boot slot, previous
boot slot, previous boot status and boot mode).
Upon retrieval of the vboot information, elog callback from ramstage
records the info into the eventlog.
Additionally, this patch refactors the existing event logging mechanism
to add newer APIs to record vboot firmware boot related information.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS and run below command to
check the cbmem log:
Scenario 1:
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot:
0x0 / 0x0
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot`
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Success`.
....
Scenario 2:
localhost ~ # crossystem recovery_request=1
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot`
VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Unknown`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add static check to ensure the reserved APOB DRAM space is the same size
as the MRC_CACHE region specified in the fmap.
Update sabrina APOB DRAM size to match the fmap.
TEST: Timeless builds identical. Test build with a larger MRC_CACHE than
APOB DRAM failed the assert as expected.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PCIe domain support for herobrine by enabling it in the devicetree.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This adds SPDX-License-Identifiers to all of the files in src/include
that are missing them or have unrecognized identifiers.
Files that were written specifically for coreboot and don't have license
information are licensed GPL-2.0-only, which is the license for the
overall coreboot project.
Files that were sourced from Linux are similarly GPL-2.0-only.
The cpu/power files were committed with source that was licensed as
GPL-2.0-or-later, so presumably that's the license for that entire
commit.
The final file, vbe.h gives a pointer to the BSD-2-Clause license
at opensource.org.
Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.
BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is required to enable PSP verstage on SoCs with recovery A/B
layout.
BUG=b:217414563
TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2
directory. Build and boot to OS in Skyrim with both PSP and x86
verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Update MrChromebox’ default branch from uefipayload_202107 to
uefipayload_202207.
This is based on upstream edk2, commit f26b70c (UefiPayloadPkg:
Add support for logging to CBMEM console).
Tested on:
* StarBook Mk V
* StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16a012485e4b4957439e776914ffd016b4506a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66083
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
SMMSTORE support in edk2 was not allowed in upstream edk2
as it was bootloader specific.
Shortly, it will be built from edk2-platforms and then,
it will be retired.
For now, the patches exist in the MrChromeBox fork (TIANOCORE_UEFIPAYLOAD), so enable
these by default when SMMSTORE_v2 is enabled.
Change-Id: I1861bf739c2e25f661b4f06a303348f0537dc8b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65867
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow passing custom build parameters to any version of edk2, not
just forks.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4eed535415ba15ae73e22cada9153820538f5f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Gang Chen