Apollo Lake uses yet another descriptor format where only two masters
are used: CPU/BIOS and CSE/TXE. CSE stores data in a region number 5
that has not been used previously and CPU must not write it. Add quirk
(-p aplk) that locks descriptor according to recommended values.
BUG=chrome-os-partner:58974
TEST=ifdtool -p aplk -l bios.bin; ifdtool -d bios.bin.new. Make sure
FLMSTR1 and FLMSTR2 are set correctly. unlock with -l and make sure
FLMSTRs are restored.
Change-Id: I3f33372bef3ff75d0e34030694c79cd07d5540de
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17202
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No boards left in the tree for this northbridge.
Change-Id: Id45da11b9d78cbd6bd50acb5a3c6c3c270f9020e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17281
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move old sockets to use romstage_legacy.c, these are ones
using intel/car/cache_as_ram.inc.
These will not be converted to RELOCATABLE_RAMSTAGE as boards
are candidates for getting dropped from the tree anyways.
Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure overcurrent pins for various usb ports.
Configure CdClock to 3.
Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17251
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for Kunimitsu board.
BUG=None
BRANCH=None
TEST=Built and booted on Kunimitsu boards. Verified these
updated DPTF settings with different workloads.
Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/350223
Reviewed-on: https://review.coreboot.org/17069
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for lars boards.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on lars DVT boards. Verified these
updated DPTF settings with different workloads.
Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/338877
Reviewed-on: https://review.coreboot.org/17068
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch updates below info,
[1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not
being used. Hence, removing unnecessary defines.
[2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0
external thermal sensor. These trip points are being used by _ACx
methods to control the fan speed on Skylake-U fan based Lars and
Kunimitsu platforms.
[3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip
points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to
control the fan speed as per the CPU temperature trip points.
[4] Newly added _ACx methods for thermal sensor TSR0 in this patch
has nothing to do with DPTF_CPU_ACTIVE_AC*.
We can control fan speed using various different thermal sensors.
In this patch, we have added new _ACx methods for TSR0 thermal sensor.
We run the fan at different speeds to cool down the system at different
TSR0 temperatures.
Similarly, we considered CPU sensor temperature values and ran the fan
at different speeds to cool down the system.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on kunimitsu and lars EVT boards.
Verified these _ACx methods with _ART table on these boards
with different workloads.
Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332368
Reviewed-on: https://review.coreboot.org/17067
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When reading+clearing a GPE for use as an interrupt we need to
re-read the status register and keep setting the clear bit until
it actually reads back clear. Also add a 1ms timeout in case the
status never clears.
This is needed if a device sends a longer interrupt pulse and it
is still asserted when the "ISR" goes to clear the status.
BUG=chrome-os-partner:59299
TEST=test cr50 TPM with 20us pulse to ensure it can successfully
communicate with the TPM and does not get confused due to seeing
interrupts that it should not.
Change-Id: I384f484a1728038d3a355586146deee089b22dd9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17212
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Increase the IRQ timeout to prevent issues if there is a delay
in the TPM responding to a command. Split the no-IRQ case out
so it doesn't suffer unnecessarily.
BUG=chrome-os-partner:59191
TEST=suspend/resume testing on eve board
Change-Id: I1ea7859bc7a056a450b2b0ee32153ae43ee8699f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17204
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add Stoney specific code subtree and fix Makefles and Kconfig files.
Author: Charles Marslett <charles@scarlettechnologies.com>
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit c3a469d11e4676b3b63d11a30955113291d00ec8)
Change-Id: Ic4d97a3745f7fc5a637ae6da17a9009b9757136e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17217
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00)
locate the HD audio controller on the northbridge root complex at 9.2
instead of the FCH. This duplicates the existing ASL into the northbridge
directories and reports the correct address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438)
Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17216
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add Stoney specific code subtree and fix Makefles and Kconfig files.
Original-Author: Charles Marslett <charles@scarlettechnologies.com>
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 51a187a3d08a425ef0cc141a7ddc49a70ac931b1)
Change-Id: I13c6b08c780e7bd2abd0fabbde1a89686132f65c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17196
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Make changes to the vendorcode files that allow them to work
with the binaryPI. This fixes various compile issues and
establishes a common calling convention between coreboot and
AGESA.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit f7ea2785d70bd6813b5b4d315b064802251d9557)
Change-Id: Ie36228476a9dbd7b83f95828ca9c7252cecd8ec8
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17195
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions. Change the license text and fix
up misc. whitespace.
This will facilitate the review of binaryPI changes in the
vendorcode directory.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)
Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Prepare for new 00670FF00 support.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit ca53cac5c847c55e56ad6f5feb382c04f33ae77a)
Change-Id: Ib48b1611bf70ec302c50f6e07bd2b3d9b09e0a24
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17193
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add acpigen_write_opregion that generates ACPI AML code for OperationRegion,
region name, region space, region length & region size are inputs.
Add acpigen_write_field that generates ACPI AML code for Field.
Operation region name & field list are inputs.
Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17113
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Adjust the names to match AMD's convention for family and model.
This patch is relevant for:
Trinity & Richland: Family 15h Models 00h-0Fh
Carrizo: Family 15h Models 60h-6Fh
Mullins & Steppe Eagle: Family 16h Models 30h-3Fh
Change-Id: I613b84ed438fb70269d789c9901f1928b5500757
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17169
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be
configured as native mode to use them for DMIC record
on other potential DMIC's.
DMIC blobs configure the clocks. For stereo & quad channel
record, both CLK_A1 and CLK_B1 are enabled.
For mono channel record, only CLK_A1 is enabled.
BUG=chrome-os-partner:56918
BRANCH=None
TEST=During DMIC record, check CLK_B1 and DATA_2 lines
Change-Id: I838009b85190de5360d593238e48c9593c1dc43a
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.
Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/17181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
SATA device remains unrecognized if connected at Port 2.
Port control and Status register (PCS) is by default set by
hardware to the disabled state as a result of an initial
power on reset. OS read PCS register during boot causes
disabling of SATA ports and can't detect any devices.
BRANCH=none
BUG=chrome-os-partner:59335
TEST=Build and boot SKL from SATA device connected at Port 2.
Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When Chrome EC is disabled, vboot hash is not available during S3 resume
Hence disable vboot verification when Chrome EC is not available.
Change-Id: I665f5f0e2e53da7b735de30443d323572d8a1a9c
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17246
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Avoid use of Local0 variable in TEVT acpi method.
If mainboard doesn't expose any thermal sensor, then warning is
generated for variable Local0 not been used.
Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17245
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add device id for PCH-Y used in Kaby Lake RVP3 board.
Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17244
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.
TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
payload. It worked as much as before (Linux didn't boot, but it
made some successful SBI calls)
Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Ron's code calculated the DLL and DLM registers of the 8250 UART, but
that's the job of the UART driver. uart_input_clock_divider isn't needed
anymore because the default value of 16 works.
As a bonus, the baud rate can now be selected in Kconfig, instead of
being hardcoded at 115200.
TEST=Booted the board at 9600 and 115200 baud.
Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17188
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Log when the MRC cache is attempted to be updated with status
of success or failure. Just one slot is supported currently
which is deemed 'normal'. This is because there are more slots
anticipated in the future.
BUG=chrome-os-partner:59395
Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17231
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Some events were added in other places, but coreboot's
elog namespace wasn't updated. As such there's a collision
with the thermtrip event. This change at least updates the
elog information to reflect potential event type uage.
BUG=chrome-os-partner:59395
Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17230
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
If selected, libgnat will be linked into ramstage. And, to support Ada
package intializations, we have to call ramstage_adainit().
Change-Id: I11417db21f16bf3007739a097d63fd592344bce3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16944
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17215
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17214
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
1. Update gpio.h to set proper pad config for Kaby Lake RVP3.
2. Set spd index to zero.
3. Remove nhlt specific init.
Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
There are two configs, sdram-lpddr3-hynix-2GB.inc and
sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14.
Changing .ddrconfig from 14 to 3 improves performance
especially on contiguous memory accesses. Comparing the .ddrconfig:
- if .ddrconfig = 3,
C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C---
- if .ddrconfig = 14,
C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C---
where
- R: indicates Row bits
- B: indicates Bank bits
- C: indicates Column bits
- D: indicates Chip selects bits
.ddrconfig = 3 has multiple banks switching which improves DDR timing.
BUG=chrome-os-partner:57321
TEST=Boot from fievel and play video
BRANCH=veyron
Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e
Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/404691
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix msch ddrconfig register write error. Also make sure that the row
number configured in msch is equal to the row number configured in the
DDR controller.
This would not affect systems with 4GB of memory, but is needed
for 2GB configurations.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de
Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/399563
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17208
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This was a dummy implementation until now which returned -1 always. Add
support for reading SPI flash status register (srp0).
BUG=chrome-os-partner:59267
BRANCH=None
TEST=Verified by enabling and disabling write-protect on reef that the
value of SRP0 changes accordingly in status register read.
Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
String format required two arguments however those
were packaged in ( , ) so the left one was ignored.
Change-Id: I59698319d5ff4215f296356147b4e22229cc9245
Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io>
Reviewed-on: https://review.coreboot.org/17118
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
After I did a new toolchain build, I found the
the mhartid register value is wrong for Spike.
The docs seem to agree with Spike, not the
code the toolchain produces?
Until such time as the bitstreams and toolchain can find
a way to agree, just hardcode it. We've been playing this game
for two years now so this is hardly a new approach.
This is intentionally ugly because we really need the
toolchains and emulators and bitstreams to sync up,
and that's not happening yet. Lowrisc
allegedly implements the v1.9 spec but it's PTEs are clearly
1.7. Once it all settles down we can just use constants
supplied by the toolchain.
I hope the syncup will have happened by the workshop in November.
This gets spike running again.
Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The Stoney processor can use multiple directory structures. Turn
this feature on in the makefile.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e)
Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17149
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Andrey Petrov