For the 1st redesign of mc_apl1 mainboard some adjustments are
necessary:
- The FPGA is now connected directly via a PCIe Root Port
- Internal Apollo Lake UARTs are now used
- Adjusting GPIO settings
Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
A FPGA is not necessarily available in further mc_apl1 variants. So we
move the loading of the driver and the notify function to the mc_apl1
variant.
Setting the CPU to Max Non-Turbo Ratio is also not absolutely necessary
for further variants.
Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This supports the Foxconn d41s, d42s, d51s, d52s.
The following is tested (SeaBIOS 1.12 + Linux 4.9) and works:
- COM1
- S3 resume (with SeaBIOS needs sercon disabled)
- Native graphic init on VGA output
- SATA
- USB
- Ethernet
- PS2 keyboard
The base for this mainboard port was the Intel D510MO port.
Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28227
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This open-codes flash_cmd, but until the API is fixed for real, it uses
xfer's existing scatter-gather ability to write command and data in one
go.
BUG=chromium:446201
TEST=emerge-coral coreboot succeeds
Change-Id: Ic81b7c9f7e0f2647e59b81d61abd68d36051e578
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Writes to VGA MEM and IO by NGI are invalid if the IGD is not decoding
them.
Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since ifdfake has been deprecated in favor of better alternatives, such
as flashrom IFD parsing. Therefore, there is no need to support ifdfake
any further. Remove the IFD_*_REGION values on the few motherboards with
them.
Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28232
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's a small window of opportunity when CPU is already in SMM but has
not yet entered S3 for a wake event to happen, which would cause a failed
S3 entry. Check for pending events at the very last moment possible, and
if there are pending wake events report them.
BUG=b:111100312
TEST=build and boot grunt.
Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For debug reasons, sometimes you not only want to log an event, but also
some extra information that would help debugging. Create an extended event
reporting event type with a dword complement, and define extended events
for failing to enter S3 due to pending wake event (one for pm1 and one for
gpe0).
BUG=b:111100312
TEST=Add a fake pending wake event, build and boot grunt, see the event in
eventlog.txt.
Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Because the Kconfig configuration files for primary payloads are
already sourced via a wildcard pattern this change requires to
use another file name pattern.
Change-Id: I83b89f5e14618e8a487ebb044fcdd3c175662591
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy code of depthcharge boot/coreboot.c and adapt it.
Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable
and prints the log.
Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in
text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy
Bridge".
Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There's nothing Sandy Bridge specific in this code.
Make it available on all platforms to reduce code duplication.
Tested on Lenovo T430: SMBIOS entry 17 is still valid.
Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Fix ACPI resume path compilation for TPM ramstage
driver
* Move enabling of the TPM prior activation and remove
reboot return status from TPM enable.
More information can be found via the TCG
specification v1.2
Tested=Elgon
Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28085
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no public datasheet available for this SuperIO so the resources are
guessed by looking at other ITE SuperIO's and the register dumps while running
vendor firmware.
The only board with this SuperIO in the tree is the asus m5a88-v. Most of the
devicetree entries would have been invalid here so one should not worry too much
about regressions.
Tested with Foxconn d41s.
Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This should not be board specific.
Change-Id: Ifa617e84af767f33a94f1ddfa7d4883c1a45198f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When doing the receive enable training, the final mapping of the ranks is
already done, so we can be sure that that address 0x00000000 there will always
be a rank.
Change-Id: I7ac017a8816fc9a47cef0695826a1c32f699f6f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
With this the time spend during the raminit decreases from ~480ms to ~126ms.
Change-Id: Ic23f39f1017010c89795e626f6a6f918f8bda17a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some OS certification test (for example Windows) will fail if there
are unsupported sleep states. Since these states are not really used
today, we can remove them from ACPI table.
BRANCH=eve
BUG=b:72197653
TEST=certification system sleep test pass.
Change-Id: I5f5122cac1bf61f7c580afb18cc66b5ff07286fb
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1065401
Commit-Queue: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/28080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These
functions are used by PspBaseLib. Remove all functions that are not used,
directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite().
BUG=b:112688270
TEST=Build grunt
Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28194
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This small change is required for the successful loading of microcode
from F15TnMicrocodePatch0600110F_Enc.c for the Richland RL-A1 CPUs,
such as A10-5750M found at coreboot-supported Lenovo G505S laptop.
Richland RL-A1 and Trinity TN-A1 CPUs are using the same microcode,
so the Richland RL-A1 IDs should be added to this equivalence table.
Function `GetPatchEquivalentId()` in
`src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c`
goes through the equivalence table like below.
for (i = 0; i < (EquivalencyEntries * 2); i += 2) {
// check for equivalence
if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) {
*ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1];
return (TRUE);
}
}
Change-Id: I7a68f2fef74fb4c578c47645f727a9ed45526f69
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28204
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: <awokd@danwin1210.me>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change PL1 from 4.5W to 7W, based on thermal test results.
BRANCH=eve
BUG=b:73133864
TEST=Verify the MSR PL1 limitation is set to 7W.
Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28078
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In legacy mode, DPTF on some systems may rely on MMIO to control PL1
settings. However, MSR PL1 also contributes to the decision of max
PL1 power; and in the current design, the lower value takes effect.
In order to align MMIO and MSR settings, a tdp_pl1_override option is
added to override the MSR PL1 limitation.
BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
2. Verify the MSR PL1 limitation is set correctly.
Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There were so many pitfalls that I wrote my own version of this even-
tually. This version is inspired by the procedure of Alex Thiessen[1].
Instead of generating a `build.h` on demand, we always generate a tem-
porary version that, if it differs from the current one, is added as
a dependency.
As we use .SECONDEXPANSION on the prerequisites, special care is taken
that we won't generate the file twice. As it would be too late to add
the dependency if we'd run `genbuild_h.sh` inside a recipe, we have
to run it through the `$(shell)` function. But that brings us to the
next issue: The make variables used by `genbuild_h.sh` are not expor-
ted to this shell like they would be in a recipe. So we export them
manually. We could also make these variables explicit parameters of
`genbuild_h.sh` instead.
An alternative to always creating the temporary `build.h` would be
to add a phony target as dependency instead, and finally calling
`genbuild_h.sh` again in case we need an update. But, um, we create
so many files anyway...
[1] https://review.coreboot.org/25685
Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC).
Linux has a driver that enables features like speed shift without
consulting ACPI. Other OSes instead rely on this information and need a
_CPC present. Prior to this change performance in Win10 never exceeds
80% and MSR 0x770 is 0, while with this change (and enabling eist) higher
speeds can be achieved and the MSR value is now 1.
Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds a method to init a cppc_config structure in a way that
should ideally work across Intel processors that support EIST.
Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.
BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.
Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is meant to solve an issue where the proximity sensor may fluctuate
between CLOSE / FAR in rapid succession upon the user removing their hand
from the unit, before settling on the correct output.
Using the hardware debouncing filter solves this issue and removes the
spurious fluctuations.
BRANCH=None
BUG=None
TEST=manual on Nocturne, observing events come in
Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/28112
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are two SKUs of Whiskey Lake W0, 2-core and 4-core.
Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures
USB-C as device mode. Force USB-C into host mode.
BUG=b:111623911
TEST=Verified that USB-C being host mode once USB OTG is set.
Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
`superiotool` follows its own style (e.g. lot's of missing spaces
and odd placement of braces in the register descriptions).
Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28214
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Callers should have a default ready and get noticed by the return
value of get_option(). No need to scare log readers at this location.
Change-Id: Ied373d8a02afdc8d1017c9f41d9004e3797dfbb3
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DIMM type read from SPD needs to be converted to make sure SMBIOS fills
in the correct formfactor.
Tested on Lenovo T430: The Form Factor no longer reads as unknown.
Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Fill in SMBIOS type 17 DIMM serial number, read from SPD.
Fixes FWTS SMBIOS type 17 test.
Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
src/soc/intel/common/block/cpu/mp_init.c
Function init_cpus: Pointer dev checked for NULL may be
dereferenced.
src/soc/intel/common/block/graphics/graphics.c
Function graphics_get_bar: Pointer dev returned from
call may be NULL and will be dereferenced.
BRANCH=None
TEST=Built & booted Yorp board.
Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Mario Scheithauer