CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.
1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console
BUG=chrome-os-partner:54342
Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0. Move esraminit from
romstage into the bootblock. Replace cache_as_ram with
car_stage_entry.S and code in romstage.c
TEST=Build and run on Galileo Gen2
Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC
value as a uint64_t value.
TEST=Build for amenia and Galileo Gen2
Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15124
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
If a bridge has the primary bus equal to the secondary bus the
busmaster_disable_on_bus() will infinitely call itself. Avoid the
inifinite recursion by checking current bus number against the
secondary bus number.
BUG=chrome-os-partner:54262
TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx
signals which means no more infinite recursion.
Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15157
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Like other boards there will likely be information needed from
GNVS in the SMM handler. Therefore, it's important that the point
is stashed accordingly.
BUG=chrome-os-partner:54275
TEST=Noted GNVS messages from SMM console on reef.
Change-Id: If12b69731330a1e0af7f8fe880635e5ffd02d715
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15152
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The UART support is needed in SMM in order for DEBUG_SMI to
function.
BUG=chrome-os-partner:54262
TEST=Ran on reef with DEBUG_SMI enabled. Can observed SMI messages.
Change-Id: Ibd6b12e27d5776046b400adf72f24133b9e54af8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15151
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
It appears that PM1 is not wired up to the SMI status register, but
it does definitely cause SMIs to trigger. Therefore, provide a fake
PM1 status bit by checking the power button status when SMI status
is indicating no status as well as the PM1 control indicating that
SCI mode is not enabled.
BUG=chrome-os-partner:54262
TEST=Smashed power button on reef to cause SMI in firmware. No longer
loops infinitely with constant SMIs firing.
Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15155
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide the bit definitions for the SMI status register. Also,
utilize them which means deleting some of the handlers that can't
exist because there are no status bits.
BUG=chrome-os-partner:54262
Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15154
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Due to USB LDO issue in current steppings, cold reboot needs to be
temporarily disabled. Thus, hard_reset call should be the same as
soft_reset.
Once future steppings are available INTEL_COMMON_RESET can be enabled again.
Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15143
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 5ede3d8cce.
No longer needed due to FSP being updated, with the 139_40 release,
to accept StackBase field
BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted with FSP 139_40
Change-Id: Ic832d8dc4ca87631f5fef80d4d41558d9a72630a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15068
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs
with the 139_40 release. In order to successfully pass through
memory/silicon init the header files must be updated to the latest
versions
BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted
Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15066
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
that are present on the Skylake-LP PCH with a 120 mHz clock. The
required lpss_i2c_base_address() method is implemented separately for
verstage/romstage and ramstage environments.
This provides methods to convert to and from "struct device" and the
I2C controller bus number for that device. These are used to provide
support for the "I2C Bus Operations" that are present in the coreboot
devicetree.
To support the I2C controller before ramstage an early init function
is provided to do minimal initializaiton of the PCI device and assign
a temporary base address for use before memory. The final base
address is assigned during device enumeration and used during ramstage.
Because it is usually not necessary to enable I2C controllers before
ramstage a config register for the devicetree is provided to perform
early initialization of this controller. In addition the bus speed
can be set in the devicetree and that speed will be applied when the
device is initialized. If not provided the default speed is set to
I2C_SPEED_FAST.
This was tested with the google/chell mainboard by reading and writing
from the trackpad and codec devices during both verstage and ramstage.
Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15105
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.
This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.
The affected mainboards are updated in this commit so it will build.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Reviewed-on: https://review.coreboot.org/15104
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V. This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.
This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.
This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a function similar to broadwell to set the PRR for a region of
flash and protect it from writes. This is used to secure the MRC
cache region if the SPI is write protected.
BUG=chrome-os-partner:54003
BRANCH=glados
TEST=boot on chell, verify PRR register is set and that the
MRC cache region cannot be written if the SPI is write protected.
Change-Id: I925ec9ce186f7adac327bca9c96255325b7f54ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: abb6f645f5ceef3f52bb7afd2632212ea916ff8d
Original-Change-Id: I2f90556a217b35b7c93645e41a1fcfe8070c53da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349274
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-on: https://review.coreboot.org/15102
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
DesignWare I2C block and have a similar configuration of that block.
This driver is ported from the Chromium depthcharge project where it
was ported from U-Boot originally, though it looks very different now.
From depthcharge it has been modified to fit into the coreboot I2C
driver model with platform_i2c_transfer() and use coreboot semantics
throughout including the stopwatch API for timeouts.
In order for this shared driver to work the SOC must:
1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
speed that the I2C controller core is running at.
2) Define the lpss_i2c_base_address() function to return the base
address for the specified bus. This could be either done by looking
up the PCI device or a static table if the controllers are not PCI
devices and just have a static base address.
The driver is usable in verstage/romstage/ramstage, though it does
require early initialization of the controller to set a temporary base
address if it is used outside of ramstage.
This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
ramstage environments by reading and writing both single bytes across
multiple segments as well as large blocks of data at once and with
different configured bus speeds.
While it does need specific configuration for each SOC this driver
should be able to work on all Intel SOCs currently in src/soc/intel.
Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15101
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.
TEST=Build and run on Galileo Gen2
Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the spelling of *firmware* in a comment.
Change-Id: I44bcd95f754ff839d582dc2150e1883a6315da9e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/15078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE
in low power state
Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15054
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because the resource for the ACPI BAR is fixed, pci_dev_set_resources
does not store it to the device. This means we need to do part of the
dance to get the ACPI IO region to work after coreboot.
Of course, this BAR can be destroyed later by the OS probing it, but
at least we try to get it working out of coreboot.
Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/15048
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
i2c_init() leaves the I2C device enabled. Combined with the default
interrupt mask (0x8ff) and the fact that the interrupt line is shared,
this leads to an interrupt storm in the OS until a proper I2C driver
is loaded.
This change clears the interrupt mask to prevent the interrupt storm.
Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/15047
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
TSEG register comes out of reset with a non-zero default value. This
causes issues when cbmem_top returns non-zero value based on TSEG read
before DRAM is initialized. Thus, clear TSEG reg early in bootblock to
avoid unwanted side-effects.
Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15049
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Verstage on apollolake requires the functions defined in car.c to
perform flush of l1d to l2 on loading romstage into CAR.
Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15046
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.
BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On apollolake, the boot media layout is different in that the traditional
"BIOS" region contains another data structure with the boot assets such
as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name
a few. This region is referred to as the IFWI. Add support for writing
the IFWI to a specified FMAP region to accommodate such platforms.
Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14999
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.
TEST=None
Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15010
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Move UART initialization into romstage.c and eliminate uart.c.
TEST=Build and run on Galileo Gen2
Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15009
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Split out the I2C code to allow I2C transactions during early romstage.
TEST=Build and run on Galileo Gen2
Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15007
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Set a temporary I2C base address during romstage.
TEST=Build and run on Galileo Gen2
Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Only define BIT names if they are not already defined.
TEST=Build and run on Galileo Gen2
Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove extra ": " following reigster type.
TEST=Build and run on Galileo Gen2
Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Migrate the clearing of the SMI interrupts and wake events from FSP into
coreboot.
TEST=Build and run on Galileo Gen2
Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14945
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Rename the file pmc.c to lpc.c to prepare for further additions.
TEST=Build and run on Galileo Gen2
Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.
Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MMIO region of 256 KiB under 4 GiB is not decoded by SPI controller
by hardware design. Current code incorrectly specifies size of that
region to be 128 KiB. This change corrects the value to 256 KiB.
Change-Id: Idcc67eb3565b800d835e75c0b765dd49d1656938
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14979
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a PCI driver for the skylake SD card device and have it generate
an entry in the SSDT for the card detect GPIO if it is provided by the
mainboard in devicetree.
This sets up a card detect GPIO configuration that will trigger an
interrupt on both edges with a 100ms debounce timeout and can wake the
SD controller from D3 state.
The GpioInt() entry is bound to the "cd-gpio" device property which will
be consumed by the kernel driver.
The resulting ACPI output in the SSDT will be combined with the SDXC
device declaration in the DSDT.
Example:
Scope (\_SB.PCI0.SDXC)
{
Name (_CRS, ResourceTemplate () {
GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 35 }
})
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "cd-gpio", Package () { \_SB.PCI0.SDXC, 0, 0, 1 } }
}
})
}
Change-Id: Ie4c1bfadd962cf55a987edb9ef86e92174205770
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14995
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Minor cleanups in pci_devs.h for indentation and newlines to be
consistent throughout the file.
Change-Id: I522df141a6b33d918cfb3de1b9019c0c4a73e3e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14994
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the Audio DSP device for skylake as a PCI driver with a static
scan_bus handler so generic devices can be declared under it.
This is for devices like the Maxim 98357A which is connected on the
I2S bus for data but has no control channel bus and instead just has
a GPIO for channel selection and power down control and needs to
describe that GPIO connection to the OS via ACPI.
Change-Id: Iae02132ff9c510562483108ab280323f78873afd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the I2C devices to skylake with the scan_bus handler for SMBUS
devices so that I2C-based devices can be declared in devicetree.cb
and get initialized properly during ramstage.
This does not yet provide the I2C driver, but it allows for devices
that are declared in devicetree.cb to provide ACPI tables to the OS.
Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the GPE header file to skylake chip.h so the SOC-defined macros
for the various GPE values can be used in devicetree directly.
For example:
chip drivers/i2c/touchpad
register "wake" = "GPE0_DW0_05"
device i2c 15.0 on end
end
Change-Id: Ic322108561b34aa34a24a4daba6ba7a4f7a3f9a4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14991
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Depending on which options are selected there needs to be certain
functions supplied. However, the spi, mmap_boot, and tsc_freq modules
were not included in the SMM builds. Fix the omission.
Change-Id: I25ab42886cfd46770ce0f4beee65f2f4d15649f3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14977
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
