At present coreboot_rsdp remains unset for QEMU, which results in
an incomplete LB_TAG_ACPI_RSDP coreboot table generated.
Fix this by assigning coreboot_rsdp properly.
TEST=Build coreboot for QEMU x86 i440fx (default) with U-Boot x86
as the payload, boot coreboot.rom with QEMU, and run 'acpi list'
from U-Boot shell to show the ACPI tables.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Change-Id: I5bc3f0528d4431fd388ca52b8865f9be0e1faf92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
For the sequenced controlled shutdown path, there's a 10ms delay
after the PEXVDD rail is disabled to permit discharge needed on
Agah/Proxima.
This can be dropped to 3ms for Hades designs Proto0 and forward.
Once Agah board is dropped, "if CONFIG" can be cleaned up/removed.
BUG=b:271167335
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I8a0d62ec76caff861adce2d6c0ba2d4e4064affa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75051
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78 ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ia8b7f997ca6234add569da751e1070144790e258
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
An underscore has crept into the mainboard model option for mc_ehl3 and
mc_ehl4 by mistake. This patch fixes the incorrect entry.
Change-Id: Ie59619877fb6341a5bbfe91c13e7692943480ad0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75040
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
- VBT information: The link from 01.org is dead, but appears to have
been identical to the i915 page in the Linux kernel docs based on
snapshots on archive.org.
- Cgit: coreboot no longer has cgit running for the repos it hosts,
and these links redirect to the Gitiles list of repos hosted on
review.coreboot.org. Based on snapshots on archive.org, these used
to link to the individual repo or tree. Replace these with an
equivalent Gitiles link.
Change-Id: Id0bfee7b806c851fbe1dcf357e14d9b593e8569a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
If the ME is disabled with the `me_state` CMOS setting, boot
times are approximately 5 seconds longer:
942:before sending EOP to ME 1,240,773 (5,599)
943:after sending EOP to ME 6,263,951 (5,023,177)
Total Time: 6,167,443
This is because the current code only checks if the ME is
disabled for CSE LITE SKUs. With this patch, boot times are
approximately 5 seconds quicker:
Total Time: 1,143,932
Tested on `starbook/adl` and `starbook/tgl`.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Update header files for FSP for Meteor Lake platform to version 3165_81, previous version being 3084_85.
FSPM:
1. Change UPD name from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage'
2. Change UPD name from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage'
3. Change UPD name from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage'
4. Address offset changes
FSPS:
1. Remove deprecated UPD 'PcieDpc'
2. Address offset changes
BUG=b:280005256
TEST=Able to build and boot google/rex to ChromeOS.
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This fixes an issue where pcie was not power gating and blocked
S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance
values to 15.73ms as stated in doc #729123 - MTL External Design
Specification.
BUG=none
TEST=Boot google/rex, print/check values.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on feedback and experiences from new coreboot users, it isn't
clear that Tutorial 1 is mainly intended to set up the toolchain and
will not produce a bootable ROM for their board. Thus, add a note
explicitly mentioning this with a short explanation.
The process of manually building and adding the payload is also unusual,
since payloads are usually handled automatically by the build system.
This adds a note in the summary to provide an explanation of this.
The savedefconfig output is also outdated, as Kconfig now outputs
additional lines (even though many of those are the same as the
defaults). This has caused confusion, leading users to think that they
may have configured coreboot incorrectly. Update this to the current
defconfig contents and add a note that this may change depending on the
coreboot version.
Change-Id: I13206aa05a425ddfe33ee35feff0db490585a59f
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73816
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Linux kernel recently updated the wording of their sign-off
procedure, changing the ambiguous "real name" requirement to "a known
identity" and dropping "no pseudonyms". Anonymous contributions remain
uncommittable [1]. As discussed in the April 19, 2023 leadership
meeting, update our policy to go along with Linux and flashrom (who also
updated their policy).
[1] Linux kernel commit d4563201f3
(Documentation: simplify and clarify DCO contribution example language)
Change-Id: Ie676334f7c1509524adcb8dbb78495fb4da35ede
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, this only exists on the old wiki and the developers.html page
on coreboot.org, but it really ought to be somewhere in the new docs
alongside the other contribution guidelines. This was largely copied
from the text from the developers.html page.
Change-Id: If50b3827ab36234719f9a90239caec4612eb6762
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74825
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The Intel SoC Meteor Lake requires a higher pcie max non-snoop and
snoop latency tolerance. Add config to let SoC overwrite the common
code settings if needed.
BUG=none
TEST=Boot google/rex and print/check if able to overwrite values.
Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Intel's EHL FSP offers the possibility to select the connected hard
drive type to SATA ports. One has the option to choose between HDD ('0'
- default) and SSD ('1').
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Processing LD flags is done without most warnings enabled, which is why
this never caused problems.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic9d82c1426a1c1d2f21c8e7560685cf9d7106a88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75033
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Selects should be done in the Kconfig file instead of Kconfig.name.
Change-Id: I2ae03a3ac548674b8c5e7dfaff47d6c536b452f1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75013
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Assigning duty_offset while duty_width==0 has no purpose.
Under intel/common/block, previous assignment for fadt->gpe0_blk
resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns
value matching pmbase + 0x60.
Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The STA_HIMAX83102_J02 and STA_ILI9882T panel will be used for Starmie,
enable these two panels config for it.
BUG=b:272425116
BRANCH=corsola
TEST=build starmie and check the cbfs include the panels
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I1dd696dd6a84d9606e4b9a2d4884dd70a6df9161
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74200
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add STA_ILI9882T panel serializable data to CBFS.
The panel datasheet: ILI9882T_Datasheet_20220428.pdf
BUG=b:275470328
BRANCH=corsola
TEST=build and check the CBFS include the panel
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ia7a37c0659f0959fe7be01aba0f08d63119d139f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Configure the CMOS bank I/O base addresses with
PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The
defaults remain the same.
Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CMOS defaults greater than 128 bytes long will extend to bank 1.
Change-Id: I9ee8364d01dd8520be101de3f83d2302d50c7283
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
FSP-M is normally memmapped and then decompressed. The SPI DMA
controller can actually read faster than mmap. So by reading the
contents into a buffer and then decompressing we reduce boot time.
It is interesting that FSP-M takes an additional 8ms to execute. I
suspect since we call it 50ms earlier it's having to wait for one of
its dependencies.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
| 970 - loading FSP-M | 0.316 | 0.997 Δ( 0.68, 0.05%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.026 | 13.874 Δ( 13.85, 0.96%) |
| 18 - finished LZ4 decompress (ignore for x86) | 64.361 | 0.337 Δ(-64.02, -4.43%) |
| 2 - before RAM initialization | 0.534 | 0.529 Δ( -0.01, -0.00%) |
| 950 - calling FspMemoryInit | 1.455 | 1.132 Δ( -0.32, -0.02%) |
| 951 - returning from FspMemoryInit | 207.695 | 216.537 Δ( 8.84, 0.61%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I850b1576501753a355e7b23745e04802a0560387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Librem Mini v1/v2 has an automatic power-on setting provided by the EC
in BRAM bank 1. Use this bank as the high bank of CMOS memory so that
setting can be described in cmos.layout.
Change-Id: Icb87bc521f71aa4350c8f5a64fc2cbe7a7a8c808
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Beware that there's no XHCI2 controller and the USB4 controller device
pointers were added right after the xhci_0 and xhci_1 controller device
pointers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74658
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Introduce acpigen_write_BBN to generate the ACPI method object that
returns the base bus number for a PCI(e) host bridge. When called, the
base_bus_number argument must be the first PCI bus number that got
assigned to the corresponding host bridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Add STA_HIMAX83102_J02 panel serializable data to CBFS.
The panel datasheet: HX83102-J02_Datasheet_v03.pdf.
BUG=b:272425116
BRANCH=corsola
TEST=build and check the CBFS include the panel
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I382bdc89e5a217fd1c28e677938f454dc09725cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
There are 2 regex patterns defined to process the lines from *fw.cfg:
1) for lines with mandatory entries
2) for lines with mandatory + optional entries
Consolidate the regex pattern. Add enums for matching regex caller
groups so that the human readable group IDs can be used instead of magic
numbers.
BUG=None
TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush
BIOS image which have both mandatory and optional entries. Confirm that
the amdfw.rom built before and after this change have matching SHA in
both Skyrim and Guybrush images. This ensures that the optional level
entries in Guybrush are handled as expected. Boot to OS in Skyrim.
Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add FW_CONFIG item for FP sensor init and conditionally init
the GPIOs based on whether we're using a SPI or UART FP sensor.
BUG=b:276939271
TEST=builds
Change-Id: I9815bd17df1d15f73529beb15d08cde1ef90efad
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add FW_CONFIG item for eMMC/NVMe support and address the init
of the lanes based on said config.
BUG=b:278877257
TEST=builds
Change-Id: Id6452f497cf78549b7d6126f1b55cd6d45b403c3
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74957
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Mark Hasemeyer <markhas@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
For early Sign of Life to work, we may need certain pin configurations
very early in boot (e.g. HDMI). This may happen before romstage GPIOs
are configured, and bootblock is not suitable for field upgrading
existing devices. Add a separate GPIO table that can be configured
when early graphics is invoked.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=Builds and SoL functions on HDMI enabled variants
Change-Id: I7b3ce96a4166451e72aa70b3086eff3fb8b082b7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Allow different gma-mainboards configs for different baseboards
as they support varying display interfaces. Set Brya to eDP only
and Brask to HDMI only.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=Builds and SoL functions on both brya and brask varaints
Change-Id: Iaf3f35b009d53e50723e4aa82c0f4932783f9bb9
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add _PLD support to GFX device so that each display output can store
its physical location of connection point. This is to be used primarily
for describing DP on USB-C ports in the future patches.
The upstream Linux kernel now has a feature to compare _PLD of Type C
connectors and DP connectors to link them together.
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=c5c51b2420625faa1f0e363f21dba1de53806ff7
This feature allows us to tell which display output is used by which
USB-C port.
So, for the future boards, we want to add _PLD for each DP connector
matching with the corresponding USB-C port.
BUG=b:277629750
TEST=emerge-${BOARD} coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I393207746a9e82c1fd7622ab3661d7b1232cb62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds some of the variety of configuration options exported
by the Pericom Inc. PI7C9X2G608GP PCIe switch over its SMBus interface.
Currently implemented options are only used to adjust the switch
upstream port amplitude and de-emphasis levels in millivolts. Only
values specified in the switch datasheet (in tables 6-6 and 6-8) are
allowed.
Example of a devicetree.cb entry:
chip drivers/i2c/pi608gp
register "gen2_3p5_enable" = "true"
register "gen2_3p5_amp" = "AMP_LVL_MV(425)"
register "gen2_3p5_deemph" = \
"DEEMPH_LVL_MV(37, 5)"
device i2c 0x6f on
ops pi608gp_ops
end
end
Link to the datasheet:
https://web.archive.org/web/20210225074853/https://www.diodes.com/assets/Datasheets/PI7C9X2G608GP.pdf
BUG=none
TEST=Create devicetree.cb and Kconfig entries for this driver
in a mainboard containing the switch and verify, that the values read
out from the switch config space match the values programmed over the
SMBus.
Change-Id: Id191c4e97b99da58efd3ba38bf8cca3603ece4d5
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Update devicetree to support G7500 touchscreen.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot and check touchscreen function
Change-Id: I3b63b1bb45275ad7eef8799dcff27f264739c258
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d71928 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
back from Stoneyridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e724292431be7f7c2a0b6678b426831e3c19154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74990
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d71928 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
forward from Stoneyridge to the newer AMD SoCs.
TEST=On Mandolin the PCI Express Root Complex now shows up in the device
manager on Windows 10 and when switching the view to 'devices by
connection', all PCI(e) devices are shown below it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bin Meng