This pin has been removed from recent revisions (or at least moved to a
pin that's not controlled like a normal GPIO). It has also never been
used on older ones (I think?). The same GPIO is now used as a SKU ID
pin, so make sure we're not incorrectly configuring it as an output
(although sku_id() overrides that later anyway, but it's still
incorrect).
BUG=b:160754995
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb
domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.
BUG=b:157580724
TEST=Boot zork, usb functional
Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no reason to create a named variable. We can just return the
package.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The ACPI specification, version 2.0 says:
_BFS is an optional control method.
So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.
Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Morphius cannot support 100Mhz fast SPI causing it to not boot.
Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe.
BUG=b:161233767
TEST=Boot morphius
Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add USB ports, USB user-facing camera and USB bluetooth to devicetree.
USB ports 4 and 5 are duplicated for picasso and dali.
BUG=b:158096224
TEST=Boot Trembyle and Dalboz, Dump acpi tables
Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split zork baseboard devicetree between dalboz and trembyle.
The devicetree is simply duplicated, no other changes in this commit.
BUG=b:158096224
TEST=Build coreboot for zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Screen flickered on VT2 on some devices after idle a period of time.
Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.
Because CB:38212 (commit eae254e) caused this issue.
BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered
Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.
BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.
Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Configure volteer2 and delbin, the two variants currently using
preQS or QS silicon, to use CSE Lite.
BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.
Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi
power enable") added helper functions for determining if a board uses
v3 schematics. However, it introduced a regression by adding a wrong
check for variant_uses_v3_schematics() in variant_audio_update(). This
change fixes the check to ensure that dmic_gpio is updated when
variant is not using v3 schematics.
BUG=b:161141258,b:161128964
TEST=Verified on trembyle that trackpad works again (it was broken
because of the regression).
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the woomax variant of the zork reference board by copying
the template(coreboot-zork/util/mainboard/google/trembyle)
files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2.
“1-2-2" means command, address and data are transmitted
through 1 wire, 2 wire and 2 wire, respectively.
BUG=b:160603142
TEST=Boot on trembyle, verify register settings.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.
Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For variants with slightly different GPIO configuration, add support to
pass an override GPIO configuration table.
BUG=None
TEST=Build and boot the waddledee mainboard.
Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
And use it instead of directly writing to the MRC struct.
Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Check the PCH's LPC device ID to know the system type instead of relying
on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This Kconfig symbol allows doubling the memory's refresh rate, assuming
that the MRC actually cares about it. It is disabled by default except
on the mainboards which explicitly enabled this setting in `pei_data`.
Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Several of these includes are no longer necessary. Get rid of them.
Since "raminit.h" already includes "pei_data.h", we can omit including
the latter for brevity's sake.
Change-Id: Ia7e9dadf87114ca9ea4761b89909ea035cdfc38a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43121
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All mainboards have a non-zero SPD address to implemented DIMM slots.
Knowing this, it is possible to compute the MRC slot population masks
automatically instead of hardcoding the values on each mainboard.
Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide,
so do not use 32-bit operations to program them.
Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so
using 32-bit operations on them is correct.
Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
It only contains a pointer to another struct. Flatten it.
Change-Id: Iab427592c332646e032a768719fc380c5794086b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Instead of using function pointers, we can use weak functions. So, drop
the pointer from `romstage_params`, leaving `pei_data` as the only
remaining member. This will be cleaned up in a follow-up commit.
Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=b:160711124
TEST="FW_NAME=ripto emerge-volteer coreboot chromeos-bootimage"
and verify that the build does not fail.
Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Zork devices shut down the i2c controllers in S3 to save power. On
resume, they need to be enabled in verstage before being accessed or
the system hangs.
BUG=b:160834101
TEST=Resume works with psp_verstage.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43334
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This simplifies things and makes type checking possible.
Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Instead of passing around a pointer to an array, just write the relevant
registers directly. Note that intel/baskingridge used spaces to indent
line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
