Commit Graph

38949 Commits

Author SHA1 Message Date
Marc Jones a81703c37b soc/intel/common/block/acpi: Make calculate_power() global
Change static calculate_power() function to global and update the name
to common_calculate_power_ratio() for SOC ACPI code use.

Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-21 02:32:44 +00:00
Michael Niewöhner 1aa8fc3cef drivers/intel/fsp2_0: recreate FSP targets on config change
When a different FSP binary was chosen in menuconfig, the split fd files
do not get updated. Thus, make them depend on `.config` to trigger a
rebuild when the config changes.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I54739eae50fa1a47bf8f3fe2e79334bc7f7ac3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21 02:32:16 +00:00
Maulik V Vaghela c5603145d3 Revert "mb/google/dedede: Update Imon slope and Offset Value for Drawcia"
Falling back to default values for Imon slope and offset for Drawcia
This is as per recommendation from ODM based on calibration

This reverts commit 2ac88f2347.

BUG=b:175629526
BRANCH=dedede
TEST=Debug FSP confirms that values are reverted to default

Change-Id: I605acdcd0de2c5dfc28af2aea8cefc6b629c0925
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48737
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:32:05 +00:00
FrankChu bc89e8337c mb/google/dedede: Add GPIO to galtic support
Add support for gpio driver for galtic

BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I01bb95545705efab1a2adf1582b6293fd89e6420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48684
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:31:50 +00:00
Dtrain Hsu 85adcdbff4 mb/google/dedede/var/madoo: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for madoo and set slew rate to 1/8
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.

BUG=b:173765599
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I968d8d43016e3569835b0a777335fa1d5c135f87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21 02:31:42 +00:00
FrankChu 8cb922346f mb/google/dedede: Update SPD table for galtic
galtic memory table as follow:
value	Vendor	Part number
0x00	MICRON	MT53E512M32D2NP-046 WT:E
0x00	HYNIX	H9HCNNNBKMMLXR-NEE
0x01	MICRON	MT53E1G32D2NP-046 WT:A
0x02	HYNIX	H9HCNNNCPMMLXR-NEE

BUG=b:170913840
BRANCH=none
TEST=emerge-dedede coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30b8fe3f14e1af7bb5760530477f9311c6a4ee62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21 02:31:34 +00:00
Kevin Chiu d800d5e3ac zork: update gumboz variant
gumboz is the dalboz/dirinboz follower.
update gumboz variant to align dirinboz settings.

BUG=b:174277853,b:173662179
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I80c03d531761c02b68bd127d889c3ace2dd9e99e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-12-21 02:24:16 +00:00
Michael Niewöhner ccceb2250e mb/clevo/kbl-u: drop duplicated configuration of UART pads
UART pads already get configured in bootblock by the UART driver in soc
code. Thus, drop the duplicated code from the mainboard.

Change-Id: I95565a74e19d693a7d5ead81e72592cc4ca2038c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-12-20 00:02:09 +00:00
Michael Niewöhner 1a0071c711 mb/clevo/cml-u: drop duplicated configuration of UART pads
UART pads already get configured in bootblock by the UART driver in soc
code. Thus, drop the duplicated code from the mainboard.

Tested successfully on Clevo L141CU.

Change-Id: I05a459b0af79c75c31b1bb26ea1a1a40857ef9bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-12-20 00:02:02 +00:00
Eric Lai 3b648baf03 soc/amd/picasso: move sb_clk_output_48Mhz from acp to fch
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally.
We may have another device need this clock e.g. superio chip.

BUG=b:174121847
BRANCH=zork
TEST= build passed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-19 16:29:44 +00:00
Eric Lai dd32e653cf soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flag
If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.

BUG=b:174121847
BRANCH=zork
TEST= build passed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-18 19:55:12 +00:00
Felix Held 07462ef3d6 soc/amd/cezanne: add GPIO support
This still uses the common GPIO code that supports setting up SMI/SCI
support for the GPIOs in all stages, which will get removed in future
patches, so for now the SoC's gpio.c needs to be included in all stages.

Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18 17:20:56 +00:00
Zheng Bao 02a5dddb01 soc/amd/cezanne: Add SMI support
Change-Id: I83b9a91cbab297d032292997a4d5768b89fe97dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48645
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18 17:20:41 +00:00
Subrata Banik fad0a5b01c vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11
List of changes:
FSP-S Header:
- Adjust UPD Offset for Reservedxx
- Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45

Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-18 16:21:29 +00:00
Amanda Huang 8edb48baa6 util: Modify LPDDR4 spd_tools to generate SPDs for ADL boards
Generates de-duplicated SPD files using a global memory part
list provided by the mainboard in JSON format.

BUG=b:173132516

Change-Id: I4964ec28d74ab36c6b6f2e9dce6c923d1df95c84
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48526
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 21:56:43 +00:00
Angel Pons 2e0053b840 azalia: Use `azalia_enter_reset` function
Also tidy up some adjacent comments.

Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17 20:25:09 +00:00
Angel Pons a1a317ebf6 soc/intel/common/hda_verb.c: Clarify mask usage
The `azalia_set_bits` will mask out all bits, so just use zero for
clarity. The resulting behavior is the same in both cases.

Change-Id: I27777f1e836fa973859629d48964060bec02c87a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17 20:17:44 +00:00
Benjamin Doron ac857ca3b1 soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
coreboot already unconditionally enables CLKRUN_EN in SoC common code.

Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.

Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 20:05:49 +00:00
Felix Held a04400d1aa soc/amd/cezanne: add GPIO definitions
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-17 14:48:50 +00:00
Angel Pons 7f839f66ea azalia: Use `azalia_exit_reset` function
Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17 13:55:23 +00:00
Angel Pons 4919028e62 device/azalia_device.c: Add codec reset helpers
Many uses of `azalia_set_bits` are used to toggle the reset bit. To
avoid having to repeat the register operations and the corresponding
comment, create two helpers with self-explanatory names. They will be
put to use in subsequent commits, with one change for each function.

Change-Id: If0594fdaf99319f08a2e272cd37958f0f216e654
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:55:10 +00:00
Angel Pons f23c6a8ff5 device/azalia_device.c: Clarify comment
The `4` here doesn't have to do with the size of u32. Instead, it is
because the verb header contains the number of jacks, which is the
number of four-verb groups.

Change-Id: I3956ce5ec2a7abc29982504cf75b262a1c098af5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:54:57 +00:00
Angel Pons d3f7028993 azalia: Replace `hda_find_verb` uses
This function is equivalent to `azalia_find_verb` in its current form,
so replace them. Also, adapt and move the function description comment.

Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:54:43 +00:00
Angel Pons d425ddd105 azalia: Make `azalia_find_verb` parametric
Allow to specify which table should the verb list be read from.

Change-Id: Id1bc40c4364cda848f416bad9eeab1b8ca3e9512
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:54:24 +00:00
Angel Pons fcf8a3a6a3 azalia: Drop unused parameter from `azalia_find_verb`
The `dev` parameter isn't used anywhere.

Change-Id: I05643f8201137ffe89ded1e3f989c5a0f04e0af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:54:06 +00:00
Angel Pons 75c4f06314 azalia: Make `find_verb` function non-static
To allow dropping copies of this function, make it non-static. Also,
rename it to `azalia_find_verb` as the function is now globally visible.
Finally, replace the copies in chipset code with `azalia_find_verb`.

Change-Id: Ie66323b2c62139e86d3d7e003f6653a3def7b5f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:53:51 +00:00
Angel Pons e108e41b33 device/azalia_device.c: Remove debug prints
The other five copies of this function in the tree do not have these
debug prints. Remove them from here for consistency. Note that this
information is already printed elsewhere, so nothing is being lost.

Change-Id: I999032af1628bf8d66a057dc72368f02ef6eb8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:53:34 +00:00
Angel Pons 61dd8365bf azalia: Make `set_bits` function non-static
There's many copies of this function in the tree. Make the copy in
azalia_device.c non-static and rename it to `azalia_set_bits`, then
replace all other copies with it. Since azalia_device.c is only built
when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary.

This has the side-effect of building hda_verb.c from the mainboard
directory. If this patch happens to break audio on a mainboard, it's
because its hda_verb.c was always wrong but wasn't being compiled.

Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17 13:53:12 +00:00
Angel Pons c8be0947f1 mb/intel/coffeelake_rvp: Stop using headers for HDA verbs
One of the variants lacks an hda_verb.h, and hda_verb.c can't be built.
Follow-up changes will make mainboard hda_verb.c files always get built
through AZALIA_PLUGIN_SUPPORT, and breaks building this contraption.

Turn the headers into standalone compilation units to prevent this
issue. Since they contain definitions, including them from multiple
compilation units wasn't a good idea anyway.

Change-Id: I00d968563539a4e1b8d1e12145293439d8358555
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48360
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 13:52:59 +00:00
Marshall Dawson b8602aa184 amd_blobs: Add cezanne files
Add blobs from the 1.0.0.1 release of CezannePI-FP6.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebfbe819ed429a7aed1882964061e1bc98f3bc39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-17 13:27:06 +00:00
Kevin Chiu ad77576bcb mb/google/zork: update USB 2.0 controller Lane Parameter for morphius
from AMD USB phy specialist recommended that TXVREFTUNE0 shouldn't over 0xD (the maximum)
in order to have enough room to accomdate a safe disconnect threshhold in COMPDISTUNE0.
TXVREFTUNE0: 0xf -> 0xd

BUG=b:172687208
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ia104454d95e5e8d6a212c97fb09d61125945eeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-17 07:55:15 +00:00
Kyösti Mälkki 3b3dd84fb1 arch/arm: Replace .id section with build_info in CBFS
For arch/arm[64], the offsets to board identification strings and
CONFIG_ROM_SIZE inside .id were never really used; it was only a
convenience to have the strings appear near the start of image.

Add the same strings in an uncompressed file in CBFS.

Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47602
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 06:25:25 +00:00
Kyösti Mälkki 4c0f5769f0 arch/ppc64: Remove .id section in bootblock
The strings in .id are expected to match the build for
the purpose of identifying the binary image. There is
no identified use for the offsets.

The files id.ld and prologue.inc were unused.

Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-17 06:25:00 +00:00
Kyösti Mälkki b19d9511f9 arch/x86: Remove ID_SECTION_OFFSET
The location is hardcoded inside flashrom and FILO.
Only two offsets are supported, 0x10 and 0x80.

Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47598
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 06:24:30 +00:00
V Sowmya f0a9142b24 mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.
Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543

Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-17 06:23:41 +00:00
Iru Cai 16f213a499 autoport: Add a license header to non-empty files
Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45464
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 06:23:30 +00:00
Mathew King 2e2fc7a4f0 mb/google/guybrush: Add new mainboard
Guybrush is a new Google mainboard with an AMD SOC.

BUG=b:175143925
TEST=builds

Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 06:23:08 +00:00
Patrick Rudolph 2031221fbd soc/intel/cannonlake: Change mainboard_silicon_init_params argument
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on
xeon_sp and denverton_ns. This allows to set test config UPDs from
mainboard code as well.

Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-12-17 06:22:55 +00:00
Patrick Rudolph 8b56c8c6b2 drivers: Replace set_vbe_mode_info_valid
Currently it's not possible to add multiple graphics driver into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics driver can use.

This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.

The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple indepent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.

Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or
fb_new_framebuffer_info_from_edid.

Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-17 06:21:56 +00:00
Kane Chen 6c04b353c5 mb/google/zork: Add GPIO to Shuboz support
1. AGPIO5 to NC
2. EGPIO141 to NC
3. EGPIO144 to NC

BUG=b:174528384
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48002
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17 06:21:32 +00:00
Zheng Bao 9ca96f35f7 soc/amd/picasso: Fix the typo in GPIO define
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16 17:17:57 +00:00
Arthur Heymans 8346307603 soc/intel/xeon_sp: Move DMICTL lock
On SKX FSP-M does not return if this is set too early.

Tested on OCP/Tiogapass, boots.

Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 14:58:44 +00:00
Arthur Heymans c7b63edeb4 mb/ocp/tiogapass/devicetree.cb: Add P2SB device
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is
accessed to read out or reconfigure the HPET and PCH IOAPIC BDF.

Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 14:58:21 +00:00
Kyösti Mälkki 413539536d soc/amd/common/gpio_banks: Drop underscore in __gpio
The local function names were chosen such that they don't
collide with <gpio.h> so the prefix is unnecessary.

Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16 13:44:53 +00:00
Huayang Duan 5d6192aefe soc/mediatek/mt8192: Do the dramc pinmux selection
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 08:03:59 +00:00
Kyösti Mälkki 97b76f7191 arch/x86: Link gdt_init.S into bootblock
Followup work forces gdtptr and gdt towards the top of
bootblock. They need to be realmode-addressable, i.e.
within top 64 KiB or same segment with .reset.

Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16 06:31:55 +00:00
Angel Pons 54b5e20cf8 soc/intel/broadwell: Drop unnecessary `sa_dev`
Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:31:22 +00:00
Kyösti Mälkki dc873cc0c6 arch/x86: Clean up bootblock assembly
We have identical gdtptr16 and gdtptr. The reference in
gdtptr_offset calculation is not accounted for when
considering --gc-sections, so to support linking
gdt_init.S separately add dummy use of gdtptr symbol.

Realmode execution already accessed gdt that was located
outside [_start16bit,_estart16bit] region. Remove latter
symbol as the former was not really a start of region,
but entry point symbol.

With the romcc bootblock solution, entry32.inc may have
been linked into romstage before, but the !ENV_BOOTBLOCK
case seems obsolete now.

Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16 06:31:03 +00:00
Ren Kuo 5283c337bf mb/google/dedede/var/magolor: Add Wifi SAR for magolor and maglia
Add wifi sar for magolor and maglia:
Using tablet mode of fw config to decide to load custom wifi sar or not.
same wifi sar value for magolor and maglia (shared firmware)

BUG=b:173001370, b:173001251
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Cq-Depend: chrome-internal:3453724

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I44ab68c9ee5deced90d3858161571ab4b39b4c8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48448
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:30:33 +00:00
Seunghwan Kim 447db3a8a9 mb/google/dedede/var/sasuke: Add memory part and generate DRAM ID
This change adds memory part used by variant sasuke to
mem_part_used.txt and generates DRAM ID allocated to the part.

BUG=b:172104731

Change-Id: Ie8d66261cb5b4493afb1c677839f807bca994af5
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48451
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:30:18 +00:00