Commit graph

3737 commits

Author SHA1 Message Date
Patrick Georgi
ac9590395e treewide: replace GPLv2 long form headers with SPDX header
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.

Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)

perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)

perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)

perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)

Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06 22:20:57 +00:00
Patrick Georgi
02363b5e46 treewide: Move "is part of the coreboot project" line in its own comment
That makes it easier to identify "license only" headers (because they
are now license only)

Script line used for that:
  perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...

Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06 22:20:28 +00:00
Shaunak Saha
56e3df459a soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel
Kernel pinctrl driver changed for Tiger Lake and went to old scheme.
Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/
third_party/kernel/+/2116670

BUG=b:151683980
BRANCH=none
TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl
     verify INTC34C5:00 listing all the pins.
Cq-Depend:chromium:2116670

Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06 15:40:41 +00:00
derek.huang
e685107dd6 soc/intel/tigerlake: Print HPR_CAUSE0 register
In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value
of HPR_CAUSE0.

Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-06 08:48:24 +00:00
Ronak Kanabar
d4ad3f537f soc/intel/jasperlake: Correct the EMMC PCR Port ID
Updating EMMC PCR PID from 0x52 to 0x51 for Jasperlake

BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP from emmc

Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I17d4e7b7e0fe5e0b18867b6481b5bc9227ae19e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-05 13:00:57 +00:00
Ronak Kanabar
a4412d68d5 soc/intel/jasperlake: Allow SD card power enable polarity configuration
SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card
power enable pin. Setting it 1 will set polarity of this pin as Active
high. This patch will allow to control it from devicetree so that it
can be set as per each board's requirement.

BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD value from FSP log

Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: Id777a262651689952a217875e6606f67855fc2f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-05 13:00:41 +00:00
John Zhao
07171b480c soc/intel/tigerlake: Add PMC mux control
PMC supports messages that can be used for configuring the USB
Type-C Multiplexer/Demultiplexer.

BUG=b:151646486
TEST=Booted to kernel on volteer board and verified PMC and Mux
agent devices identification.

Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-05 13:00:01 +00:00
Wonkyu Kim
65cc80f740 soc/intel/tigerlake: Update interrupt setting
Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04 22:46:21 +00:00
Srinidhi N Kaushik
6ad8352a3d src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M
Due to refactoring of Serial IO code in FSP v3163 onwards we need to
set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart
initialization is skipped in FSP. This makes sure that SerialIo
initialization in coreboot is not changed by FSP.

BUG=b:155315876
BRANCH=none
TEST=build and boot tglrvp/ripto/volteer and check UART debug logs

Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04 22:45:48 +00:00
Michael Niewöhner
13dee2a911 soc/intel/skl: always enable SataPwrOptEnable
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization
Registers) when SataPwrOptEnable=0, which currently is the default in
coreboot and FSP. Even if FSP's default was 1, coreboot would reset it.

This can lead to all sorts of problems and errors, for example:
 - links get lost
 - only 1.5 or 3 Gbps instead of 6 Gbps
 - "unaligned write" errors in Linux
 - ...

At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and
purism/librem13v2) SATA is not working correctly and showing such
symptoms.

To let FSP correctly initialize the SATA controller, enable the option
SataPwrOptEnable statically. There is no valid reason to disable it,
which might break SATA, anyway.

Currently, there are no reported issues on CML and CNL, so a change
there could not be tested reliably. SKL/KBL was tested successfully
without any noticable downsides. Thus, only SKL gets changed for now.

Change-Id: I8531ba9743453a3118b389565517eb769b5e7929
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04 18:52:17 +00:00
Christian Walter
e01054d86e soc/intel/cannonlake: Add DisableHeciRetry to config
Add DisableHeciRetry to the chip config and parse it in romstage.

Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-04 14:20:17 +00:00
Sridhar Siricilla
f87ff33a89 soc/intel/common/block/cse: Add boot partition related APIs
In CSE Firmware Custom SKU, CSE region is logically divided into
2 boot partitions. These boot partitions are represented by BP1(RO),
BP2(RW). With CSE Firmware Custom SKU, CSE can boot from either
RO(BP1) or RW(BP2).
The CSE Firmware Custom SKU layout appears as below:
    -------------    --------------------    ---------------------
    |CSE REGION | => | RO |  RW  | DATA | => | BP1 | BP2  | DATA |
    -------------    --------------------    ---------------------

In order to support CSE FW update to RW region, below APIs help coreboot
to get info about the boot partitions, and allows coreboot to set CSE
to boot from required boot partition (either RO(BP1) or RW(BP2)).

GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE
region. The API provides info on boot partitions like start/end offsets
of a partition within CSE region, and their version and partition status.

SET_BOOT_PARTITION_INFO - Sets CSE's next boot partition to boot from.
With the HECI API, firmware can notify CSE to boot from RO(BP1) or RW(BP2)
on next boot.

As system having CSE Firmware Custom SKU, boots from RO(BP1) after G3,
so coreboot sets CSE to boot from RW(BP2) in normal mode and further,
coreboot ensure CSE to boot from whichever is selected boot partition
if system is in recovery mode.

BUG=b:145809764
TEST=Verified on hatch

Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-04 09:47:29 +00:00
Furquan Shaikh
76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5)
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.

In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'

BUG=b:155428745

Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02 18:45:16 +00:00
Andrey Petrov
4e48ac04da soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance
Perform the P2SB hide/unhide trick. This is needed so that BAR0
(0xfd000000) is not reclaimed by resource allocator, since it can
not deal with a device that does not exist (hidden).

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-05-01 23:12:12 +00:00
Andrey Petrov
cf270f0d62 soc/intel/xeon_sp/cpx: Enable common P2SB
Use common P2SB driver. This is needed to address a problem when
enumerator does not see p2sb device (since it is hidden) but it
is active and BAR is decoded.

Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 23:12:02 +00:00
Andrey Petrov
15070e7ea8 soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs.

Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 23:11:55 +00:00
Maxim Polyakov
d2b3e81095 xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs
Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 22:12:41 +00:00
Elyes HAOUAS
6468d87dde soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:40:20 +00:00
Elyes HAOUAS
d2bbc68fa3 soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:37:47 +00:00
Elyes HAOUAS
066e61f3ea soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:37:13 +00:00
Elyes HAOUAS
ad87d1c8b9 soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:36:28 +00:00
Elyes HAOUAS
2ec1c13ac4 soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:36:26 +00:00
Elyes HAOUAS
b887adf7a5 soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:35:06 +00:00
Subrata Banik
7be0df8dd3 soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding
BIT 1 -> DEBUG_INTERFACE_UART_8250IO
BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO

Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-01 06:56:45 +00:00
Marco Chen
7d18f88c6d soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_num
BUG=b:152019429
BRANCH=None
TEST=1. provision dram_part_num field of CBI
     2. modify mainboard - dedede to report DRAM part number from CBI
     3. check DRAM part number is correct in SMBIOS for memory device

Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01 06:52:48 +00:00
Patrick Rudolph
09a106907e soc/intel/cannonlake/bootblock: Fix FSP CAR
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.

Tested on Intel CFL, the new code allows to boot using FSP-T.

Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 06:48:44 +00:00
Meera Ravindranath
0d6cc22017 soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.

BUG=None
BRANCH=None
TEST=Build and boot tglrvp.

Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-01 06:27:32 +00:00
Meera Ravindranath
798fd4b69f soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.

BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe

Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-01 06:17:21 +00:00
Elyes HAOUAS
b8a0cd11c6 src: Remove not used 'include <smbios.h>'
Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 06:16:33 +00:00
Elyes HAOUAS
2d7173d462 src: Remove unused 'include <cpu/x86/cache.h>'
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:10:49 +00:00
Karthikeyan Ramasubramanian
e0b7a88f58 soc/intel/jasperlake: Add support to generate ACPI GPIO operations
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs.

BUG=b:152936541
TEST=Build and boot the mainboard. Ensure that there are no errors in
the coreboot logs regarding unsupported ACPI GPIO operations.

Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01 06:10:04 +00:00
Eric Lai
26afd648a1 soc/intel/tigerlake: Check SPD is not NULL before print
Check SPD is not NULL before print. This can prevent the system
from hanging up.

BUG=b:154445630
TEST=Check NULL SPD is not print.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29 21:26:01 +00:00
Venkata Krishna Nimmagadda
cd41fa378d soc/intel/tigerlake: Add method to look up GPIO com ID for an index
This patch adds GPID, a helper method to look up GPIO community ID for
an index.

This patch also includes Intel's common GPIO ASL code. CGPM method in
the common code uses the GPID method introduced in this patch.

BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29 03:01:30 +00:00
Venkata Krishna Nimmagadda
f98bbda5fb soc/intel/common: Add method to modify GPIO community PM config
This patch adds CGPM, a helper method to configure GPIO power management
bits that are part of miscellaneous config. This is needed for
configuration of these bits on S0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29 03:01:22 +00:00
Nick Vaccaro
029b5432a1 soc/intel/tigerlake: fix call to print_spd_info()
Pointer passed to print_spd_info() from meminit.c needs to be
dereferenced first, so this change dereferences it.

BUG=b:154352883
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, login to kernel and execute the following cbmem command:
  localhost ~ # cbmem -c | grep LPDDR4X
and verify it returns "SPD: module type is LPDDR4X"

Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-28 20:49:44 +00:00
Furquan Shaikh
338fd9ad30 device: Constify struct device * parameter to acpi_inject_dsdt
.acpi_inject_dsdt() does not need to modify the device
structure. Hence, this change makes the struct device * parameter to
acpi_inject_dsdt as const.

Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28 19:51:25 +00:00
Furquan Shaikh
7536a398e9 device: Constify struct device * parameter to acpi_fill_ssdt()
.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.

Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28 19:50:26 +00:00
Furquan Shaikh
ec3dafd97c soc/intel: Constify struct device * parameter to intel_igd_get_controller_info
intel_igd_get_controller_info() does not need to modify the device
structure. Hence, this change makes the struct device * parameter to
intel_igd_get_controller_info() as const.

Change-Id: Ic044a80e3e2c45af6824a23f3cd0b08b94c0f279
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28 19:50:17 +00:00
Furquan Shaikh
3b54fdf282 soc/intel: Constify struct device *param to sd_fill_soc_gpio_info
sd_fill_soc_gpio_info() does not need to modify device
structure. Hence, this change makes the struct device * parameter to
this function as const.

Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28 19:50:07 +00:00
Furquan Shaikh
00296ea96f i2c/designware: Constify struct device * parameter to dw_i2c_soc_dev_to_bus
dw_i2c_soc_dev_to_bus() does not need to modify the device
structure. Thus, this change makes the struct device * parameter to
dw_i2c_soc_dev_to_bus as const.

Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28 19:39:46 +00:00
Furquan Shaikh
0f007d8ceb device: Constify struct device * parameter to write_acpi_tables
.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.

Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28 19:21:49 +00:00
Eric Lai
0ee9b14c09 soc/intel/common/block/smbus: Set SPD array NULL if no DIMM present
Set SPD array NULL if no DIMM present. do_smbus_read_byte returns
negative value if SMBus transaction fails.

BUG=b:154445630,b:151702387
TEST=Check SPD is NULL if no DIMM in the slot.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie81adbfab5bb1d5c557fe549a158cb68e26b1162
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28 16:23:15 +00:00
Kane Chen
d2b2be3929 soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI device
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD.

This commit provides _DSM method for driver to query driving strength.

TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4
BUG=b:154159888

Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-28 15:43:36 +00:00
Felix Singer
007faee948 soc/intel/cometlake: Add ucode from repo
On Comet Lake, add the following microcode updates from the 3rdparty
repository:
- 06-8e-0c (CPUID signature: 0x806ec)
- 06-a6-00 (CPUID signature: 0xa0660)

Tested with Clevo N141CU.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Id10b013df8ce98a4e9830782570e20fbcfad05c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-28 14:39:34 +00:00
Maulik V Vaghela
8745a2743c soc/intel/jasperlake: Add new MCH device ids
Add new MCH device-ids for jasperlake.
Reference is taken from jasperlake EDS volume 1 chapter 13.3.

BUG=None
BRANCH=None
TEST=code compiles and able to boot the platform.

Change-Id: I38e09579c9a3681e9168c66085cbb3a092dc30cc
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-28 09:39:42 +00:00
Matt DeVillier
8536072346 soc/baytrail/raminit: Populate SMBIOS type 17 tables
Populate SMBIOS type 17 tables using data from SPD and read via IOSF.
Refactor print_dram_info() to pass thru SPD data and channel/speed info.
Move call to print_dram_info() after cbmem initialization so the SMBIOS
data has somewhere to go.

Test: build/boot google/swanky, verify via dmidecode.

Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28 08:02:57 +00:00
Subrata Banik
d6f7ec5f44 soc/intel/apollolake: Avoid CONFIG_PCIEX_LENGTH_256MB selection
This patch removes APL SoC selecting CONFIG_PCIEX_LENGTH_256MB Kconfig
as default configuration for CONFIG_SA_PCIEX_LENGTH_MIB is 256MB.

TEST=Able to build and boot APL platform.

Change-Id: I61249f0adff5e03c07a568556e1ff76b27c6d368
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40378
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-26 08:01:17 +00:00
Furquan Shaikh
8ebbe17b86 soc/intel/tigerlake: Fix FSP SPD index for DDR4
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1
to set SPD for index 4. This change adds a helper macro to translate
DDR4 channel # to the index # that the FSP expects.

BUG=b:154445630
TEST=Verified that memory initialization for DDR4 is successful.

Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-25 05:56:17 +00:00
Andrey Petrov
5d76958de1 soc/intel/xeon_sp/cpx: Calculate number of threads based on sockets
Assuming given system is populated with multiple CPUs of same SKUs,
calculate number of threads based on MAX_SOCKET.

This is a stop gap solution until proper way of identifying total
number of sockets is determined.

Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-24 19:44:19 +00:00
Andrey Petrov
e37d1f724a soc/intel/xeon_sp/cpx: Bump MAX_CPUS
Some dual-socket socket systems offer over 100 threads available.
Other multi-socket configurations potentially offer even greater
numbers of CPUs (over 9000!).

Bump MAX_CPUS to 255.

Change-Id: I50a181b89f40777a9f7b3881280c7bacf1b947cb
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-24 19:44:12 +00:00