supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The change in tables.c protects the legacy x86 BIOS data segment
(0x400-0x4ff) from being used for storing coreboot tables. Some
bytes from the segment are used by the kernel and should not be
garbled.
The change in coreboot_table.c is not strictly necessary. It removes
some redundancy and confusion.
Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
went missing....
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Includes setting for most recent errata.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested by me on actual hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on v1 and v2 of the board.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the range of 0xf0000-0x100000, where the Coreboot tables live in v2.
As long as the payload doesn't need the tables, it seems harmless, so
why not just print a warning?
This allows v2 to load "legacybios" without having to have a separate loader.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
It'll be fine for testing and doesn't really break anything that did
work before...
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This also contains various improvements of the CN700 code in svn.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pci_write_config8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- W83627THF is strapped to 0x4e, not 0x2e
- there's no device 9 on PCI-E x1 bus, it should be device 0
- add mptable entries for AGR slot, based on info in user manual
- enable floppy drive controller so that some legacy VGA ROMs will work
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for both serial ports, making it challenging to use COM2 for the early
console.
Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This doesn't save any space for me but it is the right thing to allow GCC to
optimize.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Peter did a nice job cleaning up my initial patch. Thanks!
Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Disabling it should help performance.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is based on amd-lx800/cs5536.
Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
white space in the s2892 and s2891 mptable.c files.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.
Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.
While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Pstate intialization has moved to early init because it requires a warm reset.
Add CPUID setup and disable SMM access to late initialization.
Much of this code is leftover from porting from K8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).
The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In addition, AP microcode is now updated in early initialization to support errata settings that require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generic SMSC support, and corrects a small typo.
With this patch, coreboot v2 on a mainboard with SCH3112 has been
demonstrated to correctly use the serial port. No other chip
functions were tested.
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
recomendations.
Changes include the following:
fix > 4GB dqs tests
fix channel interleaving
ecc memory scrub updates
MC tristating updates
debug print changes
fix memory hoisting across nodes -
The DRAM Hole Address Register is set via devx in each node, but the Node
number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
set in Node 0. The memmap is setup on node0 and copied to the other nodes
later. so dev, not devx. The bug was the hole was always being set on the
first node.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
patch.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Marc Jones (marc.jones@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs.
Signed-off-by: Marc Jones(marc.jones@amd.com)
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It also keeps the boot processes from rebooting through out the coreboot process.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
The same change was committed in r3044 to the AMD CAR code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
"off" in Config.lb should cause the PCI device not to respond to
configuration requests.
Replace the existing code that I naively copied from esb6300 with
something that actually works on the 3100.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
There are no boards that use the i82801DB (ICH4). The code does NOT work.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the system automatically unless software resets the timer
periodically. The extra reboot extends boot time by several seconds.
The attached patch adds a function to the Intel 3100 southbridge code
that halts the TCO timer, thus preventing this extra reboot, and calls
the function early in the boot process on the Mt. Arvon board.
It also fixes a bug in the LPC device initialization -- the ACPI BAR
enable flag is bit 7, not bit 4.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The V-link setup and HT bridge is redone, because VT8237A has it in another
device. So far following combination of chipsets should now work:
K8T890CE + VT8237R
K8M890(CE) + VT8237R
VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and
notes about K8M890 support were added.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
max width of the link and also it will take the frequency of K8 HT
already done coreboot (and checks if t can run on it).
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* simplify and improve cpuid table
* add speedstep support for VIA C7 based CPUs
* also included as many of Uwe's suggestions as possible
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code it should have contained.
This patch updates the PCI IDs for Intel 3100 devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
northbridge and RAM controller.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
comments. Ripping out the ehci/uhci_init() code doesn't seem to have
done any harm, and I got rid of a bunch of unused junk in
i3100_smbus.h
I left the *_set_subsystem() arguments unsigned, as that's how the
function is declared in include/device/pci.h.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flashes such as SST49LF080A: 1024K x8 (8 Mbit)
Tested on my system, the flash is found and if I use coreboot in second half it
works too.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
nVidia cards. The enable link should be enough, retrain is done there.
Tested on my system.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
No functional changes, only cosmetics. This is compile-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
no VGA output from coreboot, even after the boot-rom was executed
properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with
CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the
class field of struct device is '3 bytes: (base,sub,prog-if)'.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than
desirable. I did not notice before because my board ran fine for about 15
minutes before the CPU overheated.
Thankfully the board has a good failsafe mode - it just switches off when the
CPU gets too hot, without permanent damage.
I'm debugging this and plan to commit a proper fix later in the week.
This is not really trivial, but the tree is dangerous in the current state so
I'm self-acking.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
board.
This is done via the ec_init routine in a source file in the
mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been
added to notify superio.c to get the ec_init externally.
I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board.
It works.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a compiler warning.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
working for now, and more work is needed for it to be fully dynamic. However,
just about any 128MB-512MB DIMM should work.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Don't enable pin0 for ioapic of io-4.
1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
for device under them in mptable.
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
undefined u8 type and the bitpos selection in currently unused
pnp_read_enable function.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
device) and sets the chipset voltage from 1.6V to 1.5V.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
changed, but also a SPI flash interface which has enable on bit1 and not bit0.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
have GAME and MIDI portsenabled.
It has been tested with my board. It produces same results.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mine W83627EHF.
This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but
maps to original LDN and bit position in register 0x30.
VirtualLDN = origLDN[7:0] | bitpos[10:8]
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
following mainboard files had identical Geode LX specific print_conf()
implementations:
mainboard/amd/db800/mainboard.c
mainboard/amd/norwich/mainboard.c
mainboard/digitallogic/msm800sev/mainboard.c
mainboard/pcengines/alix1c/mainboard.c
Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs.
Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
interface of the IT8716 SIO chip.
Changes :
1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
functions of a PNP device can have more than 12 resources (ex the GPIO function
of IT8716f), in which case one could have an "array overflow" inside the device
structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
device init time..)
2) - define resource masks for the GPIO function in
src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
by the init code
3) - enable the flash SPI interface into
src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
into the GPIO function). I know that this is problematic because not all m57sli
boards are SPI, but .. do anyone have a better idea how to handle this?..
Signed-off-by: Florentin Demetrescu <echelon@free.fr>
I (Ward) have verified your patch on a rev2 of this board (it works!) as well
as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse
side effects that I noticed, so I think this patch should go in.
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on actual hardware by Sergei Antonov <saproj@gmail.com>.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Sergei Antonov <saproj@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
included on the CC line for cache_as_ram_auto.c
Tested on ubuntu, where formerly it failed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
about a serial port. If a port is defined in the board configuration,
add it to lbtable.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
That fixes a compilation failure.
Signed-off-by: Marc Karasek <marc.karasek@sun.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
suspend clock (undocumented in datasheet, documented in 'W83627HG-AW').
Introduce sio_init function for all this.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
C7 bios programmer's guide explicitly states they're not necessary, and
leaves it at that. Even if they are possible and exist, we don't have
any info on it, nor any updates, so drop these unneeded references.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For the old supported CAR sizes, the newly generated code is
equivalent, so it should be a no-brainer.
Benefits:
* a nice code size reduction
* less #ifdef clutter for Family 10h
* paranoid checks for CAR size
* clear abstractions
This has been tested by Marc Jones and Jordan Crouse.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
No code lines affected, so svn blame will not be messed up.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generic x86 CAR code. For the old supported CAR sizes, the newly
generated code is equivalent, so it should be a no-brainer.
Add a copyright header to the code, the header is derived from the one
found in the same piece of code in v3.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Normalize used locale to "C" before parsing output.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
similar smp_write_intsrc calls in preprocessor macros.
Also add some comments about the actual devices the INTs
belong to.
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rather independent, lift the implicit (broken) assumption that
CONSOLE_VGA would also run the ROMs, and transfer it to a new
config option VGA_ROM_RUN.
This change is minimally intrusive, because all board configs
that previously assumed CONSOLE_VGA would also run the ROMs
didn't compile, they had to also specify PCI_ROM_RUN.
Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
(separate ROM_RUN from VGA console).
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mainboard directories, but the code was not referenced anywhere.
intel/jarrell
dell/s1850
supermicro/x6dhr_ig2
supermicro/x6dhr_ig
supermicro/x6dhe_g2
supermicro/x6dhe_g
Besides that, the contents of these files were either duplicates of
src/cpu/intel/model_f3x/microcode_M1DF340E.h or
src/cpu/intel/model_f3x/microcode_M1DF3413.h.
svn remove the following files:
src/mainboard/supermicro/x6dhe_g/microcode_updates.c
src/mainboard/supermicro/x6dhe_g2/microcode_updates.c
src/mainboard/supermicro/x6dhr_ig/microcode_updates.c
src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c
src/mainboard/dell/s1850/microcode_updates.c
src/mainboard/intel/jarrell/microcode_updates.c
Abuild tested, as expected no failures.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18
(verified on an v1.0 board).
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Removed local APIC INIT (don't worry the APIC and AP are still initialized).
The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
The Intel Multiprocessor specification indicated that a vector should be set
and a START should happen following an INIT. Then AP will execute the
instructions pointed to by the vector. There is no vector or start in
stop_this_cpu(). This seems to put the AP in an in-between state. In the case
of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
debugger.
The better solution seems to be to just put the AP in a hlt and allow the AP
to go into C1. Then APIC managing software running on the BSP can program the
AP as needed.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this is needed (at the very least) to make FILO work on these boards.
Disable UDMA/33 per default, which is slower but the safe choice, as we
don't know which IDE devices a user has attached, and some don't support
UDMA/33 very well or at all.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA"
line in it.
I figure that only adding it to the files that already have support
for LZMA payloads makes sure I don't break anything.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coherent_ht.c (save one empty line removed) so there's no use
to keep it around.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Implement ISA related support:
- Initialize the RTC
- Enable access to all BIOS regions (but _not_ write access to ROM)
- Enable ISA (not EIO) support
- Without the *_isa.c file, the Super I/O init is never performed
- Improve IDE support:
- Add config option to enable Ultra DMA/33 for each disk
- Add config option to enable legacy IDE port access
- Implement hard reset support
- Implement USB controller support
- Various code cleanups and improvements
The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
according to mcqmcqmcq@fastmail.fm. Fix it.
Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
Acked-by: mcq <mcqmcqmcq@fastmail.fm>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for
AMD Athlon 64 and AMD Opteron Processors' datasheet.
Also, add information about the CPU socket for each ID (as per datasheet).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It never worked in v2 (the v1 port did work AFAIK, though), and it's
not really useful as reference for other boards anymore (as we now
have a dozen or so 440BX boards which work in v2).
This is a specialized, custom board (not sold on the "public market"),
so it's probably not useful for pretty much everyone out there anyway.
We can easily re-add it later (based on one of the other 440BX boards)
should there be interest and/or someone with the hardware to test.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
You cannot set 'default ROM_SIZE = 0' in Options.lb (and override it in
targets/*/Config.lb). While it'll work for manual builds, abuild doesn't
cope with that very well. So set a valid value in Options.lb, too.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
make it clearer why they are disabled (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use 'static' where appropriate.
- Use 'const' where appropriate.
- Indentation fixes.
- Add comment wrt init code which is only valid for VT8237R.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reason: The existing code does not tell us why it sets the watchdog
clock at all, but since it appears in cache_as_ram_auto.c instead of
the usual place (Config.lb) there has to be some meaning to it.
Simply do what the proprietary bios does: Use the external clock source.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This enables us to have only one configuration and one set of code for
all revisions of the Gigabyte GA-M57SLI-S4.
Flash is now setup correctly for both SPI and LPC flash.
Detection of SPI flash in flashrom on rev. 2.x boards now hangs
instead of failing. However, that is just an effect of the combination
of incomplete initialization of the SPI controller and paranoid checks
in the flashrom SPI code.
If anyone wants to work on that, he needs a logic analyzer or creative
imagination. Hint: LPC-to-SPI read passthrough, clock signal.
Remaining issues for the M57SLI: Fan/environment control.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer