The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To
reduce the binary footprint for chipinfo structure, change its members
range from uint32_t to uint16_t. Add helper functions for reading and
matching jtagid. Modified socinfo_modem_supported() API to utilize
helper functions.
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
On Herobrine, we will determine if we have an NVMe device based on SKU
id. Basically, if bit 0 is 2 (or Z), then we know that we have an
NVMe device and thus will need to go through PCIe initialization.
Otherwise, we know that we are booting an eMMC device.
BUG=b:254281839
BRANCH=None
TEST=build firmware image and boot and make sure we can boot up Tested
on villager, which does not have NVMe and made sure that it boots
still. Check cbmem dump to make sure that device configuration
entry is still low since it's not initializing PCIe devices:
40:device configuration 730,203 (1,295)
Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 1b07797a7b.
Reason for revert: Herobrine program decided that we wanted
to be able to boot from NVMe if one exists.
Change-Id: If675947026095d16b72bdb0f3ec790e583523465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.
Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
We are required to boot with eMMC enabled in the BIOS to store modem
calibration data. Thus, it doesn't make sense to enable NVMe at boot
time since we will never boot from NVMe w/o eMMC. We may as well take
the boot time reduction (~100ms) by eliminating NVMe initialization.
BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after disabling NVMe and make sure that it still boots
Note that we are able to see a little over 100ms in boot time
savings with this change.
Before: 40:device configuration 824,021 (102,701)
After: 40:device configuration 717,402 (44)
Cq-Depend: chromium:3964185
Change-Id: I94f614ba0369c073617949285c0781aef5c6263f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Coverity is throwing a bunch of "maybe uninitialized" errors for tu
struct. Initialize the tu struct with zero.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Change-Id: Ie249ad4f53abc91376445420712364a28618a15a
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Instead of just printing the fatal errors, do early return so that
boot up time will be reduced during display init failure. Remove malloc
allocation and make tu a local variable.
Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66975
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for SocInfo in coreboot. The API socinfo_modem_supported is
added to help to differentiate between LTE and WiFi SKUs.
BUG=b:232302324
TEST=Validate boards are detected correctly on LTE and Wifi SKUs
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: I61047ad49772c3796ba403cafde311ad184a4093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
- Add support for edp aux read and write.
- Update edp panel properties based on edid read.
- Configure edp controller and edp phy.
Panel details:
Manufacturer: SHP Model 1523 Serial Number 0
Made week 53 of 2020
EDID version: 1.4
Digital display
8 bits per primary color channel
DisplayPort interface
Maximum image size: 31 cm x 17 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4
Default (sRGB) color space is primary color space
First detailed timing is preferred timing
Supports GTF timings within operating range
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 5a8780a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 653880a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Hex of detail: 000000fd003090a7a7230100000000000000
Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock
350MHz
Hex of detail: 000000fc004c513134304d314a5734390a20
Monitor name: LQ140M1JW49
Changes in V2:
- Remove Misc delays in edp code.
- Move mdss soc code to disp.c
- Update EDID read using I2C write & read.
Changes in V3:
- Remove unrelated delays.
- Misc changes.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Change-Id: If89abb76028766b19450e756889a5d7776106f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
For ipq806x this fixes two resources getting declared
with same index. The latter previously overwrote former.
Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase frequency of sc7280 to 75 MHz. Setting the delay to 1/8 of
a cycle as a result of experimentation.
BUG=b:190231148
BRANCH=None
TEST=Make sure that herobrine board boots
HW Engineer measured SPI frequency and verified running at 75 MHz
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I3cf5a7c85f12800a11ece397a354349f2a0a235f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64673
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the datasheet, we can safely increase the SPI frequency of
sc7280 to 50 MHz.
BUG=b:190231148
BRANCH=None
TEST=build and boot BIOS with this config on herobrine boards
Change-Id: I84420d7d8ab0cb979fc606fcf05147197bc51c35
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Previously, clock_configure() will configure the clocks to round up to
the next highest frequency bin. This seems non-intuitive. Changing
the logic to find an exact frequency match and will halt booting if no
match is found. Recently fixed a bug in CB:63311, where the clock was
being set incorrectly for emmc and was able to find it because of this
stricter check.
BUG=b:198627043
BRANCH=None
TEST=build herobrine image and try to set SPI frequency to number not
supported. Ensure device doesn't boot.
Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Found an issue where emmc and sd clocks were being misconfigured due
to using incorrect integer values when called instead of the defined
enums. Fixing by splitting the clock_configure_sdcc() function into
two (sdcc1 and sdcc2) as there was no commonality between the two
cases anyway. As a result, we can also get rid of the clk_sdcc enum.
BUG=b:198627043
BRANCH=None
TEST=build herobrine image and test in conjunction with CB:63289
make sure assert is not thrown.
Change-Id: I68f9167499ede057922135623a4b04202f4da9b5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change supports the configuration and enablement of
mdp clock to vote for turbo and supports different display
panel resolutions and framerates.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modem uses different memory regions based on LTE/WiFi.
This adds correct carve-out to prevent region being disturbed.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: T Michael Turney <quic_mturney@quicinc.com>
Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
CPUCP is CPUSS Control Processor. It refers to the firmware for control
CPUSS active power management.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on comments in CB:49392.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This patch enables bootblock compression on SC7280. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Ref link: https://review.coreboot.org/c/coreboot/+/45855
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Updated return type as CB_SUCCESS and aligned indentation.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Introduce DDR One-Time-Training Support
Device reboots without training from second iteration
and also DDR training data is 32kb size, hence update
required in memlayout and to sync with upstream changes
the Fmap size even got bumped up.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able
to configure & enable the desired clocks.
The clock driver also supports reset of subsystems like AOP and SHRM.
Also add support for Zonda PLL enable for CPU in common clock driver.
Refactor the SC7280 clock driver to use the common clock driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
