Following the same reasoning as commit
ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.
Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7699
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.
Change-Id: I7798b689db3e582649eb4af4ccd1877bb1d49063
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Id3b16872f62660393d938d6f95977a4e3842d0d1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7690
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Silence some useless Clang warns in this case.
Change-Id: I202a85f7dec52c65d80e2bc56f7d9e4eb3e61d48
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7696
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Its scope is limited to a single mainboard and is only to go through ifdef.
Kill it and move the value to the code.
Change-Id: I76a87e2790d57dee8f37b51e33d0689fffd3a59d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7135
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Currently due to enum mistake DDR3 = 0xb was confused with DIMM type and
interpreted as LRDIMM, considered unregistered and so every RAM was
unregistered.
Registered RAM is rarely used, so I suppose the code was never tested with them.
For unregistered RAM exactly the same codepath is followed.
Change-Id: I02fe8b1fd7be3bd382399ffa0eb513965a2a6d77
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7687
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
I have no such board to check the real fixes but this board shouldn't block
benefits for the rest of the tree.
Change-Id: I9e9d4af1b360bcf0099ac2901b08f7fcd7569097
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7681
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Keep only the last one: it was the one which was really used.
Change-Id: I19132f6224d6847e615e3c582aaa6e66b0d56c7a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7677
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Topology Extensions Support (bit 54 of 0xC0011005) applies to
PACKAGE_TYPE_FS1r2 also. Rids us of:
"Re-enabling disabled Topology Extensions Support"
showing up in dmesg.
Change-Id: Id123fa9632936c150cf1aebc4d34b404a4398ead
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7671
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
The current interrupt routing shares interrupt 5 between LPC and PCI which
isn't possible.
Use IRQ 11 for all devices in PCI mode. Move conflicting LPC to free IRQ.
Change-Id: I3ac8c2f19195ef6b07f4ee7dde64dd038d024126
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7477
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This config is used only to generate PIRQ table. If no such table is
supplied there is no need for config.
Change-Id: I537d440f53019a6bf7f190446074e75e7420545a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7566
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
The contents of these files were guarded by a check for the _MSC_VER
macro, which we don't use.
Change-Id: Ic595c8e6284c54e1449cf21e0cebee8c9ce7c682
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7670
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Don't build in non-essential blobs by default. However, if the user
selected to use the blobs repository, then default to including the
blobs.
Change-Id: Ie90f00d7c18d725f24fe1503fadaf098d3cefa4a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7638
Tested-by: build bot (Jenkins)
Rather than have Linux report:
i8042: PNP: No PS/2 controller found. Probing directly.
and go off probing PNP config space, build in EC ASL for the
PS/2 keyboard and mouse.
The ASL explicitly passes these resources to the Linux to avoid
said probe.
ASL Details:
PS/2 keyboard (PNP0303 at 0x60,0x64 irq 1 )
PS/2 mouse (PNP0F13 at 0x60,0x64 irq 12)
Change-Id: I0697fab65915907fbe2b3551182b3a1b0d665ddb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7651
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Provide ASL to support the AUX port (a.k.a Mouse) found at
0x60,0x64 irq 12 on this EC.
Change-Id: I6969ae4d492570136a8e14e42509638857e1ed85
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7650
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Toggle on in devicetree.cb and build into AGESA by buildOpts.c.
Add ACPI and MPTABLES interrupt routers for IOMMU also.
Change-Id: Ia838f9b70f09ed1180daeb5382edc08c4b74946c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7643
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Missing IOMMU support is missing from the libagesa Makefile, it also
lacks a header with type-signature and a few bad typecast issues.
Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Co-Author: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/7642
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use non-local inclusion syntax over relative paths for
'drivers/pc80/ps2_controller.asl'.
Change-Id: Ie2bfa893dc268ec5118d2a9addadbc759d85d357
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7664
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Right now, coreboot code using AGESA headers can only build if all the
AGESA path are given to the compiler via the "-I" option. This is sub-
optimal, as it requires us to have every AGESA source directory
specified as a compiler include path. This pollutes our global include
paths.
We restrict the compiler include paths to only allow "AGESA_ROOT/" and
"AGESA_ROOT/Include". We then modify the AGESA headers to specify
non-local include files relative to "AGESA_ROOT/Include".
We use the convention that includes relative to the directory of the
header are included as "path/to/header.h", while includes relative to
AGESA_ROOT are included as <path/to/header.h>.
This change allows building coreboot code based on AGESA with the
limited subset of include paths, but does not allow AGESA itself to
build with this restricted subset.
Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5424
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Minor fix to avoid confusion, nothing to see here.
Change-Id: I89d56a91d2df049e85cf49c23218620caba84880
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7654
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
It was requested to be able to update XHCI vs EHCI via get_option,
so I've added it here for minnow max. This could get moved to the
chipset_fsp_util.c file later, but I'm adding it here for now.
More checking needs to be added to this:
- Are both controllers enabled in devicetree? If not, we don't want
to allow the switch.
Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7633
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
- Align register values.
- Enable both EHCI and XHCI so the choice of port used can be made
at runtime. When both are enabled in devicetree, XHCI currently gets
disabled by the FSP chipset code. This can be overridden in mainboard
code or by a Kconfig entry, but there's a question about whether or not
that's desired.
- Enable function 1c.0 so the rest of the functions will be
seen, even though the function is not actually used. This is a
short-term fix, as the correct solution is to determine whether or not
any of the other functions are enabled, and not to hide function 0 if
they are. I am working on that, but I want to get this in for now.
Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7663
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
- The EDS has the function disable bit for eMMC incorrectly listed
as 8. Changing it back to the correct bit 11.
- The FSP will disable functions that it is told are disabled, so
coreboot code that disables the functions is redundant. Removing it.
Change-Id: I95c31d92d3af5182ddf7fd47f651bbb61cdedb82
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7653
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
- The ROM chip is 8MB, not 4MB.
- Default to the 2GB SKU instead of 1GB - that's what's out right now.
- Set CBFS size to 3MB - that's what the firmware descriptor is set to.
Change-Id: Ic77f5c1e898dca39de573623707ff5f5e5ca9682
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The documentation for the FSP gives the name as BAYTRAIL_FSP.fd instead
of the old FvFsp.bin.
Change-Id: I69c7c5ff49afd6552612cf50c9ca9b30cfb003e2
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7648
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
New microcode for Bay Trail I B2/B3 and D0 parts was released in the
Gold 3 Bay Trail FSP release.
Change the microcode size to an area instead of the exact size of the
patches. This will hopefully reduce updates to the microcode size.
Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Move the Kconfig variable into a .h file - this does not need to be
in Kconfig.
Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Include clock.c in the appropriate coreboot stages, modify the code to
build cleanly. Use proper pointer cast in .h files.
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196407
(cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e
Reviewed-on: http://review.coreboot.org/7271
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
These driver needs to be in src/lib, and the include file needs to be
renamed to avoid collision with the top level uart.h.
BUG=chrome-os-partner:27784
TEST=emerge-storm coreboot still works
Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196393
(cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401
Reviewed-on: http://review.coreboot.org/7270
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.
Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Update the printk statements to use FSP_INFO_LEVEL instead of
BIOS_DEBUG. These values are currently identical, but by using the
second #define, it lets them all be changed as a unit. This can
be overridden for a particular platform by adding a #define in
chipset_fsp_util.c.
Change-Id: Idbf7e55090230ec940c7c8cd3ec8632461561428
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7520
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
- Update chipset_fsp_util.c to use the UPD_DEVICE_CHECK macro. This
makes the code more standardized and easier to read.
- Add some debug printing that was removed in the transition.
Change-Id: Iea24dd9ca53f39791bc6371291a3fa7a6fc5ed0f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7498
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
- Update chipset_fsp_util.h to add the UPD_MEMDOWN_CHECK pointing into
the PcdMemoryParameters structure. This is baytrail FSP specific, so
it's put into the chipset code instead of the 'driver' code. Since some
of the values need to be decremented and some do not, a second parameter
was added to control this. This macro also does not print out the
values as they are printed out separately if memory down is enabled.
- Update chipset_fsp_util.c to use the UPD_MEMDOWN_CHECK macro. This
makes the code more standardized and easier to read.
Change-Id: I233e45db43af4726cab41f4880f1706cf8abb0b7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7632
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Update chipset_fsp_util.c to use the UPD_SPD_CHECK macro. This
makes the code more standardized and easier to read.
Change-Id: I9944e1a4df82e64a205598e98ed0f3b840af1019
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7489
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
- Update chipset_fsp_util.c to use the UPD_DEFAULT_CHECK macro. This
makes the code more standardized and easier to read.
- Update chip.h to use standardized macros
Change-Id: Icbe5ec92b0aa31e21f3dd1593a96b246d83008f7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7488
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add macros and #defines for working with the UPD data. This makes
the code look much cleaner.
Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include
the fsp_values header instead. This fixes a conflict.
Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7487
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add a section .illegal_globals to romstage and check that the section does not
contain any variables while creating romstage.
[pg: Handle individual AGESA special cases in the
linker script instead of whitelisting everything
remotely AGESA related in the Makefile.]
Change-Id: I866681f51a44bc21770d32995c281b556a90c153
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7306
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
TL;DR ASCII art that sucks, remove it.
Change-Id: I424736b040fe019bba6155de76903225a266760d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7641
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Since this board does not provide a PIRQ table.
Change-Id: I1068dd99c4cecdd2113484fe24ae2bb86a058cb3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7644
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This makes lzmadecode 64-bit clean (I hope).
It also cleans up a few other nits.
Change-Id: I24492e9f357e8d3a6de6abc351267f900eb4a19a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7623
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
We don't actually use nor support these as our implementation
makes use of gcccar.inc. They maybe useful as a reference for
history so lets keep them in version history.
Change-Id: I388251dead449dde14283e57db39c37982d947b2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7596
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Otherwise checksum may not work correctly on early stages.
For compatibility with old bootblocks also enable it early in romstage.
Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Embedded Controller sits behind the LPC bridge and so needs
LPC decodes to be enabled.
Remove the LPC decode enable out of agesawrapper.c. The enable
is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)'
which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3
LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined.
Change-Id: Ia487d21faa0fceb2557dbce14ef8822116fada91
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7628
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
The Embedded Controller sits behind the LPC bridge and so needs
LPC decodes to be enabled.
Remove the LPC decode enable out of agesawrapper.c. The enable
is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)'
which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3
LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined.
Change-Id: I0b4e99cc0d6f89f0261f26ee61b8c175a373c730
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7625
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Enabling MMCONF PCI-e configuration access should be done before
console_init(). This will likely move further to bootblock one day.
Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7163
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Originally from commit 4ca72139 move this code now from
cpu/ to northbridge/.
Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7603
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.
Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7602
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a
common file for now and split eventlog parser to a separate file.
Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7155
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.
Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7601
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may
fall through critical failures.
Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7154
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
GPP config from devicetree.cb is not implemented for fam15tn/fam16kb.
Also only for asus/f2a85-m the configuration value matched the actual
programming.
Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7600
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Change-Id: I2adb5a8fe2cede988cc6fdef5ff81da86d267175
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7624
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
change config flags for cpu and mainboard bootblock initialization.
Tested on a20/cubieboard2.
Change-Id: I2a1019c2881bc7aada15322841204992d0106453
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7188
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
changes config flags for cpu and mainboard bootblock initialization.
Tested on a20/cubieboard2.
Change-Id: I753aa60ff66de9a3352a3a0759e4d0be9d8ae1c7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7187
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.
All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).
Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
No need to keep that just because x86 has one
extra linking step.
Change-Id: Iffdbf64e0613f89070ed0dfb009379f5ca0bd3c1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7611
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
No need to mark Makefiles, C files or devicetrees
executable.
Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This is based on LENOVO X230 port.
Board boots to linux via SATA or USB.
All USB ports are working.
Remaining Issues:
1. Native raminit sometimes fails with "timC write discovery failed"
even without changing the ram configuration. I suggest
altering the native raminit code so that it reboots
if that message appears to give a chance for the
boot process to recover.
2. VGA does not work.
Native graphics initialization only supports LVDS and
the VGA Option ROM still hangs when run in SeaBIOS.
Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7341
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is gcc specific, not necessary-everywhere-but-on-clang.
Change-Id: Ie02587bd41c856cbf730ea2f72f594a20b5fefbe
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7609
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
No need to pass calls through gcc in one case and
directly to binutils in another. Just always call
binutils.
Change-Id: Icf9660ce40d3c23f96dfab6a73c169ff07d3e42b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7610
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's a portable and generic way to halt the system.
Useful when waiting for the platform to reset.
Change-Id: Ie07f3333d294a4d3e982cbc2ab9014c94b39fce0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It also tells the compiler that we never leave here.
Change-Id: I824569efd46b577588387b29fc7781abf8c42385
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7579
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Minor change in Kconfig to remove "/" defined in
FSP_VENDORCODE_HEADER_PATH and update the path in Makefile.inc.
Change-Id: Ic19ab9560aabe307d45b560f167874383cc920aa
Signed-off-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-on: http://review.coreboot.org/5894
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Edward O'Callaghan