Commit graph

152 commits

Author SHA1 Message Date
Rudolf Marek
c4369536da Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well.
The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some  simple patch which follows for asrock.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 19:59:13 +00:00
stepan
836ae29ee3 first round name simplification. drop the <component>_ prefix.
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 05:42:47 +00:00
Tobias Diedrich
ba9f0b30fb With low serial console loglevels a pcie graphics card is not
initialized properly because the pcie link takes some time to come
up.

I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
and higher only boot looks like on my system (with pcie printks set
to BIOS_ERR so they show up):

|Device error
|Device error
|PCI: 00:02.0 PCIe link up after 35800 us
|PCI: 00:03.0 PCIe link up after 12900 us
|PCI: 00:03.1 PCIe link timeout
|PCI: 00:03.2 PCIe link up after 32000 us
|APIC: 00 missing read_resources
|I2C: 01:50 missing read_resources
|I2C: 01:51 missing read_resources
|I2C: 01:52 missing read_resources
|I2C: 01:53 missing read_resources
|Start bios (version pre-0.6.2-20101025_023503-nukunuku)

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-24 19:57:08 +00:00
Rudolf Marek
bcaea142f3 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)

3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.

4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.

I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 22:00:52 +00:00
Stefan Reinauer
abc0c85516 Printing coreboot debug messages on VGA console is pretty much useless, since
initializing VGA happens pretty much as the last thing before starting the
payload. Hence, drop VGA console support, as we did in coreboot v3.

- Drop VGA and BTEXT console support. 
  Console is meant to be debugging only, and by the time graphics comes up
  99% of the risky stuff has already happened. Note: This patch does not remove
  hardware init but only the actual output functionality. 

  The ragexl driver needs some extra love, but that's for another day
- factor out die() and post()
- drop some leftover RAMBASE < 0x100000 checks.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: QingPei Wang<wangqingpei@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 08:09:50 +00:00
Uwe Hermann
d773fd370a Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 20:23:08 +00:00
Patrick Georgi
9bd9a90d6a Unify DIMM SPD addressing. For Geode, change the
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).

abuild tested.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 10:31:00 +00:00
Tobias Diedrich
8520e01af7 Linux also needs the MMCONF area to be reserved either in E820 or
as an ACPI motherboard resource or it will not enable MMCONFIG
and the extended pcie configuration area will be unaccessible:

This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).

Ruik: I extended the flash range to 16MB (This is what VT8237S can decode)
Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete)

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz> 




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 11:30:50 +00:00
Tobias Diedrich
8a71dcd321 The only southbridge having a pirq_assign_irqs function (needed for
CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
Add one for vt8237 too.
Setting up the pci routing is important in case you want to boot DOS,
OSes that don't support ACPI or MP tables and ROMs for add-in storage
controllers may depend on this too.
TODO: Fix the 4 routing links limitation in
      src/arch/i386/boot/pirq_routing.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 10:58:13 +00:00
Uwe Hermann
2e9323e5be Add a target for the ASUS A8V-E Deluxe (trivial).
For now this is a plain copy of the ASUS A8V-E SE target, I reported
that most of the code also works (sort of) for the ASUS A8V-E Deluxe
a long while ago, see

  http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html
  http://www.coreboot.org/ASUS_A8V-E_Deluxe

There will be a bunch of changes necessary though (devicetree.cb, mptable.c,
ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target.

Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as
otherwise there will be build errors if the MAINBOARD_PART_NUMBER string
gets too long (as is the case for "A8V-E Deluxe"). The error is:

  ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps
  section .romstrap loaded at [00000000ffffff80,00000000ffffffd3]

(both with stock Debian gcc and with xgcc)

Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 21:48:14 +00:00
Tobias Diedrich
5d72eb5e8e Move cable detect logic to a weak function in vt8237r_ide.c and add
an override function in m2v/mainboard.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 14:17:29 +00:00
Tobias Diedrich
d441afda91 Currently the
cablesel |= (sb->ide0_80pin_cable << 28) |
                    (sb->ide0_80pin_cable << 20) |
                    (sb->ide1_80pin_cable << 12) |
                    (sb->ide1_80pin_cable << 4);
in vt8237r_ide.c ends up doing
	cablesel |= 0xfffffff0;
(with both bits set to 1) which is probably not the intended result. ;)

After a short discussion on irc the consensus was to change the
bitfields to u8 as it's probably not worth it using bitfields here.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 14:12:14 +00:00
Tobias Diedrich
1dcd26cddc Add VT8237A id to src/southbridge/via/vt8237r/bootblock.c
I missed this one since it was working anyway, since
"The LPC BIOS ROM is always accessed when ISA addresses
 FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet)
And the rom I use for testing is smaller than this 512KB default range.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11 05:12:01 +00:00
Tobias Diedrich
e080bcabd0 Add pci id and ops for VT8237A SATA controller
Needed to change class from raid to ide so seabios can boot from it.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11 05:08:33 +00:00
Tobias Diedrich
a151f27cb0 Depends on the "Introduce get_vt8237_lpc() function" and
"Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches.

This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c
I ran some tests and apparently both the

|			/* So the chip knows we are on AMD. */
|			pci_write_config8(devctl, 0x7c, 0x7f);

and

|	/*
|	 * Allow SLP# signal to assert LDTSTOP_L.
|	 * Will work for C3 and for FID/VID change.
|	 */
|	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);

in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
fid/vid change error on boot.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 19:17:18 +00:00
Tobias Diedrich
7714cd0515 This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.c
Depends on the "Introduce get_vt8237_lpc() function" patch.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:57:10 +00:00
Tobias Diedrich
e165d41b08 Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too.
I broke this out into a seperate part to keep the other half as
straight-forward as possible.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:51:13 +00:00
Tobias Diedrich
ef2928e708 Instead of duplicating the pci_locate_device calls multiple times,
add a get_vt8237_lpc() function.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>

Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:46:13 +00:00
Tobias Diedrich
6953eeb342 Add pointer to public PCIe bridge documentation on
http://linux.via.com.tw/ as VX800 seems to be compatible.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:37:39 +00:00
Tobias Diedrich
113b29f3c1 This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
and vt8237r_lpc.c.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:28:34 +00:00
Tobias Diedrich
2210135468 This adds the VT8237A LPC device id and the pci_driver struct in
vt8237r_lpc.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:20:32 +00:00
Uwe Hermann
305e8861d6 Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04 18:33:42 +00:00
Tobias Diedrich
b54585244b Need to clear downstream read cycle retry bit, or the bus scan will
hang.  Also need to set lane config to 0x00 for autonegotiation.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02 21:24:29 +00:00
Tobias Diedrich
d50b43a128 This adds pci device ids and pci_driver structs for the K8T890 CF
variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for
subfunctions 3 and 7.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02 20:54:37 +00:00
Uwe Hermann
74d1a6e8a1 We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 17:34:08 +00:00
Patrick Georgi
8463dd9db0 Rename build system variables to be more intuitive, and
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs

The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y

Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.

Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 16:55:02 +00:00
Kevin O'Connor
c3c9b01efb Code must not access the smbus registers before the RTC power well is
ready (PSON gating).  Some boards boot faster than this power well
stabilization, and thus see bad data when accessing the smbus
registers.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-08 11:00:25 +00:00
Jens Rottmann
0d11f2db1f CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
chipset support it.  But this involves a long list of 'depends', which you have
to remember updating manually.  Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 12:46:02 +00:00
Corey Osgood
f97654833a Clarify a comment on an old hack, remove the call to early_mtrr_init
that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-01 17:20:20 +00:00
Corey Osgood
43110f5403 Update my old, no longer active email addresses
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-01 02:33:42 +00:00
Stefan Reinauer
6f57b514cb Fix all warnings in the tree
(does not fix the cmos.layout race yet)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-08 16:41:05 +00:00
Myles Watson
7eac4450b3 Always enable parent resources before child resources.
Always initialize parents before children.

Move s2881 code into a driver.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-17 16:16:56 +00:00
Stefan Reinauer
42e5f649ed The interrupt controller lives at I/O 0x4d0/0x4d1.
However on these platforms we were causing a resource conflict by
letting the resource allocator start allocations at 0x400.
Change the constraints to start at 0x1000 so we avoid allocating over
LPT ports (0x778-0x77f), PCI (0xcf8-0xcff) and some other fixed
resources that might live down there (smbus base, acpi base,...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-09 19:07:19 +00:00
Stefan Reinauer
14e2277962 Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 06:56:47 +00:00
Rudolf Marek
53b0b50dc8 Fix the the build of r5494 on Asus A8V-E SE. The K8M890 and K8T890
were not treated separately until now. Fix it. Hope self ack is OK,
compiled tested locally.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 20:24:09 +00:00
Rudolf Marek
a3c10acaac Following patch changes the K8M890 VGA handling. It reverts the framebuffer size
to option based (similar what Uwe did) and also it uses GFXUMA to handle the
high_tables_start offset from memory top.

To satisfy the CMOS option users (Hi, libv!  ;)  I added also a possibility to do
that through CMOS.

Fixed printks to match the new style.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 15:21:18 +00:00
Rudolf Marek
7ba3c4fa09 Attached patch adds support for tinybootblock on VT8237* to decode whole flash
independent of strapping, making larger flashes work. We cannot walk anything
else than PCI bus 0 because HT is not setup yet.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23 20:58:13 +00:00
Stefan Reinauer
64d3baf982 zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22 13:18:09 +00:00
Stefan Reinauer
23836e2345 zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-15 12:39:29 +00:00
Stefan Reinauer
523ebd927d zero warning days. Move RAMTOP and RAMBASE together.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14 18:59:42 +00:00
Myles Watson
f4cc089f1e Remove few more warnings and some dead code.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14 16:50:16 +00:00
Stefan Reinauer
8816cdf311 geeesh! And this really compiles and even runs?
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14 16:39:30 +00:00
Stefan Reinauer
4154c668f2 zero warnings days. Down to under 600 different warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14 10:12:23 +00:00
Stefan Reinauer
eea66b7c35 no warnings day
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-07 15:32:52 +00:00
Stefan Reinauer
8a92684514 clean up age old via epia target.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-07 03:40:37 +00:00
Stefan Reinauer
c2d29415c3 switch some ROMCC boards back to ROMCC.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-07 02:06:53 +00:00
Stefan Reinauer
c51dc44bf2 "no warnings day"
last round for today. still warnings - help appreciated.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-07 01:44:04 +00:00
Stefan Reinauer
8f2c616dbc No warnings day, next round.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-06 21:50:21 +00:00
Stefan Reinauer
c9250c6740 device_t wants device/device.h
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-03 15:41:27 +00:00
Stefan Reinauer
3c8ac786c8 remove more warnings.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-03 13:33:01 +00:00