Commit Graph

35585 Commits

Author SHA1 Message Date
Kevin Chiu 3c9b35f8c3 mb/google/zork: add G2 TS support for berknip
Add G2 GTCH7503 HID TS support

BUG=b:159510906
BRANCH=master
TEST=emerge-zork coreboot
     boot with G2 TS, make sure G2 TS is functional

Change-Id: Id9ed5fc768459edc4660ddd6fbffb0b1973ce6d1
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-28 21:47:27 +00:00
Kevin Chiu 7c606eca05 mb/google/zork: update telemetry settings for morphius
update telemetry to improve the performance.

BUG=b:154863613
BRANCH=master
TEST=emerge-zork coreboot

Change-Id: Ia08259e81f360259f23ea0f9c5c128c9d0961322
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28 21:47:06 +00:00
Kevin Chiu b721f045e3 mb/google/zork: update DRAM SPD table for morphius
Add Samsung K4A8G165WC-BCWE x2

BUG=b:159418770
BRANCH=master
TEST=emerge-zork coreboot

Change-Id: I200a1074d3c9fe79a8a2c69f42b0612e745f36f5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28 21:46:59 +00:00
Kevin Chiu 858890765e mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL support
Add Samsung K4F8E3S4HD-MGCL DRAM support.
DRAMID: 0x8

BUG=b:145094527
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage

Change-Id: Ic450c4abebfeaed050a7b8fcae74b87a148dd5cd
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28 21:46:01 +00:00
Angel Pons 104c3e5f9b Makefile.inc: Simplify fsp submodule check
TEST=Building Asrock H110M using FSP from repo updates the submodule.

Change-Id: I25023af88d878353a04db456009249da67e41521
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-28 21:45:47 +00:00
Johnny Lin d4698d94af soc/xeon_sp/cpx: Define MSR PPIN related registers
These changes are in accordance with the documentation:
[*] page 208-209
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Tested on OCP DeltaLake with change
https://review.coreboot.org/c/coreboot/+/40308/

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-28 21:44:27 +00:00
Johnny Lin db654eae79 drivers/ipmi: Read more FRU data fields for Product and Board Info
Tested on OCP Tioga Pass

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ib05fdb34b2b324b6eb766de15727668ce91d2844
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40522
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28 21:43:59 +00:00
Tim Chen ba26aa8981 mb/google/faffy: Enable USB2 port6
Due to faffy has PL-2303 connect to USB2 port6(count from port0),
needs to enable it.

BUG=b:159760559
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
     boot on puff board

Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-28 21:43:45 +00:00
Felix Held 346f391642 mb/amd/mandolin: factor out eMMC GPIO pin mux setup
This also makes the calling of the eMMC GPIO mux setup function
conditional on PICASSO_LPC_IOMUX instead of AMD_LPC_DEBUG_CARD which
only makes the selection of PICASSO_LPC_IOMUX user-configurable.

Change-Id: Ic49a668f82fbc1b851c07d312b543d2889fe4734
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-28 14:20:11 +00:00
Felix Held 664ba9767d mb/amd/mandolin: factor out port descriptors from mainboard.c
Change-Id: Ia2101cc0bae0d68cea1954424d18833aa22670c6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28 14:17:34 +00:00
Felix Held 42b0e8f438 soc/amd/picasso/soc_util: rework reduced I/O chip detection
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort
connectivity. While Dali can either be fused-down PCO or RV2 silicon,
Pollock is always RV2 silicon.

Since we have all boards using this code in tree right now,
soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku().

Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28 14:16:36 +00:00
Furquan Shaikh fa8b75fb17 gpio_keys: Allow boards to configure different wakeup routes
This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.

Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.

Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.

BUG=b:159942427

Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-28 05:22:41 +00:00
Angel Pons 490473edec sb/intel/i82801jx: Use pmutil.h definitions
Also drop now-redundant definitions and include headers where needed.

Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.

Change-Id: I2fb46bb04d96df5e8261f49e0fd4d88eedca6084
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42659
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 23:37:30 +00:00
Angel Pons e1a616cf99 sb/intel/i82801ix: Use pmutil.h definitions
Also drop now-redundant definitions and include headers where needed.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 23:37:19 +00:00
Angel Pons b60aeca26c sb/intel/i82801jx: Drop `p_cnt_throttling_supported`
The three mainboards using this southbridge do not support it.

Change-Id: I006f1ec26c40f7e2dfc2ddedb017278455368bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42655
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 23:36:34 +00:00
Angel Pons 547fe82cd0 sb/intel/i82801ix/fadt.c: Use pmutil.h definitions
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ib4cdeaaaf75818fff21acb628d198781b07aec80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42654
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 23:36:21 +00:00
Angel Pons 7c86f4a822 sb/intel/i82801jx/fadt.c: Use pmutil.h definitions
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.

Change-Id: I572a9da0cba5d23c48c4cb06de4bb75f65f5b0b0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2020-06-27 23:36:10 +00:00
Angel Pons f4bbea0f79 sb/intel/i82801gx/fadt.c: Align with i82801ix
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-27 17:39:24 +00:00
Angel Pons 741508bb3e sb/intel/i82801gx/fadt.c: Reorder statements
Change the order of the assignments to match that of i82801ix. This
changes the binary but the effective result should be the same.

Change-Id: Id720fce40e751295e629585d34017f10af2b5c7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42651
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 17:38:20 +00:00
Angel Pons 3fc2dc444e sb/intel/i82801gx: Move `acpi_fill_fadt` to fadt.c
At least i82801ix and i82801jx do this.

Change-Id: I7ff2459d82eb7933ed80180a69f0f323b8ecd25f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-27 17:38:11 +00:00
Angel Pons 9e5b432ef9 sb/intel/i82801jx/fadt.c: Align with i82801ix
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.

Change-Id: I13b972440459a62777ee2a4688d1d8af147d8921
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27 17:37:23 +00:00
Angel Pons 9cf2abd6f9 sb/intel/i82801jx/fadt.c: Reorder statements
Change the order of the assignments to match that of i82801ix. This
changes the binary but the effective result should be the same.

Change-Id: Ib190781f26f82f339eaf8039de459376ac0e3a5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27 17:37:05 +00:00
Angel Pons dd7fa543c5 sb/intel/i82801jx: Move `acpi_fill_fadt` to fadt.c
At least i82801ix does this.

Change-Id: Ic555ab17c2eca0399938d2842ca51628899c1544
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42637
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 17:36:39 +00:00
Angel Pons 22a6d11a54 mb/emulation/qemu-q35: Use common early SPI code
Tested, it still boots. It is unknown whether this has any effect on
emulated hardware, which is most likely not emulating SPI transfers.

Change-Id: I44397c46dc0715697ca8680f418888804e4ea7e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:31:13 +00:00
Angel Pons 5403423656 soc/intel/broadwell: Use common early SPI code
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:31:02 +00:00
Angel Pons 4c7ef81a23 sb/intel/lynxpoint: Use common early SPI code
Change-Id: I6c6fbed077d2f169736aee77af3783c847cf3a06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:30:48 +00:00
Angel Pons 8caa53133f sb/intel/ibexpeak: Use common early SPI code
Change-Id: Ib8cba1ae4fc269c925418965acf6956c1bfe0f79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:30:37 +00:00
Angel Pons 40783f2862 sb/intel/i82801jx: Use common early SPI code
Change-Id: If9efbde5939913b67852b377dd84cd4de1ec2718
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:29:48 +00:00
Angel Pons 298aa98b81 sb/intel/i82801ix: Use common early SPI code
Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:29:33 +00:00
Angel Pons cf39f89fd9 sb/intel/i82801gx: Use common early SPI code
Change-Id: I44de4698d062508dd24f37b37014e09d95726c71
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:29:23 +00:00
Angel Pons c9ee2c0323 sb/intel/bd82x6x: Use common early SPI code
Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27 17:29:02 +00:00
Angel Pons fc7bc54e34 sb/intel/common: Add early SPI code
All Intel southbridges with SPI perform this write. Put it inside a
function in common code. Use a different name to avoid a name clash.

As it is only one statement, make it inline so that it can be defined
on the header itself. It is only called once per southbridge anyway.

Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27 17:28:53 +00:00
Shelley Chen f183626b22 Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"
This reverts commit 1408798637.

Reason for revert: Causing backlight issues in device.  Will reland after more debugging to figure out the root cause.

BUG=b:159370566
BRANCH=None
TEST=boot up device and make sure when kernel is booted, backlight comes up.

Change-Id: I643854c6c805d262539bbb482808e8c322059a49
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-26 21:25:32 +00:00
Stefan Reinauer 4ab5ce1430 soc/rockchip: Use (Q) instead of @
This way make V=1 will tell you what it's actually doing.

Change-Id: I096bc2419e47a0b2a2454a792059464b27158cd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42818
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 21:13:33 +00:00
Felix Held 97716b18d7 mb/mandolin/devicetree: clarify that Ethernet devices are internal MACs
Change-Id: Ib7d696f4cc8f5fdcdf45e271b36664d085eb16d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 20:47:18 +00:00
Felix Held b212b67df1 mb/amd/mandolin/devicetree: disable unused internal ethernet controllers
Change-Id: Id4c7ec02f37b35bbc36d40bb937b962cc6413d17
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 20:46:15 +00:00
Stefan Reinauer 88e54e38d4 Fix up Docker paths to match jenkins nomenclature
Jenkins is calling its build nodes "agent". Reflect that in
the path names we use in configuration.

Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 18:56:48 +00:00
Felix Held ad977efa23 mb/google/zork/Kconfig: remove unused option IRQ_SLOT_COUNT
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which
it doesn't.

Change-Id: Ib5839a42f5133f5f84e1e1e4e587801b916ca571
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-26 16:14:47 +00:00
Felix Held 3d53d5397f mb/amd/mandolin/devicetree: add comment about chip behind GPP bridge 3
Change-Id: Ie1fcfb18a3ccf08c62210eec07d8965696f11da9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-26 16:08:12 +00:00
Christian Walter 23cdcb8bef mainboard/prodrive/hermes: Enable EIST in DeviceTree
Enable EIST option in the devicetree in order to make Windows aware of
using Intel CPU Turbo Technology.

Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-26 05:35:43 +00:00
Sridhar Siricilla 469dda3339 mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s).
This adds around ~5 seconds of delay during power cycle or global reset.
So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s
to minimize the delay.

Delay with Power Cycle or Global Reset:
Existing behaviour:
	S0->S5 -> [ ~5 seconds delay ] -> S5->S0

With the patch:
	S0->S5 -> [ ~2 seconds delay ] -> S5->S0

Also, correct the comment mentioned for PchPmSlpAMinAssert.
The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width
to 98ms not 2s.

Test=Verified on Hatch and Puff boards
BUG=b:158634281

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 00:15:04 +00:00
Jamie Ryu 154625bcb2 mb/google/volteer: Enable HECI interface
This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.

BUG=b:159615125
TEST=Build and boot volteer. Run lspci and check pcie device
     00:16.0 Communication controller: Intel Corporation Device a0e0

Change-Id: I68eb51c6a0af77982c060767993265764a2bc926
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-25 20:58:55 +00:00
Felix Held bc6aa222a6 mb/amd/mandolin: remove unused option IRQ_SLOT_COUNT
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which
it doesn't.

Change-Id: I76c098c7029ed9d797f6c4fb016eaa18854fadd3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25 20:36:11 +00:00
Felix Held cd36c52d78 mb/amd/mandolin: add missing Kconfig type to CBFS_SIZE option
Change-Id: Ia4226537d17bb3732086980fb4e8de6bd1eaedbb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25 20:36:01 +00:00
Kyösti Mälkki 79d41263d9 Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"
This reverts commit 4883252912.

Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as
it does not have the same view of memory space.

The prototypes xx_set/get_bar() are only valid for PSP as x86 cores
will use the constant mapping defined in <amdblocks/acpimmio_map.h>

The selected MMIO base address model depends of the architecture the
stage is built for and, to current knowledge, nothing else. So
the guards should have been with ENV_X86 vs ENV_ARM and not about
CONFIG(VERSTAGE_BEFORE_BOOTBLOCK).

For the ENV_ARM stage builds, <arch/io.h> file referenced in the
previously added mmio_util_psp.c file has not been added to the tree.
So there was some out-of-order submitting, which did not get caught
as the build-testing of mixed-arch stages has not been incorporated
into the tree yet.

The previously added file mmio_util_psp.c is also 90% redundant with
mmio_util.c.

Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 19:02:24 +00:00
Kyösti Mälkki e8afb0ee92 Revert "mb/pcengines/apu2: Update GPIO Reads & writes"
This reverts commit 87f9fc8584.

GPIO configuration is supposed to be abstracted using <gpio.h>
and the details of ACPMMIO GPIO bank hidden. This commit took
it the opposite direction.

Change-Id: Iacd80d1ca24c9d187ff2c8e68e57a609213bad08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42684
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 19:01:57 +00:00
Patrick Georgi 211e74e0f4 mb/amd/mandolin: Drop empty help text
kconfig complains.

Change-Id: I281e4faa53cad5677864305feb9162b598ae483e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25 16:59:25 +00:00
Patrick Georgi b9d0c0f7a3 util/abuild: Only update submodules once
Without this, each build will try to update the submodules. Not
necessarily a problem but git locks repos, creating spurious error
messages.

Change-Id: Iba20677d4b5f9365c92f7ed247ca56acb7d33b27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25 16:59:19 +00:00
Patrick Georgi c4b2f8c5d8 mb/amd/mandolin: Quote string in Kconfig that contains /
Newer versions of Kconfig require that.

Change-Id: I95f889d462ace1b912b5e6c7320973e8a826f3cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42773
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 14:32:27 +00:00
Sridhar Siricilla e40b9481e6 soc/intel/cannonlake: Add PchPmPwrCycDur to chip options
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur
from devicetree. The UPD determines the minimum time a platform will stay
in reset during host partition reset with power cycle or global reset.
This patch also ensures configured PchPmPwrCycDur value doesn't violate
the PCH EDS specification.

TEST=Verified on Hatch and Puff boards

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-25 13:43:01 +00:00