All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
into the socket directories, and remove it from the individual boards.
Do the same for Intel CPUs/sockets where all boards use CAR.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
W83627DHG:
- Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
that don't have their "enable" bit in bit 0 of the 0x30 register).
- Fix various I/O masks in the pnp_dev_info[] array as per
datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.
W83627EHG:
- Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
mostly implemented already, though).
- Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.
Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.
include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.
asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.
ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
>
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10
>
> Using the preprocessor will probably work too if iasl can do simple
> arithmetic (likely yes), I'll look into that.
BTW, my first idea was to use an acpi method that looks up pmbase in
the pci cfg space, but when I define a method like this:
Method(TEST, 2)
{
Return (Add(Arg0, Arg1))
}
I get:
|build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0,
|0x01, TEST(0xe400, 0x10), 0x06) {}
|Error 4096 - syntax error, unexpected PARSEOP_NAMESEG,
|expecting ')' ^
While using the builtin Add() directly works.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.
Tested:
Linux (poweroff, powerbutton event)
XP (poweroff, powerbutton event)
Abuild-tested
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This adds the board-specific parts for S3 support on the M2V board.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)
3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.
4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.
I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only to be used by developers
during bringup (and thus added manually to romstage.c and removed before
the board gets committed). This method seems to be preferred from what I
have heard on IRC / mailing list in the past.
Or, we add the ram_check() somewhere globally and allow the user to enable
it via menuconfig (possibly only if EXPERT is selected).
Either way, the current method of spreading the calls all over the place is
not really the way to go.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, remove some less useful comments, some dead code / unused functions.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The (0xa << 3) expression equals 0x50, i.e. DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).
abuild tested.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- s/Options.lb/devicetree.cb/
- s/Config.lb/devicetree.cb/
- s/cache_as_ram_auto.c/romstage.c/
- h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
the tree now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
deselected it, and very likely there won't ever be any
hardware that requires it deselected.
Keep the "selected" code path around, leading to no
functional change.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Updated patch with improved comments and small bugfix (use same
value for min and max on io resource).
While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the
easiest way to get both Linux and Windows happy, it is not quite correct
because reserved areas like APIC, MMCONF etc. ranges need to be excluded.
This is a proof of concept patch for the M2V board that dynamically creates a
ResourceTemplate() containing these in the SSDT and adds a corresponding
PNP0C02 device to the DSDT.
All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set
are added.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Added M2V-MX SE too.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as an ACPI motherboard resource or it will not enable MMCONFIG
and the extended pcie configuration area will be unaccessible:
This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).
Ruik: I extended the flash range to 16MB (This is what VT8237S can decode)
Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
http://tracker.coreboot.org/trac/coreboot/changeset/3953
Note that all corresponding DSDTs only ever check TOM2 against 0.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
Add one for vt8237 too.
Setting up the pci routing is important in case you want to boot DOS,
OSes that don't support ACPI or MP tables and ROMs for add-in storage
controllers may depend on this too.
TODO: Fix the 4 routing links limitation in
src/arch/i386/boot/pirq_routing.c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
make their defaults more obvious.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For now this is a plain copy of the ASUS A8V-E SE target, I reported
that most of the code also works (sort of) for the ASUS A8V-E Deluxe
a long while ago, see
http://www.coreboot.org/pipermail/coreboot/2008-March/031866.htmlhttp://www.coreboot.org/ASUS_A8V-E_Deluxe
There will be a bunch of changes necessary though (devicetree.cb, mptable.c,
ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target.
Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as
otherwise there will be build errors if the MAINBOARD_PART_NUMBER string
gets too long (as is the case for "A8V-E Deluxe"). The error is:
ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps
section .romstrap loaded at [00000000ffffff80,00000000ffffffd3]
(both with stock Debian gcc and with xgcc)
Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add a few more comments for the entries, and also change the devicetree.cb
files to the more compact and better readable variant with indentation level
of 2 spaces (instead of random mix of tabs and spaces).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
an override function in m2v/mainboard.c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The power-on default is 1.95V, set the DDR2 voltage to
standards-conforming 1.8V.
I also measured with a multimeter to confirm this.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
compatible. The extended cmos is accessed differently for AMD
and Intel RTCs. Not sure what if any OS cares about this distinction,
but non-Intel compatible seems like a safer way to report the AMD RTC.
Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
adjusts the Kconfig.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Rudolf
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use HAVE_ACPI_TABLES, HAVE_MP_TABLE, and HAVE_PIRQ_TABLE (instead of
GENERATE_*) in the board's Kconfig file, as all other boards do.
- Add missing HAVE_ACPI_TABLES/HAVE_MP_TABLE/HAVE_PIRQ_TABLE to boards
which have the respective files. The only exception: EPIA-M700 doesn't
select ACPI, as it doesn't have dsdt.asl. Added a comment that the user
is supposed to run the 'get_dsdt' script and edit Kconfig afterwards.
- Fix minor warning/error in
src/mainboard/msi/ms9652_fam10/acpi_tables.c,
now that the file is actually used.
- msi/ms9652_fam10: use #include instead of Include() as we usually do
now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- via/epia-n/mptable.c
- intel/eagleheights/mptable.c (commented out anyway)
- asus/p2b-d/mptable.c
- asus/p2b-ds/mptable.c
Some files still incorrectly contain some smp_write_ioapic() lines from
the original mptable utility target (Supermicro P4DPE), which has one
IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in
the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total.
However, none of the boards where this chunk of code is present has
multiple IOAPICs (and even if they had, the PCI devices where those are
located would probably be different anyway), so drop the incorrect
mptable.c contents.
Also drop the lines from the mptable utility, so that future mptable.c files
don't incorrectly inherit any of this stuff.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add "select IOAPIC" in the board's Kconfig file.
- Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two
CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
- Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c,
that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
are set.
- Rework ASUS P2B-DS mptable.c to fix a number of things:
- Convert it to use mptable_write_buses() as all mptable.c files should do.
- Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).
- Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
