Commit 0e7cf3d81d (soc/intel/alderlake:
Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5
SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the
SoC code bug required commit 044883615d
(mb/prodrive/atlas: Update correct SPD address) so that at least some
RAM would work. Now that the SoC code bug is fixed, the workaround is
no longer needed, so use the correct SPD address mapping.
TEST=Boot Atlas and verify that both memory channels work
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Building futility with OpenSSL 3.0 (default in latest Debian sid)
results in a number of warnings that various declarations have been
deprecated. Since we (and futility) have warnings as errors enabled,
this causes the building of futility to fail, killing the entire
coreboot build.
To work around this until futility is updated, turn off the warnings
about deprecated declarations.
Bug 243994708 has been filed to get futility updated. This workaround
can be removed when futility builds cleanly with the latest libsssl-dev.
BUG=b:243994708
TEST=Futility build doesn't fail with libssl-dev > 3.0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I54e27e09b0d50530709864672afe35c59c76f06e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Part of the content was on the same line as the heading.
Change-Id: Ia19487d80e9f004d59f96ff09e1f3de4f37c2f77
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67000
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC.
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The size of the input parameter to RESET_SYSTEM svc call is expected to
be 4 bytes. Fix the reset_system type from enum to uint32_t.
BUG=b:243476183
TEST=Build and boot to OS in Skyrim with PSP verstage. Trigger a system
reset to ensure that the system is reset successfully.
Change-Id: I6319a1dfc89602722c1c2b1c4ee744493ae8b33f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67117
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we have a PCIe root port without `ops_pci` or without
`get_ltr_max_latencies`, the parent device wouldn't be PCI.
Hence, check for a PCI path early.
Change-Id: I358cb6756750bb10d0a23ab7133b917bfa25988b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This workaround was added since reading the firmware version on Ti50
versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is
using Ti50 this old anymore, so remove the workaround.
BUG=b:224650720,b:236911319
TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the
firmware version:
[INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c
Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
For some reason GNAT 11 is not able to build GNAT 12, since there are
some Ada errors during the compilation. However, it works with GNAT 12.
So use GNAT 12 for the host toolchain instead.
Change-Id: If00a05a0c8564e624809268a12fae28261e380a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The qemu package doesn't exist anymore or it was renamed. Instead of
installing QEMU for all available architectures, install only the
packages which ship architectures that are supported by coreboot.
* qemu-system-arm
* qemu-system-misc (for RISC-V)
* qemu-system-ppc
* qemu-system-x86
Change-Id: Ifc46a8c9fcb1ab3c38dc8cbbc906882e93a719d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8188. Therefore,
we select this configuration to enable it.
TEST=build pass
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I14f3d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66280
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The emi.c is the same for MT8186 and MT8188, so we could move it to
the common folder and reuse it.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I225f1d07c973129172f01bf7f4d7f5d5abe7c02b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66328
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When MRC_SAVE_HASH_IN_TPM is selected, mrc_data_valid() uses the TPM
hash to verify the MRC cache data, not the checksum. However, we still
calculate the checksum when updating the cache. Skip this calculation
when MRC_SAVE_HASH_IN_TPM is selected to save boot time.
On nissa, this reduces boot time by ~14 ms:
Before:
3:after RAM initialization 854,298 (28,226)
After:
3:after RAM initialization 849,626 (14,463)
Note, the reason the calculation is so slow is that the new MRC data
lives in CBMEM, which is not yet marked as cacheable in romstage.
BUG=b:242667207
TEST=MRC caching still works as expected on nivviks. After clearing
the MRC cache, memory training happens on the next boot, but doesn't on
subsequent boots.
Change-Id: Ifbb75ecfa17421c0565aec1f3eb48d950244f821
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to
run fast calibration for MT8188 using blob.
DRAM fast calibration logs:
DRAM-K: Fast calibration passed in 19530 msecs
dram size (romstage): 0x200000000
TEST=Fast calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 0)
DRAM-K: Full calibration passed in 50176 msecs
TEST=Full calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Use common SoC drivers for DRAM calibration support.
- Remove emi.h because sdram_size() is already declared in
common/include/soc/emi.h.
- Add dramc_param.h and dramc_soc.h to prepare for implementation of
DRAM full calibration.
TEST=build pass
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2f88d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Doxygen was removed at the project level. Remove the doxygen Debian
package and make target.
Change-Id: Ib82ba7890e7f53357eeca318b5f844164747aecd
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67039
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables LID based shutdown requests.
Google/Rex platform receives a forced shutdown request while
booting to depthcharge due to EC wrongly detecting the LID is being
closed.
For now disable the LID based shutdown behaviour in depthcharge unless
the EC issue gets resolved.
BUG=b:243920003
TEST=Depthcharge no longer sees the force shutdown request now.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03e33ea4d04dc48331d1cf98c47786b2a184c258
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
If an inserted region's base wasn't aligned, the resulting range should
still cover the original end (original region's base + size) and not the
aligned-down base + size.
Change-Id: I8f1c9456d6dbab4fa868de5c93fa3656397e54c1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66607
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PNOT() should be called when the battery status changes, to give the SOC
an opportunity to handle it. This is in preparation for the low/no
battery boot changes.
This CL also updates the PNOT() comments to better match the name of the
function and why it's called.
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim
Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Clear the SMBIOS region before writing SMBIOS tables.
On librem_mini and librem_mini_v2, CBMEM allocations are offset by 4K
for reboots relative to the cold boot. This means the unused SMBIOS
region could contain the first 4K of the ACPI tables from the last boot
(including the signature), which prevents Linux from booting.
The CBMEM 4K offset appears to be due to FSP allocating memory
differently between cold boot and reboot, this appears to be normal and
causes the CBMEM base address to change.
It is not clear why Linux examines an ACPI signature found in this
region, but boot logs over serial confirm that it sees the corrupt
table. The table is supposed to be found just below 1M, and kernel
source appears to look in this region, but it is definitely finding the
corrupt table in CBMEM.
Normal cold boot:
[ 0.008615] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4)
[ 0.008619] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331)
[ 0.008624] ACPI: FACP 0x0000000099B4A2A0 000114 (v06 COREv4 COREBOOT 00000000 CORE 20220331)
[ 0.008634] ACPI: DSDT 0x0000000099B48280 00201F (v02 COREv4 COREBOOT 20110725 INTL 20220331)
...
Reboot with corrupt table:
[ 0.008820] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4)
[ 0.008823] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331)
[ 0.008828] ACPI: ???G 0x0000000099B4A2A0 20002001 (v00 ?G?$ 47020100 ?, 47020100)
[ 0.008831] ACPI: �y 0x0000000099B4A3C0 54523882 (v67 ?_HID? A�? 65520D4E al T 20656D69)
...
There are no specific errors but it returns to the firmware soon after,
presumably due to a fault. This appears to be so early in the boot
that panic=0 on the kernel command line has no effect.
Test: build/boot Librem Mini, Librem Mini v2 and reboot.
Change-Id: Ia20d0b30160e89e8d96add34d7e0e881f070ec61
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66377
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add FW_CONFIG probe for new audio sku:
ALC5682I + MAX98357
BUG=b:243474931
TEST=Boot to OS and verify audio devices are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I16af6cf4644c473034e184e95ff2038ca31b20de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67016
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as
per MTL processor EDS.
TEST= Able to build and boot RVP.
Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:239670216
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibc7116e8dc5367fd94d29aba36b91778d0c21e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Currently, memranges_steal() steals at the lowest possible address.
This is actually reflected by the test code that checks if the *base*
of the READONLY_TAG range changes. Furthermore, the test ends with the
memranges restored, so revise the comment on the final state.
Change-Id: Idef71ce464280c6805145f229de9e8913ba850bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The offset for Max Charge is located at 0x1a, so correct this in the
definitions and EC memory ACPI.
Change-Id: I92cc452d1189e62db78aed787f2de65fd5096564
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w.
BUG=b:236294162
TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
changes to reserve space for AMD_BIOS_SIG when
BIOS image is signed with RTMSignature.
Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This register has a 1MiB granularity. The lowest bit is a lock bit.
Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The define GPIO_PCH_WP needs to be mapped to GPP_H10 based on
the Rex schematics 24/6/2022.
TEST=Built and booted on Google Rex.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I2489c244bd4cbd9e10ed3db981a6e56a954b5e20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67083
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The define EC_SYNC_IRQ needs to be mapped to A17 based on
the Rex schematics 24/6/2022.
BUG=b:243781237
TEST=Successfully build rex and tested to ensure EC is now functional.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ib61ddc9f73dd7b817d3b990bef8f0169f7cafbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67082
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This change provides access to IOE through P2SB Sideband interface for
Meteor Lake TCSS functions of pad configuration and Thunderbolt
authentication. There is a policy of locking the P2SB access at the end
of platform initialization. The tbt_authentication is read from IOM
register through IOE P2SB at early silicon initialization phase and its
usage is deferred to usb4 driver.
BUG=b:213574324
TEST=Built coreboot and validated booting to OS successfully on MTLRVP
board. No boot hung was observed.
Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors p2sb_execute_sideband_access() to be able to
handle SBI operations in both SMM and non-SMM scenarios.
Prior to FSP-S operation being done, the IOE P2SB device will be
visible on the PCI bus hence, performing the SBI operation using IOE
P2SB doesn't involve unhide/hide operation.
Post FSP-S, the IOE P2SB device is hidden.
Additionally, SBI operations can't be performed as is. The only
possible way to send SBI is inside SMM mode and to do that, coreboot
needs to unhide the P2SB device prior to sending the SBI and hide
it post sending SBI.
As a result, the p2sb_execute_sideband_access() function has been
refactored to manage these cases seamlessly without users of the
p2sb_execute_sideband_access() actually being bothered about the
calling mode.
BUG=b:239806774
TEST=Able to perform p2sb_execute_sideband_access() function call in
both SMM and non-SMM mode without any hang/die.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Only 16 MByte of the SPI flash can be mapped right below the 4 GB
boundary.
In case of a larger SPI flash size, still only the 16 MByte region
starting at 0xff000000 can be configured as WRPROT and be reserved for
the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting
at address 0xfe000000 contain for example the LAPIC MMIO region, the
ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't
be configured as WRPROT. Reserving this region for the MMIO mapped SPI
flash would also result in an overlap with the MMIO resources mentioned
above.
In the case of a smaller SPI flash, reserving the full 16 MByte flash
MMIO region makes sure that the resource allocator won't try to put
anything else in the lower parts of the 16 MByte SPI mapping region.
To avoid the issues described above, always reserve/cache the maximum
amount of 16 MBytes of flash that can be mapped below 4 GB.
TEST=On boards with 16 MByte SPI flash chips, the resulting image of a
timeless build doesn't change with this patch. Verified this on Chausie
(Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena
(Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the
resulting image of a timeless build is different, but neither the
coreboot console output nor the Linux dmesg output shows any errors that
might be related to this change.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the poweron state of some of the WWAN GPIOs is the
asserted state, this patch fixes the poweron sequence so that the
WWAN module is always correctly powered on, in both cold and warm
reboot scenarios.
BUG=b:233564770
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Add legacy AMD reference boards
- Add Google AMD mainboards
- Add mailing list for code changes to all AMD sections
- Update people in AMD groups
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ibd8001f8e4cd667bf9223dc32bc33a5a1dc9e89f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake.
BUG=b:243734885
TEST=Built and booted on Google Rex. Verified the UPD value in MRC log.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Hook up ECT FSP UPD for Intel MeteorLake.
BUG=b:243734885
TEST=Built and booted on Google Rex. Verified the UPD value in MRC log.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch resolves the SoC programming dependency order where enabling
extended bios support requires MCHBASE to be enabled.
BUG=b:243693375
TEST=Able to boot from RW-A slot which is mapped to extended BIOS range.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early
GPIO tables.
BUG=b:243641061
TEST=Able to build rex image.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Voltage set based on standard configuration for each type.
TEST=build/boot google/skyrim, verify output in cbmem console log,
DMI type 17 table.
Change-Id: I9b1e68a9417e43cbb9c55b4c471664f3f9090342
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66981
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the frequency field is deprecated, print the max/configured MT/s
speeds instead.
TEST=build/boot google/skyrim, verify output in cbmem console log
Change-Id: Icee5af762ca37c3b2ec8c9a52a7f32fb848390b0
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Hook up newly-added method to convert from frequency to MT/s so that
boards which use (LP)DDR5 report their capability properly.
BUG=b:239000826
TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports
DRAM speeds correctly.
Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
As the frequency field in the SMBIOS type 17 table is deprecated,
we need to provide the maximum and configured speed in MT/s. Add
a method to convert from frequency to MT/s using a lookup table.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I0402b33a667f7d72918365a6a79b13c5b1719c0d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit adds support for LP5X SPDs. The SPD format is identical to
LP5 except that the memory type is set to 0x15 instead of 0x13. Since
they are essentially the same, LP5/5X parts share the same parts JSON
file and SPD directory. LP5X parts are distinguished by the optional
`lp5x` attribute. This commit also updates two existing LP5X memory
parts with the correct attribute.
BUG=b:242765117
TEST=Generated SPDs, verified that SPDs generated from LP5X parts match
their LP5 counterparts except for memory type byte.
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Separate the tasks that are required to be completed prior to building
edk2 into a prep recipe. This allows this to be used for building
different targets.
This also ensures that the COREBOOT toolchain is used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic4ae8ac4118a5747f38297d0fbf4cb53aa3b6d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66359
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Maximilian Brune