Use of device_t has been abandoned in ramstage.
Change-Id: I818f808e1cd8b156158251724352f8be6041030c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Replace the use of the old device_t definition inside
southbridge/amd/rs690.
Change-Id: Ief43393f62312bfe82e960faf56b1e2ec048f4ff
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16476
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.
In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.
This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.
Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/6147
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Remove some ASCII art past 80 columns.
Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The includes removed here were previously required for
struct lb_memory and lb_add_memory_range().
Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1391
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Use IORESOURCE_RESERVE to exclude the region from system RAM table.
Change-Id: I61b51022165e1304a41554f67af75b3089d892af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1393
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The code in rs690 or rs780 is always used with K8 or AMDFAM10
northbridge. Without GFXUMA, both of these set the same static value
indirectly using the variable uma_memory_base.
Make the register setting with immediate value, to remove the obscure
use of variable uma_memory_base.
Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1246
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Setting bit#21 in k8_f0#68 is part of the errata#169
which is handled in amdk8/coherent.c
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
If enabled, set up 0xe0000000..0xf0000000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up, so it's disabled by default.
Signed-off-by: Josef Kellermann<seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.
The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs
The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y
Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also fixes random whitespace issues, typos, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VGA ROM can not run. After make, run
> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom
to make the final image with vga bios.
The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
cant make test on.
## Index: src/southbridge/amd/rs690/chip.h
## ===================================================================
## --- src/southbridge/amd/rs690/chip.h (revision 4782)
## +++ src/southbridge/amd/rs690/chip.h (working copy)
## @@ -23,7 +23,6 @@
## /* Member variables are defined in Config.lb. */
## struct southbridge_amd_rs690_config
## {
## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */
## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
##
Don't apply above patch about rs690/chip.h before every board has been fixed.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
monitors.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.
Tested on dbm690t.
Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.
http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
(1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
In rpr 5.10.2, step 2, step 2.1 & step 2.6
(2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
instead of PCIEIND_P: 0x20.
In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
