Commit graph

1945 commits

Author SHA1 Message Date
Rob Barnes
f1ade489c8 ec/google: Use EC_HOST_EVENT_NONE
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.

BUG=b:184074997
TEST=Build and boot guybrush without error

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30 04:57:16 +00:00
Bernardo Perez Priego
43fd040226 mb/intel/adlrvp_m: Enable TCSS USB ports device path
This provide a more consistent mechanism to enable corresponding USB
TCSS port.

BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28 04:26:53 +00:00
Subrata Banik
0007fa96a1 soc/intel/alderlake: Update mainboard_memory_init_params() argument
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.

Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:55:12 +00:00
Subrata Banik
93632a9f1f mb/intel/sm: Skip FSP to program UART0
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit

Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 09:08:50 +00:00
Meera Ravindranath
f100e204ec mb/intel/adlrvp: Update Mainboard part number and Vendor
dmidecode output should match with the CrOS kernel updated string.

TEST=dmidecode grep "Manufacturer" = Intel Corporation
     dmidecode grep "Product name" = Alder Lake Client Platform

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 13:28:21 +00:00
Lean Sheng Tan
36941bd672 mb/intel/ehlcrb: Change default romsize and remove chromeos.fmd
Change the default rom size to 32MB and remove chromeos.fmd
because Chrome OS is not supported on EHL for now.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I49d9404eb901087037b5423a4a503c5271e14138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 06:03:54 +00:00
Bernardo Perez Priego
d4e19bfaba mb/intel/adlrvp_m: Remove DP_HPD 1 & 2 definition from devicetree
Due to latest corresponding UPD filling implementation, this is not
required.

This patch fixed the brokenness caused by
Commit hash b10afbd2e2.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-17 20:45:55 +00:00
Bernardo Perez Priego
b10afbd2e2 mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-06-17 17:05:58 +00:00
Angel Pons
d9cf794df4 broadwell boards: Use Haswell hostbridge.asl
Use hostbridge.asl from Haswell instead of Broadwell. Both files are
equivalent. Then, drop the now-unused hostbridge.asl from Broadwell.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 09:56:03 +00:00
Subrata Banik
8a18bd8500 soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.

TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.

Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-16 03:50:20 +00:00
Angel Pons
68d8357dab soc/intel/broadwell/pch: Replace ACPI device NVS
The same functionality can be provided through a runtime-generated SSDT.
The remaining parts of device NVS are removed in a follow-up.

Since the SSDTs are only loaded after the DSDT (if loaded at all), using
SSDT-provided objects outside method bodies is not possible: the objects
are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing
to this, the operation regions used by the _PS0 and _PS3 methods need to
be moved into the SSDT, as they depend on the SSDT-provided BAR1 values.

Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with
no errors and contains expected values. Linux does not complain either.

Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14 09:59:40 +00:00
Deepti Deshatty
193203f90b mb/intel/adlrvp: Add board id for MR DDR5 SKU
Add support for Maple Ridge DDR5 SKU with boardid 0x16

TEST=Verified build for ADL-P Chrome RVP
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-06-14 05:55:30 +00:00
Kyösti Mälkki
7742aedb0f mb/*/mptable.c: Use smp_write_pci_intsrc()
Split parameter '(devfn << 2) | intx' to 'devfn, intx'.

Formatted with 'spatch --max-width 96'

Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:15:11 +00:00
Kyösti Mälkki
860cff96dc mb/*/mptable.c: Replace magic constants
Read I/O APIC ID and version from hardware registers.

With coccinelle below, and minor fixups.

@ r1 @
expression E1, E2, E3, E4;
typedef u8;
@@

-smp_write_ioapic(E1, E2, E3, E4);
+u8 ioapic_id = smp_write_ioapic_from_hw(E1, E4);

@ r2 @
expression E1, E2, E3, E4;
@@

-mptable_add_isa_interrupts(E1, E2, E3, E4)
+mptable_add_isa_interrupts(E1, E2, ioapic_id, E4)

@ r3 @
expression E1, E2, E3, E4, E5, E6, E7;
@@

-smp_write_pci_intsrc(E1, E2, E3, E4, E5, E6, E7)
+smp_write_pci_intsrc(E1, E2, E3, E4, E5, ioapic_id, E7)

@ r4 @
symbol mp_INT;
expression E1, E3, E4, E5, E6, E7;
@@

-smp_write_intsrc(E1, mp_INT, E3, E4, E5, E6, E7)
+smp_write_intsrc(E1, mp_INT, E3, E4, E5, ioapic_id, E7)

Change-Id: I20799f0c09cf0292661e1f3cb93373b2c68b7314
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14 05:14:06 +00:00
Kyösti Mälkki
dea42e011a cpu/x86/lapic: Replace LOCAL_APIC_ADDR references
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.

Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11 07:11:43 +00:00
Andy Pont
d2f52ff053 soc/intel/tigerlake: Move MAX_CPUS to Kconfig
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS
value within src/soc/intel/*/Kconfig.

Move the definition there for Tiger Lake and remove from the mainboard
Kconfig files.

Signed-off-by: Andy Pont <andy.pont@sdcsystems.com>
Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10 05:37:18 +00:00
Sumeet Pawnikar
aa49608a2b soc/intel/adl: Add SKU specific power limits support
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.

BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
 CPU PL1 = 28 Watts
 CPU PL2 = 64 Watts
On adlrvp (682):
 CPU PL1 = 45 Watts
 CPU PL2 = 115 Watts
On brya (282):
 CPU PL1 = 15 Watts
 CPU PL2 = 55 Watts

Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-06-07 19:02:02 +00:00
Angel Pons
427e435b9b sb/intel/bd82x6x: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.

Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 11:37:17 +00:00
Angel Pons
0caf80d8aa bd82x6x boards: Drop redundant c2_latency
If unspecified, chipset code already uses 101, and 0x65 == 101.

Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:53:39 +00:00
Subrata Banik
66a5d40a5d mb/intel/sm: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function.  Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.

TEST=Dump devicetree device enable list without and with this CL, no
difference observed.

Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-05 19:54:53 +00:00
Subrata Banik
2cfb83fcf3 mb/intel/adlrvp: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function.  Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.

TEST=Dump devicetree device enable list without and with this CL, no
difference observed.

Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05 19:54:43 +00:00
Subrata Banik
c000057aa6 mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb
Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05 16:49:38 +00:00
Lean Sheng Tan
c6c54439f8 soc/intel/elkhartlake: Update FSP-S storage related configs
Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04 03:48:31 +00:00
Lean Sheng Tan
9420e2847e soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
Further add initial Silicon UPD settings for:
- PCIe root ports
- USB

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 03:47:51 +00:00
Lean Sheng Tan
e9ee4390a5 soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI

This CL also enables HECI 1 in devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04 03:45:43 +00:00
Bernardo Perez Priego
ea8a6a2ba2 mb/intel/adlrvp_m: Enable LTR for PCIE
BUG=none
TEST=Use command $ lspci -vv
     LTR+ is listed on DevCtl2

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492
Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01 23:03:35 +00:00
Tan, Lean Sheng
09133c78dd soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
Add Silicon upd settings for LPSS (GSPI/UART/I2C).

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-01 05:58:39 +00:00
Bora Guvendik
3585dc5be4 mb/intel/adlrvp_m: add ec device entry to devicetree
TEST=Boot to OS and verify acpi tables.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30 20:18:42 +00:00
Tan, Lean Sheng
33f8fc698c soc/intel/elkhartlake: Update FSP-M UPD related configs
Upload the FSP-M UPD configs. This CL also updated the chip.h and
devicetree.cb with the relevant variables and configs.
This CL also updated the GPIO related settings (PMC & SD card) in
devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-30 20:15:42 +00:00
Bernardo Perez Priego
e3a079cff8 mb/intel/adlrvp_m: Disable unused TBT ports from device tree
These PCIe and DMA ports are not available for adlrvp_m.

BUG=none
TEST=Boot device

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28 04:53:50 +00:00
Tan, Lean Sheng
6948df1f4f mb/intel/ehlcrb: Upload EHL CRB GPIO configs
Initial upload of the GPIO configs for EHL CRB.
This CL also includes the UART GPIO configs in early GPIO table.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-28 04:44:06 +00:00
John Zhao
7e982b1dd9 mb/intel/shadowmountain: Update mainboard properties
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.

BUG=b:186521258
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 21:59:33 +00:00
John Zhao
a7f8fb59e5 mb/intel/shadowmountain: Remove power_gpio from baseboard
Along with upstream kernel for Retimer firmware update, coreboot defines
power control for each DFP respectively under host router. This change
removes the power_gpio from the baseboard. Individual DFPx power_gpio
will be added once the dependent definition is complete.

BUG=b:186521258
TEST=Build image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 21:58:36 +00:00
Angel Pons
c56c723deb mainboard: Use decimal for device lapic 0x0 on
Most boards use `device lapic 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.

Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18 11:42:48 +00:00
Angel Pons
bceea67461 mainboard: Use decimal for device domain 0x0 on
Most boards use `device domain 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.

Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18 11:42:36 +00:00
Angel Pons
d2489ee712 mainboard: Use decimal for device cpu_cluster 0x0 on
Most boards use `device cpu_cluster 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.

Change-Id: I083c8f8e9b38ddcc217dc8bf17ae3c9473ba77e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18 11:42:21 +00:00
Deepti Deshatty
8e7facf343 soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during
silicon init.
Type-c aux lines DC bias changes are propagated from tigerlake
platform.

TEST=Verified superspeed pendrive detection on coldboot.

Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 10:09:04 +00:00
Maulik V Vaghela
2b97ea153a mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ec
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps
rebooting with hash error.

Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-18 10:00:35 +00:00
Bora Guvendik
39736253d5 mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12 08:01:19 +00:00
Maulik V Vaghela
01ecb77ef6 mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.

BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board

Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-12 00:51:11 +00:00
Angel Pons
a5c829d4e1 mb/intel/dg41wv/devicetree.cb: Fix up whitespace
Remove a blank line and correct the indentation of another line.

Change-Id: Id66f0a847720713c1d3445ac70a9e075228dfe88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54017
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11 12:52:41 +00:00
Angel Pons
94bbf0efc8 skylake DT/HALO mainboards: Drop SaGv setting
SaGv is only supported on ULT/ULX hardware.

Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-07 20:59:26 +00:00
Maulik V Vaghela
ce6fdd458b mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.

Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07 09:32:26 +00:00
Bernardo Perez Priego
e73e1ce9de mb/intel/adlrvp_m: Disable Type-C xDCI
Disabling this pci 0d.1 device since it is not required.

TEST= Boot to OS.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52744
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 14:36:01 +00:00
Anil Kumar
88dd4f705a mb/intel/adlrvp: Enable support for Chrome OS mode switches
Branch=none
Test=build and boot ADL-M RVP. Test recovery mode using servo command
dut-control power_state:rec

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52614
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 20:27:13 +00:00
Arthur Heymans
c8116f6ea0 nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.

Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 11:47:15 +00:00
Usha P
24f7d2e80f mb/intel/shadowmountain: Enable early EC Software Sync
BUG=None
TEST=Build and boot to OS on shadowmountain. Ensure that the
EC Software Sync is complete.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-05-05 11:44:44 +00:00
Maulik V Vaghela
e46e740f91 mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd
While building adlrvp board with chromeos.fmd and adding all chromeos
related artifacts, RO region is running out of space. Also, we need
to increase RW region size to accommodate all binaries and artifacts.
Aligning chromeos.fmd with Brya will help in solving this issue, thus
aligning chromeos.fmd with Brya.

BUG=b:184997582
BRANCH=NONE
TEST=Code compiles fine and able to boot adlrvp platform

Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 07:42:51 +00:00
Francois Toguo
7da1c1732a mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOs
This CL configures TCSS, BT and WiFi related GPIOs based on schematics.

BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29 20:19:18 +00:00
Anil Kumar
b46ec389bd mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP
This patch adds UART0 config in early GPIO table

Branch=None
Test=Build coreboot and boot on ADLRVP-M board. Check UART logs

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:24:41 +00:00