Commit graph

3044 commits

Author SHA1 Message Date
Julien Viard de Galbert
f528195bdf soc/intel/denverton_ns: re-factor HSIO configuration
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.

Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:32:53 +00:00
Jonathan Neuschäfer
67b3268fac RISC-V boards: Stop using the config string
RISC-V is moving towards OpenFirmware-derived device trees, and the old
functions to read the config string don't work anymore. Use dummy values
for the memory base and size until we can query the device tree.

Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:31:00 +00:00
Marshall Dawson
3727708aef soc/amd/common/psp: Require PSP PCI definition in SOC
Remove the definition for the PSP PCI device from the common PSP
code.  Any APU using this source should have its own definitions,
and this allows for the device to move within the config space.

Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06 22:21:50 +00:00
Aaron Durbin
4239a1671c soc/amd/stoneyridge: consolidate addresses in iomap.h
Take the existing scattered around address space defines
and put them in iomap.h.

Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-06 16:11:23 +00:00
Aaron Durbin
733ad92c65 soc/amd/stoneyridge: start header file for iomap
Create a new header file, iomap.h, which serves as a single
place for providing the address space definitions. Remove
the amd_defs.h file that had a single define in it.

Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-06 16:10:45 +00:00
Aaron Durbin
3173d4444f soc/amd/stoneyridge: don't open code known literals
We have macros for register addresses. Use it for MMIO_CONF_BASE
instead of duplicating a literal again.

Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:57 +00:00
Aaron Durbin
174abc5180 soc/amd/stoneyridge: fix incorrect constants in macros
Hex constants need '0x' prefix. Clearly these weren't being used,
but they should be fixed properly.

Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:48 +00:00
Aaron Durbin
426dc8e827 soc/amd/stoneyridge: remove superfluous NULL field initialization
By definition in C, fields that are not explicitly initialized will
be zero'd out. Therefore, remove the redundant struture field
initialization.

Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:41 +00:00
Aaron Durbin
8dd4006161 soc/amd/common: remove superfluous NULL initializers on globals
Global variables that are unitialized in C programs reside
in the .bss section. By definition, this section is cleared
to 0. Therefore, remove the explicit NULL initialization because
it's completely unnecessary.

Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:35 +00:00
Aaron Durbin
e3f7d44d3b soc/amd/common: remove use of LibAmdMemFill()
memset() exists for a reason. There's 0 reason to duplicate the
functionality but add extraneous parameters that do nothing. This
is just poor coding practices. Remove LibAmdMemFill() usage.

BUG=b:62240746

Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:28 +00:00
Lijian Zhao
7b2d1ae299 soc/intel/cannonlake: Add DSP support
Add dsp driver support for cannonalake, especially the scan_bus function
of Audio controller required.

TEST=N/A

Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04 00:44:03 +00:00
Lijian Zhao
9bb684a0ec soc/intel/cannonlake: Install common i2c
Add common i2c support for cannonlake.

TEST=N/A

Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 00:42:00 +00:00
Hannah Williams
96939ae694 soc/intel/apollolake: Fix nhlt blobs path for GLK
Change-Id: Iabea32654918575c952857145ee6edb165899baf
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04 00:38:25 +00:00
Jonathan Neuschäfer
0781cbe1d3 sb and soc: Enforce correct offset of member "chromeos" in global_nvs_t
The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos").  Avoid this bug in the future.

Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04 00:33:26 +00:00
Lijian Zhao
ebd7c44d7b soc/intel/skylake: Update coding style for i2c
From comment from https://review.coreboot.org/#/c/22238/, the coding
style need to be update.

TEST=N/A

Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04 00:30:38 +00:00
Lijian Zhao
44e2abf38f soc/intel/apollolake: Move to common dsp driver
Move dsp driver implementation to common dsp driver.

TEST=Boot up and check dsp driver loaded or not in OS.

Change-Id: Ia2be1c9f18e0e110600bd56a0b6cb8d40ca5e01f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:27:24 +00:00
Lijian Zhao
7b6a8cec9b soc/intel/common: Add common dsp driver
Audio DSP pci driver can be common across different platforms.

TEST=N/A.

Change-Id: Ia9206657864b8795799dc71af54996017c1eec57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04 00:26:54 +00:00
Marshall Dawson
5bb0d75566 amd/stoneyridge: Clarify SPD structure in chip.h
Add #define values and clarify the spdAddrLookup array.

Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-03 18:40:26 +00:00
Paul Menzel
8890dccb23 soc/mediatek/mt8173: Remove cast of NULL* to void *
`NULL` already has that type in coreboot.

```
src/include/stddef.h:#define NULL ((void *)0)
```

Change-Id: I73aeaef178be8779020c436732952aa732e90c46
Reported-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 16:03:30 +00:00
Paul Menzel
11015342b4 soc/intel/quark/spi: Correct conversion specifier
Use the correct conversion specifier for `size_t` to fix the error
below.

```
from src/soc/intel/quark/spi.c:18:
src/soc/intel/quark/spi.c: In function 'xfer':
src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \
   of type 'long int', but argument 3 has type 'unsigned int' \
   [-Werror=format=]
   printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data));
                    ^
```

Found-by: gcc (Debian 7.2.0-8) 7.2.0
Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03 15:22:06 +00:00
Paul Menzel
fa7d2a07fe soc/intel/common/block/lpc: Make integer literal unsigned long
```
    CC         romstage/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the '<<' expression is undefined
                alignment = 1 << (log2_ceil(window_size));
                            ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```

Change-Id: I9bf2283e23ca7739a7e5b0993d9b6034ea28fb78
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03 07:54:01 +00:00
Paul Menzel
64e83409a1 soc/intel/common/block: Make integer literal unsigned long
Fix the warning below by making the integer literal unsigned.

```
    CC         bootblock/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \
'<<' expression is undefined
                alignment = 1 << (log2_ceil(window_size));
                            ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```

Found-by: Clang static analyzer scan-build
          (clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation)

Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03 07:52:52 +00:00
Paul Menzel
57ea9b41e7 soc/mediatek/mt8173/Kconfig: Use plural of *message*
Change-Id: I07e70f7e4b3c1244559b834a91ac143cd36f75bd
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:42:07 +00:00
Paul Menzel
0d0be39bb9 soc/mediatek/mt8173: Remove unneeded header inclusion
Change-Id: If2135ca74de5e9336349bdb0e034f484b7e3dd26
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:41:24 +00:00
Paul Menzel
22db82d91d soc/mediatek/mt8173: Fix typo in debug message
Change-Id: I431a23129af8744f51edfee450f3c6e5cb0f3898
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:41:00 +00:00
Paul Menzel
454cfa00b9 soc/mediatek/mt8173: Correct multi-line comment format
Make the format of two multi-line comments compliant with the coding
style.

Change-Id: I8bc7b1eb175957b76ca19acdcb29b06ae86429b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:40:55 +00:00
Mario Scheithauer
545593d62c soc/intel/apollolake: Add APL CPU device ID
Add Apollo Lake CPU device ID for E0 stepping.

Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 07:14:20 +00:00
Mario Scheithauer
d0e51330ed soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio
If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.

Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 07:11:37 +00:00
Marshall Dawson
383ef6eef8 amd/stoneyridge: Remove duplicate LPC decode setup
Delete the LPC I/O decode configuration from fixme.c.  This code is
superseded by early_setup.c.

Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:59:08 +00:00
Marshall Dawson
7d06a3fe5a amd/stoneyridge: Add pci_dev macros
Add #defines that will allow easy use of PCI devices across stages.
Future work can convert soc/amd/stoneyridge to use these and clean
up the DEV_D18F4 macro still in place.

Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:58:59 +00:00
Marshall Dawson
cbb78cd752 amd/stoneyridge: Add definitions for various NB registers
Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.

Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:58:44 +00:00
Marshall Dawson
14ef26b07b amd/stoneyridge: Consolidate duplicate comment
Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:58:34 +00:00
Marshall Dawson
7a694318e5 amd/stoneyridge: Add definition for HPET to southbridge
Add #define values for the HPET device.  In Stoney Ridge, the base
address is fixed and cannot be relocated.

Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:56:12 +00:00
Bora Guvendik
d2c636582d soc/intel/cannonlake: Use SCS common code
This patch uses common SCS library to set up sd card.

Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 17:42:30 +00:00
Kane Chen
66f1f382cd intel/common/smbus: increase spd read performance
This change increases the spd read performance by using smbus word
access.

BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm

Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 15:49:55 +00:00
Marc Jones
6e70d67824 soc/amd/common: Add weak call for platform PCIE slot reset
Since it is fairly uncommon, add a weak call that may be done by
the platform if it has the support.

BUG=b:66690176
BRANCH=none
TEST=coreboot builds.

Change-Id: I50008da6f85039a428184bf9e7642c0aa6610247
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 02:22:02 +00:00
Lijian Zhao
8aba24d3e1 soc/intel/apollolake: Switch to common p2sb
Using common p2sb driver instead of private one.

TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.

Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27 20:13:59 +00:00
Lijian Zhao
899f5ffbdd soc/intel/cannonlake: Use common p2sb driver
Add common p2sb driver support.

TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.

Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27 20:13:33 +00:00
Lijian Zhao
a3cbbf7652 intel/common/p2sb: Add common p2sb driver
Add common p2sb device driver that will use fixed resource instead
dynamic assigned by PCI enumeration.

TEST=None

Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-27 20:13:27 +00:00
Marc Jones
bb59f67ee8 soc/amd/common: Remove agesa_LateRunApTask() callback
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake
in the AGESA spec and the function is in the wrong section.

bug=b:66690176, b:67210418
branch=none
test=none

Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-27 16:58:45 +00:00
Shaunak Saha
95b61752db soc/intel/cannonlake: Add support for C state and P state
This patch adds the C state and P state configurations for
cannonlake soc.

TEST = Boot and test the CPU states for all the cores are
       present in "powertop" tool output.

Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26 15:55:37 +00:00
Patrick Georgi
66b5acc54b soc/intel/cannonlake: remove duplicate power_state migration
Common PMC code comes with its own.

Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26 15:54:19 +00:00
Patrick Georgi
c6202e8c00 soc/intel/apollolake: avoid double accounting for power state
intel/common's pmclib already keeps track of the power state (since
commit f073872e22 and doing it twice can
mess up the data that ends up in cbmem (and from there, everything else),
so don't.

BUG=b:67976359
BRANCH=none
TEST=builds

Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26 04:57:49 +00:00
Furquan Shaikh
f5e8fe5d95 soc/intel/apollolake: Fix broken GNVS offset for chromeos
Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.

This change fixes the above issue by reducing the size of unused array.

BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.

Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25 17:12:40 +00:00
Furquan Shaikh
af88398887 soc/intel/skylake: Fix broken GNVS offset for chromeos
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.

This change fixes the above issue by reducing the size of unused
array.

BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.

Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25 17:06:06 +00:00
Chris Ching
aa8e5d36b1 soc: Add Kconfig for each soc vendor
Allows explicit ordering for vendors that share a common configuration
that must be sourced last.

The issue is that chips in soc/{amd,intel}/[ab].* will be able to
override defaults set in this file, but Kconfig files that get sourced
later (soc/amd/[d-z].*) will NOT be able to override these defaults.

Note: intel and amd soc chips now need to be added manually to the new
Kconfig file

BUG=b:62235314
TEST=make lint-stable

Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23 17:18:32 +00:00
John Zhao
9b6384c1a5 soc/intel/cannonlake: Increase stack size from 4KiB to 8KiB
Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092

Increase the stack size from 4kiB to 8kiB to prevent stack overrun.

TEST=No stack overrun is observed and it boots to OS properly.

Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23 16:40:01 +00:00
Lijian Zhao
c85890d0d8 soc/intel/cannonlake: Change max root port to 16
Cannonlake SOC support up to 16 PCI express root port.

BUG=CID 1381813;1381814;

Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 02:17:24 +00:00
Philipp Deppenwiese
fea2429e25 security/vboot: Move vboot2 to security kconfig section
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.

Fix vboot2 headers

Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 02:14:46 +00:00
Matt DeVillier
9e0d69bf1e soc/intel/skylake: pass SataSpeedLimit param to FSP2
The Librem13v2 needs to set this parameter to work around
power-related issues with some SATA devices.

Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22045
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 01:58:22 +00:00