Commit Graph

25334 Commits

Author SHA1 Message Date
Patrick Rudolph fb87e413bd cbfstool: Show current FMAP region in print
In case multiple FMAP regions are specified, print the FMAP name.
Useful if VBOOT is enabled and multiple CBFS are printed.

Change-Id: Id6f29ebeda8a9bde6dfe39362e0f2a5e33c86b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26862
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13 14:34:00 +00:00
Pratik Prajapati 7fd1e4b9b1 intel/wifi: Add WGDS ACPI method for Geo Aware SAR
To comply with all relevant bodies throughout the world, SAR settings
take into account the lowest common denominator Tx power settings. This
setup may lead to non-optimal performance when the user location is in a
country that may allow higher power setting. The purpose of Wireless Geo
Delta Settings (WGDS) is to provide offset settings for FCC, Europe,
Japan and Rest of the world. These offsets would be added (by Intel wifi
driver) to the base SAR Tx Power as defined in WRDS and EWRD

BUG=b:65155728
BRANCH=none
TEST=WGDS ACPI table gets created as expected.

Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-13 10:42:04 +00:00
Martin Roth 8919ac726b mainboard/google/kahlee: Add more 3 SPD files
BUG=b:111195311
TEST=Build grunt, verify SPDs are present

Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13 03:08:37 +00:00
Ricky Liang 8d0fd5d7d3 mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board
schematics.

Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://review.coreboot.org/27433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-07-12 17:28:38 +00:00
Patrick Rudolph ded0c77d48 Coverity: Fix CID1393976
Cast to u64 to prevent possible integer overflow.

Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12 15:22:06 +00:00
Patrick Rudolph f4d81e0385 Coverity: Fix CID1393978
Fix a typo.
Only memcpy into target buffer if pointer is not NULL.

Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12 15:21:36 +00:00
Patrick Rudolph 679d624fae Coverity: Fix CID1393979
Fix resource leak in dt_set_bin_prop_by_path().

Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12 15:21:10 +00:00
Xiang Wang 3ec008bf40 riscv: add include/arch/smp/ directory
Replicate directory layout from x86 for SMP.

Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27355
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12 11:53:30 +00:00
Pratik Prajapati 6e3cc8855b soc/intel/skylake: add a space in printing ME FPF status
This is cosmetic change

Before:
ME: Power Management Event  : Clean global reset
ME: Progress Phase State    : Unknown phase: 0x08 state: 0x10
ME: Power Down Mitigation   : NO
ME: FPF status               : fused

After:
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Unknown phase: 0x08 state: 0x10
ME: Power Down Mitigation   : NO
ME: FPF status              : fused

Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-12 11:53:18 +00:00
Elyes HAOUAS a4fc7bef7f nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs
Change-Id: Ib1f999447b37a1524d589552ea2eec640c2a2c7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-12 11:52:52 +00:00
Frans Hendriks 34510c377e soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optional
Currently thermal event support can not be disabled at board level.
Define and dependent code are placed in same file.

Move define of HAVE_THERM_EVENT_HANDLER to mainboard file.

Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27415
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12 11:52:23 +00:00
Furquan Shaikh a353d054ae mb/google/octopus/variants/yorp: Enable TBMC device
This change enables tablet mode ACPI device for yorp.

BUG=b:111264961
CQ-DEPEND=CL:1132686

Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12 00:39:59 +00:00
Furquan Shaikh 13367490b0 mb/google/octopus: Enable TBMC device only for phaser
Enabling of TBMC device on AP side requires corresponding support on the
EC side as well. Since not all octopus variants have tablet mode support
enabled, this change enables TBMC device only for phaser.

BUG=b:111264961

Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12 00:39:51 +00:00
Furquan Shaikh 4d98916721 mb/google/octopus/variants/bip: Enable EC SW sync
This change enables EC SW sync for bip by removing GBB flag selection
for disabling SW sync.

BUG=b:110523189
TEST=Verified that EC SW sync works fine on bip.

Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12 00:39:44 +00:00
li feng 3130a93bfa skylake: Remove "IshEnable"
Remove "IshEnable" from soc_intel_skylake_config since it's not
used anymore.

Enable/disable ISH by checking if ISH device is turned on or not.

Refer to https://review.coreboot.org/#/c/coreboot/+/26485/.

BUG=b:79244403
BRANCH=none
TEST=Built.

Change-Id: I4d2889af118659852431c87cb516fd19b577efc5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11 10:48:12 +00:00
li feng 0738d2a00d mainboard/google/poppy/variants/atlas: config ISH in mainboard side
To enable ISH device on atlas board, change "device pci 13.0 off end" to
"device pci 13.0 on end" in file
mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is
not needed.

Config atlas board specific ISH setting in devicetree.cb.
Dynamically load gpio setting for ISH enabled/disabled cases.

BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.

Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11 10:47:53 +00:00
Weiyi Lu 60e1fcb07f mediatek/mt8183: add PLL and clock init support
Add PLL and clock init code.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Checked with frequency meter in SOC.

Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/27031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11 10:47:09 +00:00
Tristan Shieh 17180af69a mediatek: Share PLL code among similar SOCs
Refactor PLL code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27305
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:46:45 +00:00
Tristan Shieh bb684e0c8d google/kukui: Update MMU table in romstage and ramstage
In order to get better performance, map dram as cached after dram ready
in romstage.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Need a futher check after dram
     calibration code ready.

Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27304
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:46:25 +00:00
Tristan Shieh 0eb92dfbc7 mediatek/mt8183: Add MMU operation support
Enable MMU in bootblock for performance, link common code to provide
mtk_mmu_after_dram() to update MMU table in romstage after dram ready,
implement mtk_soc_disable_l2c_sram(), and call
mtk_mmu_disable_l2c_sram() to turn off L2C sram in ramstage.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11 10:46:09 +00:00
Tristan Shieh c645a5aac4 mediatek: Share MMU operation code among similar SOCs
Refactor MMU operation code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11 10:45:48 +00:00
Martin Roth 1a26a30a7f mainboard/google/kahlee: Update existing SPD files
Add an extra space after 8th value on each line to make it easier
to count the values.
Update the empty spd to remove two random 0x80 values.

BUG=None
TEST=None

Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27423
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:45:19 +00:00
Martin Roth cef673759e mainboard/google/kahlee: Add additional SPDs for variants
BUG=b:111079089, b:80375243
TEST=Build grunt, verify that SPDs are included.

Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27422
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:45:11 +00:00
Xiang Wang 387417be03 riscv: add support to check ISA extension
Add support to check ISA extension for RISC-V.

Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-11 10:44:08 +00:00
Michał Żygowski 654a45d2ad src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode
According to BKDG for AMD Family 16h Models 30h-3Fh Processors
SDR50 tuning should be disabled in 0xA8 register.

Also fix clock frequency setting in 0xA4 for stepping >= A1
which caused reduced performance of SD cards transfer speed
even by half.

Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-10 09:53:22 +00:00
Paul Menzel 209a1bf8ca payloads/Kconfig: Put option *None* at the top
As *None* is special and not a payload, it makes sense to put it at the
top. Also, it was at before the latest addition of the FIT payload
choice.

Fixes: a892cde6 (lib: Add FIT payload support)
Change-Id: I52163ea9472308ecbc396012d9912b9617e0c318
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-07-10 09:53:12 +00:00
Patrick Rudolph 88f81af1ef soc/cavium: Add secondary CPU support
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10 07:07:09 +00:00
Patrick Rudolph ae15fec0b8 soc/cavium/cn81xx: Set cntfrq_el0
Set cntfrq_el0 to provide correct timer frequency.

Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25450
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10 07:05:27 +00:00
Patrick Rudolph bbfeb586a6 mb/cavium/cn8100_sff_evb: Be verbose
Print some useful information about the board.

Change-Id: I0acac7a29290bc2eb9f4283317165fa0cf1b24e1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25449
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10 07:04:40 +00:00
Patrick Rudolph d0dcf877e4 soc/cavium: Clean uart code
* Only init UART_FOR_CONSOLE
* Allow UART init with zero baudrate.
* Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic.

Tested on CN8100_SFF_EVB.

Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10 07:03:56 +00:00
Patrick Rudolph 06c7d64be9 soc/cavium: Enable MMU
* Configure and enable MMU.
* Cover the whole I/O space.
* A minimum of 512KB TTB space is required.
* Use secure mem attribute as firmware is running in ARM TZ region.

Tested on Cavium SoC.

Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10 07:03:29 +00:00
David Hendricks 8cbd569f74 cavium: Add CN81xx SoC and eval board support
This adds Cavium CN81xx SoC and SFF EVB files.

Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK

BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs

romstage:
- Use minimal DRAM init only

devicetree:
- Convert FTD to static C file containing key value pairs

Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)

Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init

Not working:
- Booting a payload
- Booting upstream ATF

TODO:
- Configuration straps

Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10 07:01:57 +00:00
Patrick Rudolph 03d3142733 util/cavium: Add tool to convert devicetree blobs
Convert Cavium's BDK devicetree blob to a static C file.

The resulting file must be included in mainboard folder to provide
board specific configuration values to BDK functions.

Example call:
python devicetree_convert.py --in sff8104.dtb --out bdk_devicetree.c

Change-Id: I76a5588aefe4f680228eca46a0e4dba7e695931c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26228
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-09 09:54:22 +00:00
Elyes HAOUAS 251279c537 src/southbridge: Use "foo *bar" instead of "foo* bar"
Change-Id: I72d50615d77b91529810e8f590fa56f3c6f7546c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09 09:31:54 +00:00
Elyes HAOUAS 39303d5d49 src/soc: Use "foo *bar" instead of "foo* bar"
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09 09:31:10 +00:00
Elyes HAOUAS fd051dc018 src/northbridge: Use "foo *bar" instead of "foo* bar"
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09 09:29:53 +00:00
Elyes HAOUAS 95bca33efa src/mb: Use "foo *bar" instead of "foo* bar"
Change-Id: Iedc2e48349e40e94863c8080d11e11dbe6084c9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09 09:29:00 +00:00
Elyes HAOUAS c92f5f218f src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"
Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09 09:28:35 +00:00
Elyes HAOUAS b0b0c8c60a src/{device,drivers}: Use "foo *bar" instead of "foo* bar"
Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09 09:27:34 +00:00
Elyes HAOUAS 6c9737b1ac src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar"
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09 09:26:18 +00:00
li feng 2106638ec2 soc/intel/skylake: config ISH in SOC side
Config ISH in SOC side by checking if ISH device is turned on.

"IshEnable" is not needed anymore since ISH device on/off will tell
if ISH should be enabled or not. "IshEnable" will be removed from chip.h
in separate CL.

Atlas board specific ISH setting is needed, which is committed in
separate CL.

BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.

Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-09 09:24:42 +00:00
Patrick Rudolph f1114d8918 ec/lenovo/h8/acpi: Add BDC interface
* Add SSDT generator to add dynamic ACPI code.
* Implement GBDC and SBDC for thinkpad_acpi kernel module.
Required for BDC power control from userspace.

Tested on Lenovo T430:
The bluetooth module is detected and can be powercycled using network manager.

Change-Id: Ida825196650966194a883945896a038b0790fe45
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09 09:19:59 +00:00
Felix Held 01d2e46ddb superio: move files to match the common naming scheme
Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23009
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06 16:47:21 +00:00
Martin Roth 18c4e26ede util/lint: Update lint-stable-000-license-headers linter
- Update stable directories
- Remove duplicated directories

There are currently 220 files that still need to have headers added or
be excluded from the lint-000-license-headers test.

Change-Id: I40046a2fb7359262b130f6813eda1f2c30916b46
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-06 15:31:51 +00:00
Martin Roth 842253b242 src: Add missing license headers
These two files were added before I was able to get the updated linter
committed.  Updated/Add the headers so the stable header lint check
can be updated.

Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-06 15:30:59 +00:00
Frans Hendriks 69a835d311 util/cbfstool/compiler: __attribute redefinition
In Windows Cygwin enviroment, compiler reports
redefinition error at cbfstool/ifwitool.c
on _packed and __aligned.

Skip new defines when vales are already defined.

Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-06 13:10:27 +00:00
Xiang Wang 8889e0106d riscv: use __riscv_atomic to check support A extension
GCC pre-defined some macros for detecting ISA extensions.
We should use these macros to detect ISA features.

Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475
Signed-off-by: XiangWang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-07-06 13:07:08 +00:00
Kevin Chiu 12f0b4c80e google/grunt: Update Raydium TS device ACPI nodes
change I2C irq to EDGE trigger

BUG=b:110962003
BRANCH=master
TEST=emerge-grunt coreboot
     Raydium TS is working.
Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27327
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06 13:02:24 +00:00
Justin TerAvest 3419bf639d mb/google/octopus: Enable tablet mode
This change configures ACPI to properly route notifications from the EC
for tablet mode events to userspace. Relevant EC config changes are at:
  https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1125261

BUG=b:111078678
TEST=With EC change, tablet mode detected by evtest and powerd

Change-Id: Ifbc318186b195534f647f062544de4968aa87401
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06 13:02:07 +00:00
Patrick Rudolph f81f62a6c1 ec/lenovo/h8/acpi: Move ACPI HKEY device to new file
Move the APCI HKEY device to a new file and include it.
The follow-up commits will extend it and this way it remains readable.

Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2018-07-06 13:00:52 +00:00