2009-08-12 17:00:51 +02:00
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##
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2010-01-20 19:44:30 +01:00
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## This file is part of the coreboot project.
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2009-08-12 17:00:51 +02:00
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##
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2012-08-23 09:32:58 +02:00
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## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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2010-01-20 19:44:30 +01:00
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## Copyright (C) 2009-2010 coresystems GmbH
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2009-08-12 17:00:51 +02:00
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##
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2010-01-20 19:44:30 +01:00
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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2013-02-23 18:37:27 +01:00
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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2009-08-12 17:00:51 +02:00
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##
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2012-04-12 22:00:03 +02:00
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mainmenu "coreboot configuration"
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2009-08-12 17:00:51 +02:00
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2009-10-05 15:55:28 +02:00
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menu "General setup"
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2009-10-18 20:35:50 +02:00
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config EXPERT
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bool "Expert mode"
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help
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This allows you to select certain advanced configuration options.
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Warning: Only enable this option if you really know what you are
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doing! You have been warned!
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2009-10-05 15:55:28 +02:00
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config LOCALVERSION
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2009-10-07 18:15:40 +02:00
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string "Local version string"
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2009-10-05 15:55:28 +02:00
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help
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Append an extra string to the end of the coreboot version.
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2009-10-07 18:15:40 +02:00
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This can be useful if, for instance, you want to append the
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respective board's hostname or some other identifying string to
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the coreboot version number, so that you can easily distinguish
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boot logs of different boards from each other.
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2010-02-09 20:35:16 +01:00
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config CBFS_PREFIX
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string "CBFS prefix to use"
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default "fallback"
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help
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Select the prefix to all files put into the image. It's "fallback"
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by default, "normal" is a common alternative.
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2010-03-16 02:17:19 +01:00
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choice
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2012-04-12 22:00:03 +02:00
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prompt "Compiler to use"
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2010-03-16 02:17:19 +01:00
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default COMPILER_GCC
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help
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This option allows you to select the compiler used for building
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coreboot.
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config COMPILER_GCC
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bool "GCC"
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2012-04-12 22:00:03 +02:00
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help
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Use the GNU Compiler Collection (GCC) to build coreboot.
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For details see http://gcc.gnu.org.
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2010-03-16 02:17:19 +01:00
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config COMPILER_LLVM_CLANG
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bool "LLVM/clang"
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2012-04-12 22:00:03 +02:00
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help
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Use LLVM/clang to build coreboot.
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For details see http://clang.llvm.org.
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2010-03-16 02:17:19 +01:00
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endchoice
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2013-12-29 18:45:23 +01:00
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config ANY_TOOLCHAIN
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bool "Allow building with any toolchain"
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default n
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depends on COMPILER_GCC
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help
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Many toolchains break when building coreboot since it uses quite
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unusual linker features. Unless developers explicitely request it,
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we'll have to assume that they use their distro compiler by mistake.
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Make sure that using patched compilers is a conscious decision.
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2010-03-25 22:45:25 +01:00
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config CCACHE
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2012-04-12 22:00:03 +02:00
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bool "Use ccache to speed up (re)compilation"
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2010-03-25 22:45:25 +01:00
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default n
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help
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Enables the use of ccache for faster builds.
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2012-04-12 22:00:03 +02:00
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Requires the ccache utility in your system $PATH.
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For details see https://ccache.samba.org.
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2010-03-25 22:45:25 +01:00
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2010-08-09 15:28:18 +02:00
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config SCONFIG_GENPARSER
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bool "Generate SCONFIG parser using flex and bison"
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default n
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depends on EXPERT
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help
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2012-04-12 22:00:03 +02:00
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Enable this option if you are working on the sconfig device tree
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parser and made changes to sconfig.l and sconfig.y.
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2010-08-09 15:28:18 +02:00
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Otherwise, say N.
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2010-05-19 20:41:15 +02:00
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config USE_OPTION_TABLE
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bool "Use CMOS for configuration values"
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default n
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2010-07-06 23:05:04 +02:00
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depends on HAVE_OPTION_TABLE
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2010-05-19 20:41:15 +02:00
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help
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Enable this option if coreboot shall read options from the "CMOS"
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2012-04-12 22:00:03 +02:00
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NVRAM instead of using hard-coded values.
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2010-05-19 20:41:15 +02:00
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2011-05-02 21:53:04 +02:00
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config COMPRESS_RAMSTAGE
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bool "Compress ramstage with LZMA"
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default y
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help
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Compress ramstage to save memory in the flash image. Note
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that decompression might slow down booting if the boot flash
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2012-04-12 22:00:03 +02:00
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is connected through a slow link (i.e. SPI).
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2011-05-02 21:53:04 +02:00
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2011-06-19 03:03:28 +02:00
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config INCLUDE_CONFIG_FILE
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2012-04-12 22:00:03 +02:00
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bool "Include the coreboot .config file into the ROM image"
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2011-06-19 03:03:28 +02:00
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default y
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2012-04-12 22:00:03 +02:00
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help
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Include the .config file that was used to compile coreboot
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in the (CBFS) ROM image. This is useful if you want to know which
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options were used to build a specific coreboot.rom image.
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2014-07-22 18:00:56 +02:00
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Saying Y here will increase the image size by 2-3KB.
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2012-04-12 22:00:03 +02:00
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You can use the following command to easily list the options:
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grep -a CONFIG_ coreboot.rom
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Alternatively, you can also use cbfstool to print the image
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contents (including the raw 'config' item we're looking for).
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Example:
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$ cbfstool coreboot.rom print
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coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
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offset 0x0
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Alignment: 64 bytes
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2012-05-18 19:18:47 +02:00
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2012-04-12 22:00:03 +02:00
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Name Offset Type Size
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cmos_layout.bin 0x0 cmos layout 1159
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fallback/romstage 0x4c0 stage 339756
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2014-07-22 18:00:56 +02:00
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fallback/ramstage 0x53440 stage 186664
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2012-04-12 22:00:03 +02:00
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fallback/payload 0x80dc0 payload 51526
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config 0x8d740 raw 3324
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(empty) 0x8e480 null 3610440
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2011-06-19 03:03:28 +02:00
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2013-10-11 21:08:02 +02:00
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config EARLY_CBMEM_INIT
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bool
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default n
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help
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Make coreboot initialize the CBMEM structures while running in ROM
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stage. This is useful when the ROM stage wants to communicate
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some, for instance, execution timestamps. It needs support in
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romstage.c and should be enabled by the board's Kconfig.
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2014-03-28 22:46:45 +01:00
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config BROKEN_CAR_MIGRATE
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bool
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default y if !EARLY_CBMEM_INIT && HAVE_ACPI_RESUME
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default n
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help
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Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and
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manage CAR migration on S3 resume path only. Couple boards use
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CAR_GLOBAL and never do CAR migration.
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2013-03-13 18:41:44 +01:00
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config DYNAMIC_CBMEM
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bool "The CBMEM space is dynamically grown."
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default n
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2013-10-11 21:08:02 +02:00
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select EARLY_CBMEM_INIT
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2013-03-13 18:41:44 +01:00
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help
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Instead of reserving a static amount of CBMEM space the CBMEM
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area grows dynamically. CBMEM can be used both in romstage (after
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memory initialization) and ramstage.
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2011-09-21 23:46:43 +02:00
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config COLLECT_TIMESTAMPS
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bool "Create a table of timestamps collected during boot"
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2013-10-11 20:14:59 +02:00
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default n
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2011-09-21 23:46:43 +02:00
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help
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2012-04-12 22:00:03 +02:00
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Make coreboot create a table of timer-ID/timer-value pairs to
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allow measuring time spent at different phases of the boot process.
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2012-04-30 21:06:10 +02:00
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config USE_BLOBS
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bool "Allow use of binary-only repository"
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default n
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help
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This draws in the blobs repository, which contains binary files that
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might be required for some chipsets or boards.
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This flag ensures that a "Free" option remains available for users.
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Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 01:23:28 +01:00
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config COVERAGE
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bool "Code coverage support"
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depends on COMPILER_GCC
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default n
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help
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Add code coverage support for coreboot. This will store code
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coverage information in CBMEM for extraction from user space.
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If unsure, say N.
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2014-10-17 13:08:36 +02:00
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config RELOCATABLE_MODULES
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bool "Relocatable Modules"
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2010-12-17 00:37:17 +01:00
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default n
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2014-10-17 13:08:36 +02:00
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help
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If RELOCATABLE_MODULES is selected then support is enabled for
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building relocatable modules in the RAM stage. Those modules can be
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loaded anywhere and all the relocations are handled automatically.
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2012-11-30 01:28:21 +01:00
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2014-10-17 13:08:36 +02:00
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config RELOCATABLE_RAMSTAGE
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depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM)
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bool "Build the ramstage to be relocatable in 32-bit address space."
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2012-11-29 05:16:28 +01:00
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default n
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2014-10-17 13:08:36 +02:00
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help
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The reloctable ramstage support allows for the ramstage to be built
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as a relocatable module. The stage loader can identify a place
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out of the OS way so that copying memory is unnecessary during an S3
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wake. When selecting this option the romstage is responsible for
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determing a stack location to use for loading the ramstage.
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2012-11-29 05:16:28 +01:00
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2014-10-17 13:08:36 +02:00
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config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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depends on RELOCATABLE_RAMSTAGE
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bool "Cache the relocated ramstage outside of cbmem."
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2014-04-29 01:39:40 +02:00
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default n
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2014-10-17 13:08:36 +02:00
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help
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The relocated ramstage is saved in an area specified by the
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by the board and/or chipset.
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2014-02-07 03:58:24 +01:00
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2014-05-07 03:00:19 +02:00
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choice
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prompt "Bootblock behaviour"
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default BOOTBLOCK_SIMPLE
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config BOOTBLOCK_SIMPLE
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bool "Always load fallback"
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config BOOTBLOCK_NORMAL
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bool "Switch to normal if CMOS says so"
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endchoice
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config BOOTBLOCK_SOURCE
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string
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default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
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default "bootblock_normal.c" if BOOTBLOCK_NORMAL
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config UPDATE_IMAGE
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bool "Update existing coreboot.rom image"
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default n
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help
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If this option is enabled, no new coreboot.rom file
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is created. Instead it is expected that there already
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is a suitable file for further processing.
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The bootblock will not be modified.
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2014-10-17 13:08:36 +02:00
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endmenu
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source src/mainboard/Kconfig
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# This option is used to set the architecture of a mainboard to X86.
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# It is usually set in mainboard/*/Kconfig.
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config ARCH_X86
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bool
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default n
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select PCI
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config ARCH_ARM
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bool
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default n
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config ARCH_ARM64
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bool
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default n
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source src/arch/x86/Kconfig
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source src/arch/arm/Kconfig
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source src/arch/arm64/Kconfig
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source src/vendorcode/Kconfig
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config SYSTEM_TYPE_LAPTOP
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default n
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bool
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Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
menu "Chipset"
|
|
|
|
|
|
|
|
|
|
comment "CPU"
|
|
|
|
|
source src/cpu/Kconfig
|
|
|
|
|
comment "Northbridge"
|
2009-08-12 17:00:51 +02:00
|
|
|
source src/northbridge/Kconfig
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
comment "Southbridge"
|
2009-08-12 17:00:51 +02:00
|
|
|
source src/southbridge/Kconfig
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
comment "Super I/O"
|
2009-08-12 17:00:51 +02:00
|
|
|
source src/superio/Kconfig
|
2011-01-27 12:43:03 +01:00
|
|
|
comment "Embedded Controllers"
|
|
|
|
|
source src/ec/Kconfig
|
2013-09-07 07:41:48 +02:00
|
|
|
comment "SoC"
|
|
|
|
|
source src/soc/Kconfig
|
2014-04-25 22:12:13 +02:00
|
|
|
source src/drivers/intel/fsp/Kconfig
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
|
|
|
|
|
endmenu
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2012-11-30 21:34:04 +01:00
|
|
|
source src/device/Kconfig
|
2012-11-14 02:00:01 +01:00
|
|
|
|
2010-05-16 17:31:53 +02:00
|
|
|
menu "Generic Drivers"
|
|
|
|
|
source src/drivers/Kconfig
|
|
|
|
|
endmenu
|
|
|
|
|
|
drivers: Add I2C TPM driver to coreboot
On ARM platforms the TPM is not attached through LPC but through I2C.
This patch adds an I2C TPM driver that supports the following chips:
* Infineon SLB9635
* Infineon SLB9645
In order to select the correct TPM implementation cleanly, CONFIG_TPM
is moved to src/Kconfig and does the correct choice.
Old-Change-Id: I2def0e0f86a869d6fcf56fc4ccab0bc935de2bf1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/167543
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit b4049a0e96f6335a93877e1e884f9a440487c421)
i2c tpm: Remove mostly useless delay code/tables.
I assume from the code in the TPM driver that the TPM spec defines
different types of delays and timeouts which each have a particular
duration, and that the TPM can tell you how long each type is if you ask
it. There was a large table, some members of a data structure, and a
function or two which managed the timeouts and figured their value for
different operations. The timeout values for the various "ordinals"
were never set in the vendor specific data structure, however, and
always defaulted to 2 minutes. Similarly the timeouts a, b, c, and d
were never overridden from their defaults. This change gets rid of all
the timeout management code and makes the "ordinal" timeout 2 minutes
and the a, b, c, and d timeouts 2 seconds, the larger of the two default
values.
This is a port from depthcharge to coreboot, original change:
https://chromium-review.googlesource.com/#/c/168363/
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Old-Change-Id: I79696d6329184ca07f6a1be4f6ca85e1655a7aaf
Reviewed-on: https://chromium-review.googlesource.com/168583
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit b22395a73f361c38626911808332a3706b2334fe)
TPM: Stop requesting/releasing the TPM locality.
The locality is requested when the TPM is initialized and released when
it's cleaned up. There's no reason to set it to the same thing again and
restore it back to the same value before and after every transaction.
forward ported from https://chromium-review.googlesource.com/#/c/168400
Old-Change-Id: I291d1f86f220ef0eff6809c6cb00459bf95aa5e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168584
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit cc866c20c6f936f349d2f1773dd492dca9bbf0c1)
Squashed three commits for the i2c tpm driver.
Change-Id: Ie7a50c50fda8ee986c02de7fe27551666998229d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6519
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-30 01:05:02 +02:00
|
|
|
config TPM
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
select LPC_TPM if ARCH_X86
|
ARM: Generalize armv7 as arm.
There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.
Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
ARM: Split out ARMv7 code and make it possible to have other arch versions.
We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.
The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.
Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)
Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.
Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
2013-10-01 08:00:33 +02:00
|
|
|
select I2C_TPM if ARCH_ARM
|
2014-04-29 01:39:40 +02:00
|
|
|
select I2C_TPM if ARCH_ARM64
|
drivers: Add I2C TPM driver to coreboot
On ARM platforms the TPM is not attached through LPC but through I2C.
This patch adds an I2C TPM driver that supports the following chips:
* Infineon SLB9635
* Infineon SLB9645
In order to select the correct TPM implementation cleanly, CONFIG_TPM
is moved to src/Kconfig and does the correct choice.
Old-Change-Id: I2def0e0f86a869d6fcf56fc4ccab0bc935de2bf1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/167543
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit b4049a0e96f6335a93877e1e884f9a440487c421)
i2c tpm: Remove mostly useless delay code/tables.
I assume from the code in the TPM driver that the TPM spec defines
different types of delays and timeouts which each have a particular
duration, and that the TPM can tell you how long each type is if you ask
it. There was a large table, some members of a data structure, and a
function or two which managed the timeouts and figured their value for
different operations. The timeout values for the various "ordinals"
were never set in the vendor specific data structure, however, and
always defaulted to 2 minutes. Similarly the timeouts a, b, c, and d
were never overridden from their defaults. This change gets rid of all
the timeout management code and makes the "ordinal" timeout 2 minutes
and the a, b, c, and d timeouts 2 seconds, the larger of the two default
values.
This is a port from depthcharge to coreboot, original change:
https://chromium-review.googlesource.com/#/c/168363/
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Old-Change-Id: I79696d6329184ca07f6a1be4f6ca85e1655a7aaf
Reviewed-on: https://chromium-review.googlesource.com/168583
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit b22395a73f361c38626911808332a3706b2334fe)
TPM: Stop requesting/releasing the TPM locality.
The locality is requested when the TPM is initialized and released when
it's cleaned up. There's no reason to set it to the same thing again and
restore it back to the same value before and after every transaction.
forward ported from https://chromium-review.googlesource.com/#/c/168400
Old-Change-Id: I291d1f86f220ef0eff6809c6cb00459bf95aa5e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168584
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit cc866c20c6f936f349d2f1773dd492dca9bbf0c1)
Squashed three commits for the i2c tpm driver.
Change-Id: Ie7a50c50fda8ee986c02de7fe27551666998229d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6519
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-30 01:05:02 +02:00
|
|
|
help
|
|
|
|
|
Enable this option to enable TPM support in coreboot.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
config HEAP_SIZE
|
|
|
|
|
hex
|
2009-10-16 21:12:49 +02:00
|
|
|
default 0x4000
|
2009-08-12 17:00:51 +02:00
|
|
|
|
|
|
|
|
config MAX_CPUS
|
|
|
|
|
int
|
|
|
|
|
default 1
|
|
|
|
|
|
|
|
|
|
config MMCONF_SUPPORT_DEFAULT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config MMCONF_SUPPORT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2013-11-28 17:11:49 +01:00
|
|
|
config BOOTMODE_STRAPS
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
source src/console/Kconfig
|
|
|
|
|
|
|
|
|
|
config HAVE_ACPI_RESUME
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2010-06-05 12:03:08 +02:00
|
|
|
config HAVE_ACPI_SLIC
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
config ACPI_SSDTX_NUM
|
|
|
|
|
int
|
|
|
|
|
default 0
|
|
|
|
|
|
|
|
|
|
config HAVE_HARD_RESET
|
|
|
|
|
bool
|
2009-10-09 13:47:21 +02:00
|
|
|
default n
|
2010-02-27 09:39:04 +01:00
|
|
|
help
|
|
|
|
|
This variable specifies whether a given board has a hard_reset
|
|
|
|
|
function, no matter if it's provided by board code or chipset code.
|
|
|
|
|
|
2013-04-30 05:31:51 +02:00
|
|
|
config HAVE_MONOTONIC_TIMER
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
The board/chipset provides a monotonic timer.
|
|
|
|
|
|
2013-04-30 16:58:12 +02:00
|
|
|
config TIMER_QUEUE
|
|
|
|
|
def_bool n
|
|
|
|
|
depends on HAVE_MONOTONIC_TIMER
|
|
|
|
|
help
|
2013-09-13 06:57:49 +02:00
|
|
|
Provide a timer queue for performing time-based callbacks.
|
2013-04-30 16:58:12 +02:00
|
|
|
|
2013-05-06 19:20:52 +02:00
|
|
|
config COOP_MULTITASKING
|
|
|
|
|
def_bool n
|
2013-05-06 19:22:23 +02:00
|
|
|
depends on TIMER_QUEUE && ARCH_X86
|
2013-05-06 19:20:52 +02:00
|
|
|
help
|
|
|
|
|
Cooperative multitasking allows callbacks to be multiplexed on the
|
|
|
|
|
main thread of ramstage. With this enabled it allows for multiple
|
|
|
|
|
execution paths to take place when they have udelay() calls within
|
|
|
|
|
their code.
|
|
|
|
|
|
|
|
|
|
config NUM_THREADS
|
|
|
|
|
int
|
|
|
|
|
default 4
|
|
|
|
|
depends on COOP_MULTITASKING
|
|
|
|
|
help
|
|
|
|
|
How many execution threads to cooperatively multitask with.
|
|
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
config HAVE_OPTION_TABLE
|
|
|
|
|
bool
|
2010-07-06 23:05:04 +02:00
|
|
|
default n
|
2009-10-15 19:49:07 +02:00
|
|
|
help
|
|
|
|
|
This variable specifies whether a given board has a cmos.layout
|
|
|
|
|
file containing NVRAM/CMOS bit definitions.
|
2010-07-06 23:05:04 +02:00
|
|
|
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
|
2009-08-12 17:00:51 +02:00
|
|
|
|
|
|
|
|
config PIRQ_ROUTE
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config HAVE_SMI_HANDLER
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config PCI_IO_CFG_EXT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config IOAPIC
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2012-08-16 23:05:42 +02:00
|
|
|
config CBFS_SIZE
|
|
|
|
|
hex
|
|
|
|
|
default ROM_SIZE
|
|
|
|
|
|
2014-01-06 10:06:26 +01:00
|
|
|
config CACHE_ROM_SIZE_OVERRIDE
|
2012-08-16 23:05:42 +02:00
|
|
|
hex
|
2014-01-06 10:06:26 +01:00
|
|
|
default 0
|
2012-08-16 23:05:42 +02:00
|
|
|
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
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# TODO: Can probably be removed once all chipsets have kconfig options for it.
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2009-10-04 19:15:39 +02:00
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config VIDEO_MB
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int
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Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
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default 0
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2009-10-04 19:15:39 +02:00
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2009-09-22 20:49:08 +02:00
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config USE_WATCHDOG_ON_BOOT
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bool
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default n
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config VGA
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bool
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default n
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help
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Build board-specific VGA code.
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config GFXUMA
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bool
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2009-10-26 16:14:07 +01:00
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default n
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2009-09-22 20:49:08 +02:00
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help
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Enable Unified Memory Architecture for graphics.
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2009-10-15 15:35:47 +02:00
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config HAVE_ACPI_TABLES
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bool
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2009-10-15 19:49:07 +02:00
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help
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This variable specifies whether a given board has ACPI table support.
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It is usually set in mainboard/*/Kconfig.
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2009-10-15 15:35:47 +02:00
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config HAVE_MP_TABLE
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bool
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2009-10-15 19:49:07 +02:00
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help
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This variable specifies whether a given board has MP table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the MP table is actually generated by coreboot
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is configurable by the user via GENERATE_MP_TABLE.
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2009-10-15 15:35:47 +02:00
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config HAVE_PIRQ_TABLE
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bool
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2009-10-15 19:49:07 +02:00
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help
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This variable specifies whether a given board has PIRQ table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the PIRQ table is actually generated by coreboot
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is configurable by the user via GENERATE_PIRQ_TABLE.
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2009-10-15 15:35:47 +02:00
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2012-08-23 09:32:58 +02:00
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config MAX_PIRQ_LINKS
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int
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default 4
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help
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This variable specifies the number of PIRQ interrupt links which are
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routable. On most chipsets, this is 4, INTA through INTD. Some
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chipsets offer more than four links, commonly up to INTH. They may
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also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
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table specifies links greater than 4, pirq_route_irqs will not
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function properly, unless this variable is correctly set.
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2014-08-30 19:28:05 +02:00
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config PER_DEVICE_ACPI_TABLES
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bool
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default n
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2009-10-26 16:14:07 +01:00
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#These Options are here to avoid "undefined" warnings.
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#The actual selection and help texts are in the following menu.
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menu "System tables"
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2009-09-22 20:49:08 +02:00
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2009-10-15 15:35:47 +02:00
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config GENERATE_MP_TABLE
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2012-11-14 02:33:08 +01:00
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prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
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bool
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default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
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2009-10-15 19:49:07 +02:00
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help
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Generate an MP table (conforming to the Intel MultiProcessor
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specification 1.4) for this board.
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If unsure, say Y.
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2009-09-22 20:49:08 +02:00
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2009-10-15 15:35:47 +02:00
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config GENERATE_PIRQ_TABLE
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2012-11-14 02:33:08 +01:00
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prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
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bool
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default HAVE_PIRQ_TABLE
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2009-10-15 19:49:07 +02:00
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help
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Generate a PIRQ table for this board.
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If unsure, say Y.
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2009-09-22 20:49:08 +02:00
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2011-08-14 20:56:34 +02:00
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config GENERATE_SMBIOS_TABLES
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depends on ARCH_X86
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bool "Generate SMBIOS tables"
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default y
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help
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Generate SMBIOS tables for this board.
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If unsure, say Y.
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2009-09-22 20:49:08 +02:00
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endmenu
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2009-08-12 17:00:51 +02:00
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menu "Payload"
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choice
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2009-10-07 18:15:40 +02:00
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prompt "Add a payload"
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2010-12-30 18:39:50 +01:00
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default PAYLOAD_NONE if !ARCH_X86
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default PAYLOAD_SEABIOS if ARCH_X86
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2009-08-12 17:00:51 +02:00
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2009-10-07 18:15:40 +02:00
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config PAYLOAD_NONE
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bool "None"
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help
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Select this option if you want to create an "empty" coreboot
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ROM image for a certain mainboard, i.e. a coreboot ROM image
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which does not yet contain a payload.
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For such an image to be useful, you have to use 'cbfstool'
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to add a payload to the ROM image later.
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2009-08-12 17:00:51 +02:00
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config PAYLOAD_ELF
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2009-10-07 18:15:40 +02:00
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bool "An ELF executable payload"
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2009-08-12 17:00:51 +02:00
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help
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Select this option if you have a payload image (an ELF file)
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which coreboot should run as soon as the basic hardware
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initialization is completed.
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You will be able to specify the location and file name of the
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payload image later.
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2013-08-31 08:26:52 +02:00
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config PAYLOAD_LINUX
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bool "A Linux payload"
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help
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Select this option if you have a Linux bzImage which coreboot
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should run as soon as the basic hardware initialization
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is completed.
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You will be able to specify the location and file name of the
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payload image later.
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2010-12-30 18:39:50 +01:00
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config PAYLOAD_SEABIOS
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bool "SeaBIOS"
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depends on ARCH_X86
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help
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Select this option if you want to build a coreboot image
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with a SeaBIOS payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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2011-04-15 05:34:05 +02:00
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config PAYLOAD_FILO
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bool "FILO"
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help
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Select this option if you want to build a coreboot image
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with a FILO payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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2013-11-14 12:10:08 +01:00
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config PAYLOAD_GRUB2
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bool "GRUB2"
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help
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Select this option if you want to build a coreboot image
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with a GRUB2 payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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2013-01-16 02:02:58 +01:00
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config PAYLOAD_TIANOCORE
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bool "Tiano Core"
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help
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Select this option if you want to build a coreboot image
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with a Tiano Core payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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2010-12-30 18:39:50 +01:00
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endchoice
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choice
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prompt "SeaBIOS version"
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default SEABIOS_STABLE
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depends on PAYLOAD_SEABIOS
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config SEABIOS_STABLE
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2014-09-13 12:43:45 +02:00
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bool "1.7.5"
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2010-12-30 18:39:50 +01:00
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help
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Stable SeaBIOS version
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config SEABIOS_MASTER
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bool "master"
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help
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Newest SeaBIOS version
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2014-07-22 18:00:56 +02:00
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2009-08-12 17:00:51 +02:00
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endchoice
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2013-07-09 19:43:09 +02:00
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config SEABIOS_PS2_TIMEOUT
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prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS
|
2013-08-16 10:14:38 +02:00
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default 0
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2013-07-09 19:43:09 +02:00
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depends on EXPERT
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int
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help
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Some PS/2 keyboard controllers don't respond to commands immediately
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after powering on. This specifies how long SeaBIOS will wait for the
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keyboard controller to become ready before giving up.
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2014-04-02 00:47:33 +02:00
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config SEABIOS_THREAD_OPTIONROMS
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prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS
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default n
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bool
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help
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Allow hardware init to run in parallel with optionrom execution.
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This can reduce boot time, but can cause some timing
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variations during option ROM code execution. It is not
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known if all option ROMs will behave properly with this option.
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2014-07-25 22:39:05 +02:00
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config SEABIOS_MALLOC_UPPERMEMORY
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bool
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default y
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depends on PAYLOAD_SEABIOS
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help
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Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
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"low memory" allocations. If this is not selected, the memory is
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instead allocated from the "9-segment" (0x90000-0xa0000).
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This is not typically needed, but may be required on some platforms
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to allow USB and SATA buffers to be written correctly by the
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hardware. In general, if this is desired, the option will be
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set to 'N' by the chipset Kconfig.
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2014-09-12 19:43:49 +02:00
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config SEABIOS_VGA_COREBOOT
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prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS
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default n
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depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
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bool
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help
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Coreboot can initialize the GPU of some mainboards.
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After initializing the GPU, the information about it can be passed to the payload.
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Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
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2013-11-14 12:10:08 +01:00
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choice
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prompt "GRUB2 version"
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default GRUB2_MASTER
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depends on PAYLOAD_GRUB2
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config GRUB2_MASTER
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bool "HEAD"
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help
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Newest GRUB2 version
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2014-07-22 18:00:56 +02:00
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2013-11-14 12:10:08 +01:00
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endchoice
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2011-04-15 05:34:05 +02:00
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choice
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prompt "FILO version"
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default FILO_STABLE
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depends on PAYLOAD_FILO
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config FILO_STABLE
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bool "0.6.0"
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help
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Stable FILO version
|
2014-07-22 18:00:56 +02:00
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2011-04-15 05:34:05 +02:00
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config FILO_MASTER
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bool "HEAD"
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help
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Newest FILO version
|
2014-07-22 18:00:56 +02:00
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2011-04-15 05:34:05 +02:00
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endchoice
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|
|
2010-12-19 22:20:14 +01:00
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|
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config PAYLOAD_FILE
|
2009-08-17 16:47:32 +02:00
|
|
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string "Payload path and filename"
|
2009-08-12 17:00:51 +02:00
|
|
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depends on PAYLOAD_ELF
|
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|
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default "payload.elf"
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|
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help
|
2009-08-25 02:53:22 +02:00
|
|
|
The path and filename of the ELF executable file to use as payload.
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2013-08-31 08:26:52 +02:00
|
|
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config PAYLOAD_FILE
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|
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string "Linux path and filename"
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depends on PAYLOAD_LINUX
|
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default "bzImage"
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|
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help
|
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|
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The path and filename of the bzImage kernel to use as payload.
|
|
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|
|
|
2010-12-30 18:39:50 +01:00
|
|
|
config PAYLOAD_FILE
|
|
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|
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depends on PAYLOAD_SEABIOS
|
2014-08-11 16:09:07 +02:00
|
|
|
default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
|
2010-12-30 18:39:50 +01:00
|
|
|
|
2014-09-12 19:43:49 +02:00
|
|
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config PAYLOAD_VGABIOS_FILE
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string
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|
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depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT
|
|
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|
|
default "payloads/external/SeaBIOS/seabios/out/vgabios.bin"
|
|
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|
|
2011-04-15 05:34:05 +02:00
|
|
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config PAYLOAD_FILE
|
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|
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depends on PAYLOAD_FILO
|
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|
|
default "payloads/external/FILO/filo/build/filo.elf"
|
|
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|
|
|
2013-11-14 12:10:08 +01:00
|
|
|
config PAYLOAD_FILE
|
|
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|
|
depends on PAYLOAD_GRUB2
|
|
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|
|
default "payloads/external/GRUB2/grub2/build/default_payload.elf"
|
|
|
|
|
|
2013-02-05 22:58:29 +01:00
|
|
|
config PAYLOAD_FILE
|
|
|
|
|
string "Tianocore firmware volume"
|
|
|
|
|
depends on PAYLOAD_TIANOCORE
|
|
|
|
|
default "COREBOOT.fd"
|
|
|
|
|
help
|
|
|
|
|
The result of a corebootPkg build
|
|
|
|
|
|
2009-10-07 18:15:40 +02:00
|
|
|
# TODO: Defined if no payload? Breaks build?
|
|
|
|
|
config COMPRESSED_PAYLOAD_LZMA
|
|
|
|
|
bool "Use LZMA compression for payloads"
|
|
|
|
|
default y
|
2013-11-14 12:10:08 +01:00
|
|
|
depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2
|
2009-10-07 18:15:40 +02:00
|
|
|
help
|
|
|
|
|
In order to reduce the size payloads take up in the ROM chip
|
|
|
|
|
coreboot can compress them using the LZMA algorithm.
|
|
|
|
|
|
2013-08-31 08:26:52 +02:00
|
|
|
config LINUX_COMMAND_LINE
|
|
|
|
|
string "Linux command line"
|
|
|
|
|
depends on PAYLOAD_LINUX
|
|
|
|
|
default ""
|
|
|
|
|
help
|
|
|
|
|
A command line to add to the Linux kernel.
|
|
|
|
|
|
|
|
|
|
config LINUX_INITRD
|
|
|
|
|
string "Linux initrd"
|
|
|
|
|
depends on PAYLOAD_LINUX
|
|
|
|
|
default ""
|
|
|
|
|
help
|
|
|
|
|
An initrd image to add to the Linux kernel.
|
|
|
|
|
|
2009-09-17 18:21:31 +02:00
|
|
|
endmenu
|
|
|
|
|
|
2009-10-07 18:15:40 +02:00
|
|
|
menu "Debugging"
|
|
|
|
|
|
|
|
|
|
# TODO: Better help text and detailed instructions.
|
2009-08-12 17:00:51 +02:00
|
|
|
config GDB_STUB
|
2009-08-25 02:53:22 +02:00
|
|
|
bool "GDB debugging support"
|
2012-03-25 20:51:16 +02:00
|
|
|
default n
|
2009-08-12 17:00:51 +02:00
|
|
|
help
|
2009-08-25 02:53:22 +02:00
|
|
|
If enabled, you will be able to set breakpoints for gdb debugging.
|
2010-12-11 21:33:41 +01:00
|
|
|
See src/arch/x86/lib/c_start.S for details.
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2012-06-22 15:56:37 +02:00
|
|
|
config GDB_WAIT
|
|
|
|
|
bool "Wait for a GDB connection"
|
|
|
|
|
default n
|
|
|
|
|
depends on GDB_STUB
|
|
|
|
|
help
|
|
|
|
|
If enabled, coreboot will wait for a GDB connection.
|
|
|
|
|
|
2012-05-03 01:33:18 +02:00
|
|
|
config DEBUG_CBFS
|
|
|
|
|
bool "Output verbose CBFS debug messages"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option enables additional CBFS related debug messages.
|
|
|
|
|
|
2010-08-26 14:46:02 +02:00
|
|
|
config HAVE_DEBUG_RAM_SETUP
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
config DEBUG_RAM_SETUP
|
|
|
|
|
bool "Output verbose RAM init debug messages"
|
|
|
|
|
default n
|
2010-08-26 14:46:02 +02:00
|
|
|
depends on HAVE_DEBUG_RAM_SETUP
|
2010-03-05 11:03:50 +01:00
|
|
|
help
|
|
|
|
|
This option enables additional RAM init related debug messages.
|
|
|
|
|
It is recommended to enable this when debugging issues on your
|
|
|
|
|
board which might be RAM init related.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-10-01 16:50:12 +02:00
|
|
|
config HAVE_DEBUG_CAR
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2010-11-10 03:00:32 +01:00
|
|
|
config DEBUG_CAR
|
|
|
|
|
def_bool n
|
|
|
|
|
depends on HAVE_DEBUG_CAR
|
|
|
|
|
|
|
|
|
|
if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
2010-11-10 01:14:32 +01:00
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
|
|
|
# printk(BIOS_DEBUG, ...) calls.
|
2010-10-01 16:50:12 +02:00
|
|
|
config DEBUG_CAR
|
|
|
|
|
bool "Output verbose Cache-as-RAM debug messages"
|
|
|
|
|
default n
|
2010-11-10 03:00:32 +01:00
|
|
|
depends on HAVE_DEBUG_CAR
|
2010-10-01 16:50:12 +02:00
|
|
|
help
|
|
|
|
|
This option enables additional CAR related debug messages.
|
2010-11-10 03:00:32 +01:00
|
|
|
endif
|
2010-10-01 16:50:12 +02:00
|
|
|
|
2010-06-01 21:25:31 +02:00
|
|
|
config DEBUG_PIRQ
|
|
|
|
|
bool "Check PIRQ table consistency"
|
|
|
|
|
default n
|
|
|
|
|
depends on GENERATE_PIRQ_TABLE
|
|
|
|
|
help
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-08-26 14:46:02 +02:00
|
|
|
config HAVE_DEBUG_SMBUS
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
config DEBUG_SMBUS
|
|
|
|
|
bool "Output verbose SMBus debug messages"
|
|
|
|
|
default n
|
2010-08-26 14:46:02 +02:00
|
|
|
depends on HAVE_DEBUG_SMBUS
|
2010-03-05 11:03:50 +01:00
|
|
|
help
|
|
|
|
|
This option enables additional SMBus (and SPD) debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config DEBUG_SMI
|
|
|
|
|
bool "Output verbose SMI debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on HAVE_SMI_HANDLER
|
|
|
|
|
help
|
|
|
|
|
This option enables additional SMI related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-08-01 17:41:14 +02:00
|
|
|
config DEBUG_SMM_RELOCATION
|
|
|
|
|
bool "Debug SMM relocation code"
|
|
|
|
|
default n
|
|
|
|
|
depends on HAVE_SMI_HANDLER
|
|
|
|
|
help
|
|
|
|
|
This option enables additional SMM handler relocation related
|
|
|
|
|
debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-11-10 01:14:32 +01:00
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
|
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
|
|
|
config DEBUG_MALLOC
|
2012-11-14 02:00:01 +01:00
|
|
|
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
|
|
|
bool
|
2010-11-10 01:14:32 +01:00
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option enables additional malloc related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
2011-07-01 23:44:39 +02:00
|
|
|
|
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
|
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
|
|
|
config DEBUG_ACPI
|
2012-11-14 02:00:01 +01:00
|
|
|
prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
|
|
|
bool
|
2011-07-01 23:44:39 +02:00
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option enables additional ACPI related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will slightly increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
2010-11-10 01:14:32 +01:00
|
|
|
|
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
|
|
|
# printk(BIOS_DEBUG, ...) calls.
|
2010-09-08 00:30:15 +02:00
|
|
|
config REALMODE_DEBUG
|
2012-11-14 02:00:01 +01:00
|
|
|
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
|
|
|
bool
|
2010-09-08 00:30:15 +02:00
|
|
|
default n
|
2010-11-10 03:00:32 +01:00
|
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
2010-09-08 00:30:15 +02:00
|
|
|
help
|
|
|
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the time to emulate a ROM.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
config X86EMU_DEBUG
|
|
|
|
|
bool "Output verbose x86emu debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on PCI_OPTION_ROM_RUN_YABEL
|
|
|
|
|
help
|
|
|
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_JMP
|
|
|
|
|
bool "Trace JMP/RETF"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print information about JMP and RETF opcodes from x86emu.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_TRACE
|
|
|
|
|
bool "Trace all opcodes"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print _all_ opcodes that are executed by x86emu.
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
WARNING: This will produce a LOT of output and take a long time.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_PNP
|
|
|
|
|
bool "Log Plug&Play accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print Plug And Play accesses made by option ROMs.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_DISK
|
|
|
|
|
bool "Log Disk I/O"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print Disk I/O related messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_PMM
|
|
|
|
|
bool "Log PMM"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to POST Memory Manager (PMM).
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_VBE
|
|
|
|
|
bool "Debug VESA BIOS Extensions"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to VESA BIOS Extension (VBE) functions.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_INT10
|
|
|
|
|
bool "Redirect INT10 output to console"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Let INT10 (i.e. character output) calls print messages to debug output.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_INTERRUPTS
|
|
|
|
|
bool "Log intXX calls"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to interrupt handling.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_CHECK_VMEM_ACCESS
|
|
|
|
|
bool "Log special memory accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to accesses to certain areas of the virtual
|
|
|
|
|
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_MEM
|
|
|
|
|
bool "Log all memory accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print memory accesses made by option ROM.
|
|
|
|
|
Note: This also includes accesses to fetch instructions.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_IO
|
|
|
|
|
bool "Log IO accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print I/O accesses made by option ROM.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2013-05-15 00:19:49 +02:00
|
|
|
config X86EMU_DEBUG_TIMINGS
|
|
|
|
|
bool "Output timing information"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
|
|
|
|
|
help
|
|
|
|
|
Print timing information needed by i915tool.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2011-11-17 21:50:54 +01:00
|
|
|
config DEBUG_TPM
|
|
|
|
|
bool "Output verbose TPM debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on TPM
|
|
|
|
|
help
|
|
|
|
|
This option enables additional TPM related debug messages.
|
|
|
|
|
|
2012-05-10 20:27:32 +02:00
|
|
|
config DEBUG_SPI_FLASH
|
|
|
|
|
bool "Output verbose SPI flash debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on SPI_FLASH
|
|
|
|
|
help
|
|
|
|
|
This option enables additional SPI flash related debug messages.
|
|
|
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2013-06-06 09:46:37 +02:00
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config DEBUG_USBDEBUG
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bool "Output verbose USB 2.0 EHCI debug dongle messages"
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default n
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depends on USBDEBUG
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help
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This option enables additional USB 2.0 debug dongle related messages.
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Select this to debug the connection of usbdebug dongle. Note that
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you need some other working console to receive the messages.
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2012-04-04 00:07:22 +02:00
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if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
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# Only visible with the right southbridge and loglevel.
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config DEBUG_INTEL_ME
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bool "Verbose logging for Intel Management Engine"
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default n
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help
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Enable verbose logging for Intel Management Engine driver that
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is present on Intel 6-series chipsets.
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endif
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2011-09-02 23:23:41 +02:00
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config TRACE
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bool "Trace function calls"
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default n
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help
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If enabled, every function will print information to console once
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the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
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the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
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of calling function. Please note some printk releated functions
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are omitted from trace to have good looking console dumps.
|
Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 01:23:28 +01:00
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|
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config DEBUG_COVERAGE
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bool "Debug code coverage"
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default n
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|
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depends on COVERAGE
|
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help
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|
|
If enabled, the code coverage hooks in coreboot will output some
|
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|
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information about the coverage data that is dumped.
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|
2009-10-07 18:15:40 +02:00
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endmenu
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2009-10-26 16:14:07 +01:00
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# These probably belong somewhere else, but they are needed somewhere.
|
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|
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config ENABLE_APIC_EXT_ID
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bool
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default n
|
2009-11-12 17:38:03 +01:00
|
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|
|
config WARNINGS_ARE_ERRORS
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|
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bool
|
2010-07-08 18:41:05 +02:00
|
|
|
default y
|
2009-11-27 17:55:13 +01:00
|
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|
|
2010-10-13 08:23:02 +02:00
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|
|
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
|
|
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|
|
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
|
|
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|
|
# mutually exclusive. One of these options must be selected in the
|
|
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|
|
# mainboard Kconfig if the chipset supports enabling and disabling of
|
|
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|
|
# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
|
|
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|
|
# in mainboard/Kconfig to know if the button should be enabled or not.
|
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|
|
config POWER_BUTTON_DEFAULT_ENABLE
|
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|
|
def_bool n
|
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|
|
|
help
|
|
|
|
|
Select when the board has a power button which can optionally be
|
|
|
|
|
disabled by the user.
|
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|
|
config POWER_BUTTON_DEFAULT_DISABLE
|
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|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board has a power button which can optionally be
|
|
|
|
|
enabled by the user, e.g. when the board ships with a jumper over
|
|
|
|
|
the power switch contacts.
|
|
|
|
|
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|
|
|
|
config POWER_BUTTON_FORCE_ENABLE
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board requires that the power button is always
|
|
|
|
|
enabled.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_FORCE_DISABLE
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board requires that the power button is always
|
|
|
|
|
disabled, e.g. when it has been hardwired to ground.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_IS_OPTIONAL
|
|
|
|
|
bool
|
|
|
|
|
default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
|
|
|
|
|
default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
|
|
|
|
|
help
|
|
|
|
|
Internal option that controls ENABLE_POWER_BUTTON visibility.
|
2013-10-31 16:26:23 +01:00
|
|
|
|
|
|
|
|
config REG_SCRIPT
|
|
|
|
|
bool
|
|
|
|
|
default y if ARCH_X86
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Internal option that controls whether we compile in register scripts.
|
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
|
|
|
|
|
|
|
|
# Maximum reboot count
|
|
|
|
|
# TODO: Improve description.
|
|
|
|
|
config MAX_REBOOT_CNT
|
|
|
|
|
int
|
|
|
|
|
default 3
|