2020-05-08 19:28:13 +02:00
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/* inteltool - dump all registers on an Intel CPU + chipset based system */
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util/: Replace GPLv2 boiler plate with SPDX header
Used commands:
perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist)
perl -i -p0e 's|This[\s*]*program[\s*]*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.*[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*This[\s*#]*program[\s*#]*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.*[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
Change-Id: I1008a63b804f355a916221ac994701d7584f60ff
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08 20:48:04 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2008-05-14 00:14:21 +02:00
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#include <stdio.h>
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#include <stdlib.h>
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2017-10-03 15:45:45 +02:00
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#include <string.h>
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2011-11-14 21:40:34 +01:00
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#include <inttypes.h>
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2008-05-14 00:14:21 +02:00
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#include <getopt.h>
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2008-08-20 15:41:24 +02:00
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#include <fcntl.h>
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2008-12-04 16:18:20 +01:00
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#include <sys/mman.h>
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2010-10-24 15:50:13 +02:00
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#include <unistd.h>
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2018-03-13 21:58:52 +01:00
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#include <errno.h>
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2019-10-09 17:35:23 +02:00
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#include <limits.h>
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2013-04-05 20:38:08 +02:00
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#include "inteltool.h"
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2017-04-05 17:39:57 +02:00
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#include "pcr.h"
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2008-05-14 00:14:21 +02:00
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2016-01-05 17:59:06 +01:00
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#ifdef __NetBSD__
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#include <machine/sysarch.h>
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#endif
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2018-03-13 21:58:52 +01:00
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#define MAX_PCR_PORTS 8 /* how often may `--pcr` be specified */
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enum long_only_opts {
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LONG_OPT_PCR = 0x100,
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2019-10-09 17:35:23 +02:00
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LONG_OPT_RANGE = 0x101,
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2018-03-13 21:58:52 +01:00
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};
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2012-10-13 02:19:30 +02:00
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/*
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* http://pci-ids.ucw.cz/read/PC/8086
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* http://en.wikipedia.org/wiki/Intel_Tick-Tock
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* http://en.wikipedia.org/wiki/List_of_Intel_chipsets
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* http://en.wikipedia.org/wiki/Intel_Xeon_chipsets
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*/
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2008-05-14 16:22:59 +02:00
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static const struct {
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uint16_t vendor_id, device_id;
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2008-05-14 23:20:55 +02:00
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char *name;
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2008-05-14 16:22:59 +02:00
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} supported_chips_list[] = {
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2012-10-13 02:19:30 +02:00
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/* Host bridges/DRAM controllers (Northbridges) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" },
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2012-10-13 06:23:52 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82946, "946GZ/PL" },
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2012-10-13 02:19:30 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" },
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2009-11-02 16:01:49 +01:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
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2012-10-13 02:19:30 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
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2017-04-13 18:55:31 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82XX4X,
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"GL40/GS40/GM45/GS45/PM45" },
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2015-08-17 13:04:41 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q45, "Q45/Q43" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G45, "G45/G43/P45/P43" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G41, "G41" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43, "B43 (Base)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43_2, "B43 (Soft)" },
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2012-10-13 02:19:30 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" },
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2017-04-13 18:55:31 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P,
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"Intel i5000P Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X,
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"Intel i5000X Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z,
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"Intel i5000Z Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V,
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"Intel i5000V Memory Controller Hub" },
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2012-10-13 02:19:30 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
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2017-04-13 18:55:31 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX,
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"Atom D400/500 Series" },
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2010-12-17 23:34:58 +01:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
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2012-10-13 02:19:30 +02:00
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/* Host bridges /DRAM controllers integrated in CPUs */
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2017-04-13 18:55:31 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN,
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"0th generation (Nehalem family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN,
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"1st generation (Westmere family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D,
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"2nd generation (Sandy Bridge family) Core Processor (Desktop)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M,
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"2nd generation (Sandy Bridge family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3,
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"2nd generation (Sandy Bridge family) Core Processor (Xeon E3)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D,
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"3rd generation (Ivy Bridge family) Core Processor (Desktop)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M,
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"3rd generation (Ivy Bridge family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3,
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"3rd generation (Ivy Bridge family) Core Processor (Xeon E3 v2)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c,
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"3rd generation (Ivy Bridge family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D,
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"4th generation (Haswell family) Core Processor (Desktop)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M,
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"4th generation (Haswell family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3,
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"4th generation (Haswell family) Core Processor (Xeon E3 v3)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U,
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"4th generation (Haswell family) Core Processor ULT" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U,
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"5th generation (Broadwell family) Core Processor ULT" },
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2022-10-07 00:25:33 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D,
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"5th generation (Broadwell family) Core Processor (Desktop)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M,
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"5th generation (Broadwell family) Core Processor (Mobile)" },
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2017-10-28 14:45:48 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M,
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"6th generation (Skylake-H family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST,
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"6th generation (Skylake-S/H family) Core Processor (Workstation)" },
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2018-01-01 01:48:21 +01:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D,
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"6th generation (Skylake-S family) Core Processor (Desktop)" },
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2017-10-03 16:03:07 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2,
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"6th generation (Skylake-S family) Core Processor (Desktop)" },
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2019-08-27 17:20:08 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E,
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"6th generation (Skylake family) Core Processor Xeon E (Server)" },
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2020-03-14 22:39:30 +01:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U,
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"6th generation (Skylake family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y,
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"6th generation (Skylake family) Core Processor (Mobile)" },
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2014-12-08 06:11:54 +01:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
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2018-07-24 06:09:47 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U,
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"7th generation (Kaby Lake family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y,
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"7th generation (Kaby Lake family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q,
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"7th generation (Kaby Lake family) Core Processor (Mobile)" },
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2019-05-06 17:50:57 +02:00
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3,
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|
"7th generation (Kaby Lake family) Core Processor Xeon E3-1200" },
|
2019-06-12 06:23:46 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1,
|
|
|
|
|
"8th generation (Coffee Lake family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2,
|
|
|
|
|
"8th generation (Whiskey Lake family) Core Processor (Mobile)" },
|
2019-12-29 14:31:01 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U,
|
|
|
|
|
"10th generation (Icelake family) Core Processor (Mobile)" },
|
2020-08-08 18:17:31 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U1,
|
|
|
|
|
"10th generation (Comet Lake family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U2,
|
|
|
|
|
"10th generation (Comet Lake family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U3,
|
|
|
|
|
"10th generation (Comet Lake family) Core Processor (Mobile)" },
|
2020-10-23 03:40:41 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE,
|
|
|
|
|
"Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
|
2021-05-03 22:12:23 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
|
|
|
|
|
"Xeon Scalable Processor 4th generation (Sapphire Rapids SP)" },
|
2021-07-09 16:00:16 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2,
|
|
|
|
|
"11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4,
|
|
|
|
|
"11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2,
|
|
|
|
|
"11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4,
|
|
|
|
|
"11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4,
|
|
|
|
|
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6,
|
|
|
|
|
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8,
|
|
|
|
|
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
|
2022-04-05 10:40:03 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_8,
|
|
|
|
|
"12th generation (Alder Lake S family) Core Processor (Desktop)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_4,
|
|
|
|
|
"12th generation (Alder Lake S family) Core Processor (Desktop)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_4,
|
|
|
|
|
"12th generation (Alder Lake S family) Core Processor (Desktop)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_0,
|
|
|
|
|
"12th generation (Alder Lake S family) Core Processor (Desktop)" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_0,
|
|
|
|
|
"12th generation (Alder Lake S family) Core Processor (Desktop)" },
|
2022-08-17 10:28:20 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8,
|
|
|
|
|
"12th generation (Alder Lake P family) Core Processor"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8,
|
|
|
|
|
"12th generation (Alder Lake P family) Core Processor"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8,
|
|
|
|
|
"12th generation (Alder Lake P family) Core Processor"},
|
|
|
|
|
|
2012-10-13 02:19:30 +02:00
|
|
|
/* Southbridges (LPC controllers) */
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
|
2017-04-10 22:26:13 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
|
2021-11-14 15:34:02 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10D, "ICH10D" },
|
2020-07-09 14:16:39 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10DO, "ICH10DO" },
|
2009-06-30 16:11:42 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
|
2010-05-30 14:33:12 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
|
2008-12-04 16:18:20 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
|
2015-03-01 10:14:15 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8ME, "ICH8M-E" },
|
2010-08-17 10:33:44 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
|
2008-05-14 16:22:59 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
|
2008-05-14 22:05:00 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
|
2008-05-14 16:22:59 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
|
2008-05-14 22:05:00 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
|
2010-04-21 08:23:19 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
|
2010-12-17 23:34:58 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" },
|
2008-05-14 16:22:59 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
|
2008-05-17 23:33:35 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
|
2008-05-14 16:22:59 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
|
2009-09-30 19:05:46 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
|
2012-10-13 02:19:30 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
|
2013-05-28 11:30:25 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_DESKTOP, "3400 Desktop" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_MOBILE, "3400 Mobile" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_P55, "P55" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM55, "PM55" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H55, "H55" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM57, "QM57" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H57, "H57" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM55, "HM55" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q57, "Q57" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM57, "HM57" },
|
2017-04-13 18:55:31 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF,
|
|
|
|
|
"3400 Mobile SFF" },
|
2013-05-28 11:30:25 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B55_A, "B55" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS57, "QS57" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400, "3400" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3420, "3420" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3450, "3450" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B55_B, "B55" },
|
2013-03-29 17:57:15 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z68, "Z68" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_P67, "P67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UM67, "UM67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65, "HM65" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H67, "H67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM67, "HM67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q65, "Q65" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS67, "QS67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q67, "Q67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM67, "QM67" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B65, "B65" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C202, "C202" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C204, "C204" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C206, "C206" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H61, "H61" },
|
2012-10-13 02:19:30 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, 0x1d40, "X79" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, 0x1d41, "X79" },
|
2013-03-29 17:57:15 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z77, "Z77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z75, "Z75" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q77, "Q77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q75, "Q75" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B75, "B75" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H77, "H77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C216, "C216" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM77, "QM77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS77, "QS77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM77, "HM77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UM77, "UM77" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM76, "HM76" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" },
|
2019-12-29 14:31:01 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_U,
|
|
|
|
|
"Icelake U LPC" },
|
2017-04-13 18:55:31 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL,
|
|
|
|
|
"Lynx Point Low Power Full Featured Engineering Sample" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM,
|
|
|
|
|
"Lynx Point Low Power Premium SKU" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE,
|
|
|
|
|
"Lynx Point Low Power Base SKU" },
|
2020-02-21 18:37:51 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM,
|
|
|
|
|
"Wildcat Point Low Power Premium SKU" },
|
2017-04-13 18:55:31 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP,
|
2020-02-21 18:37:51 +01:00
|
|
|
"Wildcat Point Low Power Base SKU" },
|
2012-10-13 02:19:30 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
|
2014-12-08 06:11:54 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },
|
2017-10-28 14:45:48 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE,
|
|
|
|
|
"Sunrise Point Desktop Engineering Sample" },
|
2019-02-19 23:49:11 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE,
|
|
|
|
|
"Sunrise Point-LP Engineering Sample" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL,
|
|
|
|
|
"Sunrise Point-LP U Base/Skylake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL,
|
|
|
|
|
"Sunrise Point-LP Y Premium/Skylake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL,
|
|
|
|
|
"Sunrise Point-LP U Premium/Skylake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL,
|
|
|
|
|
"Sunrise Point-LP U Base/Kabylake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL,
|
|
|
|
|
"Sunrise Point-LP Y Premium/Kabylake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL,
|
|
|
|
|
"Sunrise Point-LP U Premium/Kabylake" },
|
2018-07-24 06:09:47 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE,
|
2019-02-19 23:49:11 +01:00
|
|
|
"Sunrise Point-LP U iHDCP 2.2 Base/Kabylake" },
|
2018-07-24 06:09:47 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM,
|
2019-02-19 23:49:11 +01:00
|
|
|
"Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" },
|
2018-07-24 06:09:47 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM,
|
2019-02-19 23:49:11 +01:00
|
|
|
"Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" },
|
2019-06-12 06:23:46 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM,
|
|
|
|
|
"Cannon Point-LP U Premium/CoffeeLake/Whiskeylake" },
|
2020-08-08 18:17:31 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM,
|
|
|
|
|
"Comet Point-LP U Premium/Cometlake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE,
|
|
|
|
|
"Comet Point-LP U Base/Cometlake" },
|
2021-07-09 16:00:16 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER,
|
|
|
|
|
"Tiger Point U Engineering Sample" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM,
|
|
|
|
|
"Tiger Point U Premium/Tigerlake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE,
|
|
|
|
|
"Tiger Point U Base/Tigerlake" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER,
|
|
|
|
|
"Tiger Point Y Engineering Sample" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM,
|
|
|
|
|
"Tiger Point Y Premium/Tigerlake" },
|
2017-10-28 14:45:48 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q170, "Q170" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q150, "Q150" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B150, "B150" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C236, "C236" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C232, "C232" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM170, "QM170" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM170, "HM170" },
|
2017-03-30 17:45:36 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" },
|
2017-10-28 14:45:48 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" },
|
2019-08-16 18:15:12 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621, "C621" },
|
2020-11-03 13:46:41 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621A, "C621A" },
|
2019-08-16 18:15:12 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C622, "C622" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C624, "C624" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C625, "C625" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C626, "C626" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627, "C627" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628, "C628" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C629, "C629" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C624_SUPER, "C624 Super SKU" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_1, "C627 Super SKU" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621_SUPER, "C621 Super SKU" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_2, "C627 Super SKU" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628_SUPER, "C628 Super SKU" },
|
2021-05-03 23:06:22 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG, "Emmits Burg" },
|
2021-06-25 11:07:32 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H270, "H270" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z270, "Z270" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q270, "Q270" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q250, "Q250" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B250, "B250" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z370, "Z370" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310C, "H310C" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X299, "X299" },
|
2019-02-19 11:51:34 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q370, "Q370" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B360, "B360" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C246, "C246" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C242, "C242" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM370, "QM370" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM370, "HM370" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM246, "CM246" },
|
2018-06-20 01:52:19 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE, "C8 Mobile"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP, "C8 Desktop"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, "Z87"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z85, "Z85"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM86, "HM86"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87, "H87"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM87, "HM87"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q85, "Q85"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q87, "Q87"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM87, "QM87"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B85, "B85"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C222, "C222"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},
|
2022-10-07 00:18:04 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C9_MOBILE, "C9 Mobile"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C9_DESKTOP, "C9 Desktop"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM97, "HM97"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z97, "Z97"},
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H97, "H97"},
|
2018-11-20 12:10:29 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
|
2019-01-12 19:20:50 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" },
|
2021-10-22 10:31:22 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" },
|
2021-07-09 16:00:16 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W580, "W580" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C256, "C256" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C252, "C252" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM570, "HM570" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM580, "QM580" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM590, "WM590" },
|
2022-04-05 10:40:03 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H610, "H610" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B660, "B660" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H670, "H670" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q670, "Q670" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z690, "Z690" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W680, "W680" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W685, "W685" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM690, "WM690" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM670, "HM670" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM790, "WM790" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM770, "HM770" },
|
2022-10-17 14:30:24 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" },
|
2023-03-10 19:44:04 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" },
|
2022-10-17 14:30:24 +02:00
|
|
|
|
2017-11-07 19:51:21 +01:00
|
|
|
/* Intel GPUs */
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
|
|
|
|
|
"Intel(R) G35 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS_1,
|
|
|
|
|
"Intel(R) G35 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_965_EXPRESS,
|
|
|
|
|
"Mobile Intel(R) 965 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_965_EXPRESS_1,
|
|
|
|
|
"Mobile Intel(R) 965 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_965_EXPRESS_2,
|
|
|
|
|
"Mobile Intel(R) 965 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_965_EXPRESS_3,
|
|
|
|
|
"Mobile Intel(R) 965 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_4_SERIES,
|
|
|
|
|
"Mobile Intel(R) 4 Series Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_4_SERIES_1,
|
|
|
|
|
"Mobile Intel(R) 4 Series Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G45,
|
|
|
|
|
"Intel(R) G45/G43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G45_1,
|
|
|
|
|
"Intel(R) G45/G43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q45,
|
|
|
|
|
"Intel(R) Q45/Q43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q45_1,
|
|
|
|
|
"Intel(R) Q45/Q43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G41,
|
|
|
|
|
"Intel(R) G41 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G41_1,
|
|
|
|
|
"Intel(R) G41 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B43,
|
|
|
|
|
"Intel(R) B43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B43_1,
|
|
|
|
|
"Intel(R) B43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B43_2,
|
|
|
|
|
"Intel(R) B43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B43_3,
|
|
|
|
|
"Intel(R) B43 Express Chipset Family" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_GRAPHICS,
|
|
|
|
|
"Intel(R) HD Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_GRAPHICS_1,
|
|
|
|
|
"Intel(R) HD Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_GRAPHICS_2,
|
|
|
|
|
"Intel(R) HD Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_2000,
|
|
|
|
|
"Intel(R) HD 2000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_2000_1,
|
|
|
|
|
"Intel(R) HD 2000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_3000,
|
|
|
|
|
"Intel(R) HD 3000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_3000_1,
|
|
|
|
|
"Intel(R) HD 3000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_3000_2,
|
|
|
|
|
"Intel(R) HD 3000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_3000_3,
|
|
|
|
|
"Intel(R) HD 3000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_3000_4,
|
|
|
|
|
"Intel(R) HD 3000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_3000_5,
|
|
|
|
|
"Intel(R) HD 3000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_2500,
|
|
|
|
|
"Intel(R) HD 2500 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_2500_1,
|
|
|
|
|
"Intel(R) HD 2500 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_2500_2,
|
|
|
|
|
"Intel(R) HD 2500 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4000,
|
|
|
|
|
"Intel(R) HD 4000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4000_1,
|
|
|
|
|
"Intel(R) HD 4000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4000_2,
|
|
|
|
|
"Intel(R) HD 4000 Graphics" },
|
2019-07-26 15:09:18 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4400,
|
|
|
|
|
"Intel(R) HD 4400 Graphics" },
|
2022-05-20 08:50:21 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4400_1,
|
|
|
|
|
"Intel(R) HD 4400 Graphics" },
|
2017-11-07 19:51:21 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4600,
|
|
|
|
|
"Intel(R) HD 4600 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_4600_1,
|
|
|
|
|
"Intel(R) HD 4600 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_5000,
|
|
|
|
|
"Intel(R) HD 5000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_5000_1,
|
|
|
|
|
"Intel(R) HD 5000 Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_5000_2,
|
|
|
|
|
"Intel(R) HD 5000 Graphics" },
|
2019-01-02 14:44:54 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_510,
|
|
|
|
|
"Intel(R) HD Graphics 510" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_515,
|
|
|
|
|
"Intel(R) HD Graphics 515" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_520,
|
|
|
|
|
"Intel(R) HD Graphics 520" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_1,
|
|
|
|
|
"Intel(R) HD Graphics 530" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2,
|
|
|
|
|
"Intel(R) HD Graphics 530" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1,
|
|
|
|
|
"Intel(R) UHD Graphics 615" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2,
|
|
|
|
|
"Intel(R) UHD Graphics 615" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_617,
|
|
|
|
|
"Intel(R) UHD Graphics 617" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_1,
|
|
|
|
|
"Intel(R) UHD Graphics 620" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_2,
|
|
|
|
|
"Intel(R) UHD Graphics 620" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_3,
|
|
|
|
|
"Intel(R) UHD Graphics 620" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_1,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_2,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_3,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_4,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_5,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_6,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_7,
|
|
|
|
|
"Intel(R) UHD Graphics 630" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_640,
|
|
|
|
|
"Intel(R) UHD Graphics 640" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_540,
|
|
|
|
|
"Intel(R) Iris Graphics 540" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_550,
|
|
|
|
|
"Intel(R) Iris Graphics 550" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PRO_580,
|
|
|
|
|
"Intel(R) Iris Pro Graphics 580" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_650,
|
|
|
|
|
"Intel(R) Iris Plus Graphics 650" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_655,
|
|
|
|
|
"Intel(R) Iris Plus Graphics 655" },
|
2019-12-29 14:31:01 +01:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7,
|
|
|
|
|
"Intel(R) Iris Plus Graphics G7" },
|
2021-07-09 16:00:16 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_UY,
|
|
|
|
|
"Intel(R) Iris Xe Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_Y,
|
|
|
|
|
"Intel(R) Iris Xe Graphics" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1,
|
|
|
|
|
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1_2,
|
|
|
|
|
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1,
|
|
|
|
|
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2,
|
|
|
|
|
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
|
2022-04-05 10:40:03 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1,
|
|
|
|
|
"Intel(R) AlderLake-S GT1" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_2,
|
|
|
|
|
"Intel(R) AlderLake-S GT1" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_3,
|
|
|
|
|
"Intel(R) AlderLake-S GT1" },
|
|
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_4,
|
|
|
|
|
"Intel(R) AlderLake-S GT1" },
|
2020-08-08 18:17:31 +02:00
|
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS,
|
|
|
|
|
"Intel(R) UHD Graphics" },
|
2008-05-14 16:22:59 +02:00
|
|
|
};
|
|
|
|
|
|
2009-09-01 11:52:14 +02:00
|
|
|
#ifndef __DARWIN__
|
2008-12-04 16:18:20 +01:00
|
|
|
static int fd_mem;
|
|
|
|
|
|
2011-03-18 23:08:39 +01:00
|
|
|
void *map_physical(uint64_t phys_addr, size_t len)
|
2008-12-04 16:18:20 +01:00
|
|
|
{
|
|
|
|
|
void *virt_addr;
|
|
|
|
|
|
|
|
|
|
virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
|
|
|
|
|
fd_mem, (off_t) phys_addr);
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2008-12-04 16:18:20 +01:00
|
|
|
if (virt_addr == MAP_FAILED) {
|
2011-11-14 21:40:34 +01:00
|
|
|
printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n",
|
|
|
|
|
phys_addr, len);
|
2008-12-04 16:18:20 +01:00
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return virt_addr;
|
|
|
|
|
}
|
|
|
|
|
|
2009-09-01 11:52:14 +02:00
|
|
|
void unmap_physical(void *virt_addr, size_t len)
|
2008-12-04 16:18:20 +01:00
|
|
|
{
|
|
|
|
|
munmap(virt_addr, len);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2008-05-14 00:14:21 +02:00
|
|
|
|
2019-07-01 19:21:55 +02:00
|
|
|
static void print_version(void)
|
2008-05-14 00:14:21 +02:00
|
|
|
{
|
|
|
|
|
printf("inteltool v%s -- ", INTELTOOL_VERSION);
|
|
|
|
|
printf("Copyright (C) 2008 coresystems GmbH\n\n");
|
|
|
|
|
printf(
|
|
|
|
|
"This program is free software: you can redistribute it and/or modify\n"
|
|
|
|
|
"it under the terms of the GNU General Public License as published by\n"
|
|
|
|
|
"the Free Software Foundation, version 2 of the License.\n\n"
|
|
|
|
|
"This program is distributed in the hope that it will be useful,\n"
|
|
|
|
|
"but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
|
|
|
|
|
"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
|
2016-01-12 21:30:50 +01:00
|
|
|
"GNU General Public License for more details.\n\n");
|
2008-05-14 00:14:21 +02:00
|
|
|
}
|
|
|
|
|
|
2019-07-01 19:21:55 +02:00
|
|
|
static void print_usage(const char *name)
|
2008-05-14 00:14:21 +02:00
|
|
|
{
|
2020-03-13 22:22:26 +01:00
|
|
|
printf("usage: %s [-vh?gGrplmedPMaAsfSRx]\n", name);
|
2008-05-14 00:14:21 +02:00
|
|
|
printf("\n"
|
|
|
|
|
" -v | --version: print the version\n"
|
|
|
|
|
" -h | --help: print this help\n\n"
|
2015-01-03 02:52:10 +01:00
|
|
|
" -s | --spi: dump southbridge spi and bios_cntrl registers\n"
|
2016-05-10 23:16:33 +02:00
|
|
|
" -f | --gfx: dump graphics registers (UNSAFE: may hang system!)\n"
|
2016-06-08 16:39:22 +02:00
|
|
|
" -R | --ahci: dump AHCI registers\n"
|
2014-08-25 23:59:42 +02:00
|
|
|
" -g | --gpio: dump southbridge GPIO registers\n"
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
" -G | --gpio-diffs: show GPIO differences from defaults\n"
|
2014-08-25 23:59:42 +02:00
|
|
|
" -r | --rcba: dump southbridge RCBA registers\n"
|
|
|
|
|
" -p | --pmbase: dump southbridge Power Management registers\n\n"
|
2020-03-13 22:22:26 +01:00
|
|
|
" -l | --lpc: dump southbridge LPC/eSPI Interface registers\n\n"
|
2008-05-14 00:14:21 +02:00
|
|
|
" -m | --mchbar: dump northbridge Memory Controller registers\n"
|
2016-05-05 17:29:39 +02:00
|
|
|
" -S FILE | --spd=FILE: create a file storing current timings (implies -m)\n"
|
2008-05-14 00:14:21 +02:00
|
|
|
" -e | --epbar: dump northbridge EPBAR registers\n"
|
|
|
|
|
" -d | --dmibar: dump northbridge DMIBAR registers\n"
|
|
|
|
|
" -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n"
|
|
|
|
|
" -M | --msrs: dump CPU MSRs\n"
|
2019-10-09 17:35:23 +02:00
|
|
|
" --cpu-range <start>[-<end>]: (optional) set CPU cores range for -M (--msrs) option\n"
|
2012-01-08 15:27:18 +01:00
|
|
|
" -A | --ambs: dump AMB registers\n"
|
2017-07-24 22:53:26 +02:00
|
|
|
" -x | --sgx: dump SGX status\n"
|
2020-09-03 20:28:19 +02:00
|
|
|
" -t | --tme: dump TME status\n"
|
2022-12-19 18:52:34 +01:00
|
|
|
" -k | --keylocker: dump Key Locker status\n"
|
2016-05-10 23:16:33 +02:00
|
|
|
" -a | --all: dump all known (safe) registers\n"
|
2018-03-13 21:58:52 +01:00
|
|
|
" --pcr=PORT_ID: dump all registers of a PCR port\n"
|
|
|
|
|
" (may be specified max %d times)\n"
|
|
|
|
|
"\n", MAX_PCR_PORTS);
|
2008-05-14 00:14:21 +02:00
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-25 00:16:22 +02:00
|
|
|
static void print_system_info(struct pci_dev *nb, struct pci_dev *sb, struct pci_dev *gfx)
|
|
|
|
|
{
|
|
|
|
|
unsigned int id, i;
|
|
|
|
|
char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown";
|
|
|
|
|
|
|
|
|
|
id = cpuid(1);
|
|
|
|
|
|
|
|
|
|
/* Determine names */
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) {
|
|
|
|
|
if (nb->device_id == supported_chips_list[i].device_id)
|
|
|
|
|
nbname = supported_chips_list[i].name;
|
|
|
|
|
}
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) {
|
|
|
|
|
if (sb->device_id == supported_chips_list[i].device_id)
|
|
|
|
|
sbname = supported_chips_list[i].name;
|
|
|
|
|
}
|
|
|
|
|
if (gfx) {
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
|
|
|
|
|
if (gfx->device_id == supported_chips_list[i].device_id)
|
|
|
|
|
gfxname = supported_chips_list[i].name;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Intel has suggested applications to display the family of a CPU as
|
|
|
|
|
* the sum of the "Family" and the "Extended Family" fields shown
|
|
|
|
|
* above, and the model as the sum of the "Model" and the 4-bit
|
|
|
|
|
* left-shifted "Extended Model" fields.
|
|
|
|
|
* http://download.intel.com/design/processor/applnots/24161832.pdf
|
|
|
|
|
*/
|
|
|
|
|
printf("CPU: ID 0x%x, Processor Type 0x%x, Family 0x%x, Model 0x%x, Stepping 0x%x\n",
|
|
|
|
|
id, (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
|
|
|
|
|
((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
|
|
|
|
|
|
|
|
|
|
printf("Northbridge: %04x:%04x (%s)\n",
|
|
|
|
|
nb->vendor_id, nb->device_id, nbname);
|
|
|
|
|
|
|
|
|
|
printf("Southbridge: %04x:%04x (%s)\n",
|
|
|
|
|
sb->vendor_id, sb->device_id, sbname);
|
|
|
|
|
|
|
|
|
|
if (gfx)
|
|
|
|
|
printf("IGD: %04x:%04x (%s)\n",
|
|
|
|
|
gfx->vendor_id, gfx->device_id, gfxname);
|
|
|
|
|
}
|
|
|
|
|
|
2008-05-14 00:14:21 +02:00
|
|
|
int main(int argc, char *argv[])
|
|
|
|
|
{
|
|
|
|
|
struct pci_access *pacc;
|
2016-06-08 16:39:22 +02:00
|
|
|
struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev;
|
2016-05-05 17:29:39 +02:00
|
|
|
const char *dump_spd_file = NULL;
|
2017-08-09 11:30:14 +02:00
|
|
|
int opt, option_index = 0;
|
2008-05-14 00:14:21 +02:00
|
|
|
|
2008-05-14 23:20:55 +02:00
|
|
|
int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
|
|
|
|
|
int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
|
2012-01-08 15:27:18 +01:00
|
|
|
int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0;
|
2020-09-03 20:28:19 +02:00
|
|
|
int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0, dump_tme = 0;
|
2022-12-19 18:52:34 +01:00
|
|
|
int dump_lpc = 0, dump_keylocker = 0;
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
int show_gpio_diffs = 0;
|
2018-03-13 21:58:52 +01:00
|
|
|
size_t pcr_count = 0;
|
|
|
|
|
uint8_t dump_pcr[MAX_PCR_PORTS];
|
2008-05-14 00:14:21 +02:00
|
|
|
|
2019-10-09 17:35:23 +02:00
|
|
|
unsigned int cores_range_start = 0, cores_range_end = UINT_MAX;
|
|
|
|
|
|
2008-05-14 00:14:21 +02:00
|
|
|
static struct option long_options[] = {
|
|
|
|
|
{"version", 0, 0, 'v'},
|
|
|
|
|
{"help", 0, 0, 'h'},
|
|
|
|
|
{"gpios", 0, 0, 'g'},
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
{"gpio-diffs", 0, 0, 'G'},
|
2008-05-14 00:14:21 +02:00
|
|
|
{"mchbar", 0, 0, 'm'},
|
|
|
|
|
{"rcba", 0, 0, 'r'},
|
|
|
|
|
{"pmbase", 0, 0, 'p'},
|
2020-03-13 22:22:26 +01:00
|
|
|
{"lpc", 0, 0, 'l'},
|
2008-05-14 00:14:21 +02:00
|
|
|
{"epbar", 0, 0, 'e'},
|
|
|
|
|
{"dmibar", 0, 0, 'd'},
|
|
|
|
|
{"pciexpress", 0, 0, 'P'},
|
|
|
|
|
{"msrs", 0, 0, 'M'},
|
2019-10-09 17:35:23 +02:00
|
|
|
{"cpu-range", required_argument, 0, LONG_OPT_RANGE},
|
2012-01-08 15:27:18 +01:00
|
|
|
{"ambs", 0, 0, 'A'},
|
2015-01-03 02:52:10 +01:00
|
|
|
{"spi", 0, 0, 's'},
|
2015-10-10 13:20:32 +02:00
|
|
|
{"spd", 0, 0, 'S'},
|
2008-05-14 00:14:21 +02:00
|
|
|
{"all", 0, 0, 'a'},
|
2015-05-20 14:04:41 +02:00
|
|
|
{"gfx", 0, 0, 'f'},
|
2016-06-08 16:39:22 +02:00
|
|
|
{"ahci", 0, 0, 'R'},
|
2017-07-24 22:53:26 +02:00
|
|
|
{"sgx", 0, 0, 'x'},
|
2018-03-13 21:58:52 +01:00
|
|
|
{"pcr", required_argument, 0, LONG_OPT_PCR},
|
2020-09-03 20:28:19 +02:00
|
|
|
{"tme", 0, 0, 't'},
|
2022-12-19 18:52:34 +01:00
|
|
|
{"keylocker", 0, 0, 'k'},
|
2008-05-14 00:14:21 +02:00
|
|
|
{0, 0, 0, 0}
|
|
|
|
|
};
|
|
|
|
|
|
2022-12-19 18:52:34 +01:00
|
|
|
while ((opt = getopt_long(argc, argv, "vh?gGrplmedPMaAsfRS:xtk",
|
2008-05-14 23:20:55 +02:00
|
|
|
long_options, &option_index)) != EOF) {
|
2008-05-14 00:14:21 +02:00
|
|
|
switch (opt) {
|
|
|
|
|
case 'v':
|
|
|
|
|
print_version();
|
|
|
|
|
exit(0);
|
|
|
|
|
break;
|
2015-10-10 13:20:32 +02:00
|
|
|
case 'S':
|
|
|
|
|
dump_spd_file = optarg;
|
|
|
|
|
dump_mchbar = 1;
|
|
|
|
|
break;
|
2008-05-14 00:14:21 +02:00
|
|
|
case 'g':
|
|
|
|
|
dump_gpios = 1;
|
|
|
|
|
break;
|
2015-05-20 14:04:41 +02:00
|
|
|
case 'f':
|
|
|
|
|
dump_gfx = 1;
|
|
|
|
|
break;
|
2016-06-08 16:39:22 +02:00
|
|
|
case 'R':
|
|
|
|
|
dump_ahci = 1;
|
|
|
|
|
break;
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
case 'G':
|
|
|
|
|
show_gpio_diffs = 1;
|
|
|
|
|
break;
|
2008-05-14 00:14:21 +02:00
|
|
|
case 'm':
|
|
|
|
|
dump_mchbar = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'r':
|
|
|
|
|
dump_rcba = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'p':
|
|
|
|
|
dump_pmbase = 1;
|
|
|
|
|
break;
|
2020-03-13 22:22:26 +01:00
|
|
|
case 'l':
|
|
|
|
|
dump_lpc = 1;
|
|
|
|
|
break;
|
2008-05-14 00:14:21 +02:00
|
|
|
case 'e':
|
|
|
|
|
dump_epbar = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'd':
|
|
|
|
|
dump_dmibar = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'P':
|
|
|
|
|
dump_pciexbar = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'M':
|
|
|
|
|
dump_coremsrs = 1;
|
|
|
|
|
break;
|
2019-10-09 17:35:23 +02:00
|
|
|
case LONG_OPT_RANGE:
|
|
|
|
|
if (strlen(optarg) == 0) {
|
|
|
|
|
print_usage(argv[0]);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
const int sscanf_ret = sscanf(optarg, "%u-%u", &cores_range_start, &cores_range_end);
|
|
|
|
|
if (sscanf_ret == 1) {
|
|
|
|
|
/* the end of the range is not specified - only for one core */
|
|
|
|
|
cores_range_end = cores_range_start;
|
|
|
|
|
} else if (sscanf_ret != 2) {
|
|
|
|
|
print_usage(argv[0]);
|
|
|
|
|
exit(1);
|
|
|
|
|
} else if (cores_range_end < cores_range_start) {
|
|
|
|
|
printf("Error: invalid cores range <%u-%u>!\n",
|
|
|
|
|
cores_range_start, cores_range_end);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
break;
|
2008-05-14 00:14:21 +02:00
|
|
|
case 'a':
|
|
|
|
|
dump_gpios = 1;
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
show_gpio_diffs = 1;
|
2008-05-14 00:14:21 +02:00
|
|
|
dump_mchbar = 1;
|
|
|
|
|
dump_rcba = 1;
|
|
|
|
|
dump_pmbase = 1;
|
2020-03-13 22:22:26 +01:00
|
|
|
dump_lpc = 1;
|
2008-05-14 00:14:21 +02:00
|
|
|
dump_epbar = 1;
|
|
|
|
|
dump_dmibar = 1;
|
|
|
|
|
dump_pciexbar = 1;
|
|
|
|
|
dump_coremsrs = 1;
|
2012-01-08 15:27:18 +01:00
|
|
|
dump_ambs = 1;
|
2015-01-03 02:52:10 +01:00
|
|
|
dump_spi = 1;
|
2016-06-08 16:39:22 +02:00
|
|
|
dump_ahci = 1;
|
2017-07-24 22:53:26 +02:00
|
|
|
dump_sgx = 1;
|
2020-09-03 20:28:19 +02:00
|
|
|
dump_tme = 1;
|
2022-12-19 18:52:34 +01:00
|
|
|
dump_keylocker = 1;
|
2012-01-08 15:27:18 +01:00
|
|
|
break;
|
|
|
|
|
case 'A':
|
|
|
|
|
dump_ambs = 1;
|
2008-05-14 00:14:21 +02:00
|
|
|
break;
|
2015-01-03 02:52:10 +01:00
|
|
|
case 's':
|
|
|
|
|
dump_spi = 1;
|
|
|
|
|
break;
|
2017-07-24 22:53:26 +02:00
|
|
|
case 'x':
|
|
|
|
|
dump_sgx = 1;
|
|
|
|
|
break;
|
2020-09-03 20:28:19 +02:00
|
|
|
case 't':
|
|
|
|
|
dump_tme = 1;
|
|
|
|
|
break;
|
2022-12-19 18:52:34 +01:00
|
|
|
case 'k':
|
|
|
|
|
dump_keylocker = 1;
|
|
|
|
|
break;
|
2018-03-13 21:58:52 +01:00
|
|
|
case LONG_OPT_PCR:
|
|
|
|
|
if (pcr_count < MAX_PCR_PORTS) {
|
|
|
|
|
errno = 0;
|
|
|
|
|
const unsigned long int pcr =
|
|
|
|
|
strtoul(optarg, NULL, 0);
|
|
|
|
|
if (strlen(optarg) == 0 || errno) {
|
|
|
|
|
print_usage(argv[0]);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
dump_pcr[pcr_count++] = (uint8_t)pcr;
|
|
|
|
|
} else {
|
|
|
|
|
print_usage(argv[0]);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
break;
|
2008-05-14 00:14:21 +02:00
|
|
|
case 'h':
|
|
|
|
|
case '?':
|
|
|
|
|
default:
|
|
|
|
|
print_usage(argv[0]);
|
|
|
|
|
exit(0);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-24 15:50:13 +02:00
|
|
|
#if defined(__FreeBSD__)
|
2013-04-05 20:38:08 +02:00
|
|
|
if (open("/dev/io", O_RDWR) < 0) {
|
2010-10-24 15:50:13 +02:00
|
|
|
perror("/dev/io");
|
2016-01-05 17:59:06 +01:00
|
|
|
#elif defined(__NetBSD__)
|
|
|
|
|
# ifdef __i386__
|
|
|
|
|
if (i386_iopl(3)) {
|
|
|
|
|
perror("iopl");
|
|
|
|
|
# else
|
|
|
|
|
if (x86_64_iopl(3)) {
|
|
|
|
|
perror("iopl");
|
|
|
|
|
# endif
|
2010-10-24 15:50:13 +02:00
|
|
|
#else
|
2008-05-14 23:20:55 +02:00
|
|
|
if (iopl(3)) {
|
2010-10-24 15:50:13 +02:00
|
|
|
perror("iopl");
|
|
|
|
|
#endif
|
2008-05-14 23:20:55 +02:00
|
|
|
printf("You need to be root.\n");
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
2008-05-14 00:14:21 +02:00
|
|
|
|
2009-09-01 11:52:14 +02:00
|
|
|
#ifndef __DARWIN__
|
2008-05-14 00:14:21 +02:00
|
|
|
if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
|
|
|
|
|
perror("Can not open /dev/mem");
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
2008-12-04 16:18:20 +01:00
|
|
|
#endif
|
2008-05-14 00:14:21 +02:00
|
|
|
|
|
|
|
|
pacc = pci_alloc();
|
2017-04-05 17:39:57 +02:00
|
|
|
pacc->method = PCI_ACCESS_I386_TYPE1;
|
2008-05-14 00:14:21 +02:00
|
|
|
pci_init(pacc);
|
|
|
|
|
pci_scan_bus(pacc);
|
|
|
|
|
|
|
|
|
|
/* Find the required devices */
|
2010-04-27 08:56:47 +02:00
|
|
|
for (dev = pacc->devices; dev; dev = dev->next) {
|
2009-09-30 19:05:46 +02:00
|
|
|
pci_fill_info(dev, PCI_FILL_CLASS);
|
|
|
|
|
/* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
|
|
|
|
|
if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
|
2014-11-05 21:27:01 +01:00
|
|
|
if (sb == NULL) {
|
2009-09-30 19:05:46 +02:00
|
|
|
sb = dev;
|
2014-11-05 21:27:01 +01:00
|
|
|
} else {
|
2009-09-30 19:05:46 +02:00
|
|
|
fprintf(stderr, "Multiple devices with class ID"
|
|
|
|
|
" 0x0601, using %02x%02x:%02x.%02x\n",
|
2014-11-05 21:27:01 +01:00
|
|
|
sb->domain, sb->bus, sb->dev, sb->func);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2009-09-30 19:05:46 +02:00
|
|
|
}
|
|
|
|
|
}
|
2008-05-14 00:14:21 +02:00
|
|
|
|
|
|
|
|
if (!sb) {
|
|
|
|
|
printf("No southbridge found.\n");
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-31 12:09:58 +02:00
|
|
|
pci_fill_info(sb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
|
2008-05-14 00:14:21 +02:00
|
|
|
|
|
|
|
|
if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
|
|
|
|
|
printf("Not an Intel(R) southbridge.\n");
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
|
|
|
|
|
if (!nb) {
|
|
|
|
|
printf("No northbridge found.\n");
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-31 12:09:58 +02:00
|
|
|
pci_fill_info(nb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
|
2008-05-14 00:14:21 +02:00
|
|
|
|
|
|
|
|
if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
|
|
|
|
|
printf("Not an Intel(R) northbridge.\n");
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-20 14:04:41 +02:00
|
|
|
gfx = pci_get_dev(pacc, 0, 0, 0x02, 0);
|
|
|
|
|
if (gfx) {
|
2017-03-31 12:09:58 +02:00
|
|
|
pci_fill_info(gfx, PCI_FILL_IDENT | PCI_FILL_BASES |
|
|
|
|
|
PCI_FILL_CLASS);
|
2020-10-23 03:42:25 +02:00
|
|
|
if ((gfx->device_class & 0xff00) != 0x0300)
|
|
|
|
|
gfx = NULL;
|
|
|
|
|
else if (gfx->vendor_id != PCI_VENDOR_ID_INTEL)
|
|
|
|
|
gfx = NULL;
|
2015-05-20 14:04:41 +02:00
|
|
|
}
|
|
|
|
|
|
2017-03-30 17:47:24 +02:00
|
|
|
if (sb->device_id == PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC) {
|
2016-11-18 00:51:13 +01:00
|
|
|
ahci = pci_get_dev(pacc, 0, 0, 0x13, 0);
|
2017-03-30 17:47:24 +02:00
|
|
|
} else {
|
2016-11-18 00:51:13 +01:00
|
|
|
ahci = pci_get_dev(pacc, 0, 0, 0x1f, 2);
|
2017-03-30 17:47:24 +02:00
|
|
|
if (ahci) {
|
|
|
|
|
pci_fill_info(ahci, PCI_FILL_CLASS);
|
|
|
|
|
if (ahci->device_class != PCI_CLASS_STORAGE_SATA)
|
|
|
|
|
ahci = pci_get_dev(pacc, 0, 0, 0x17, 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
2016-06-08 16:39:22 +02:00
|
|
|
|
|
|
|
|
if (ahci) {
|
2017-03-31 12:09:58 +02:00
|
|
|
pci_fill_info(ahci, PCI_FILL_IDENT | PCI_FILL_BASES |
|
|
|
|
|
PCI_FILL_CLASS);
|
2016-06-08 16:39:22 +02:00
|
|
|
|
2017-03-30 17:47:24 +02:00
|
|
|
if (ahci->vendor_id != PCI_VENDOR_ID_INTEL ||
|
|
|
|
|
ahci->device_class != PCI_CLASS_STORAGE_SATA)
|
|
|
|
|
ahci = NULL;
|
2016-06-08 16:39:22 +02:00
|
|
|
}
|
|
|
|
|
|
2019-10-25 00:16:22 +02:00
|
|
|
print_system_info(nb, sb, gfx);
|
2015-05-20 14:04:41 +02:00
|
|
|
|
2008-05-14 00:14:21 +02:00
|
|
|
/* Now do the deed */
|
|
|
|
|
if (dump_gpios) {
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
print_gpios(sb, 1, show_gpio_diffs);
|
|
|
|
|
printf("\n\n");
|
|
|
|
|
} else if (show_gpio_diffs) {
|
|
|
|
|
print_gpios(sb, 0, show_gpio_diffs);
|
2008-05-14 00:14:21 +02:00
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dump_rcba) {
|
|
|
|
|
print_rcba(sb);
|
|
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dump_pmbase) {
|
2010-11-27 15:44:19 +01:00
|
|
|
print_pmbase(sb, pacc);
|
2008-05-14 00:14:21 +02:00
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-13 22:22:26 +01:00
|
|
|
if (dump_lpc) {
|
|
|
|
|
print_lpc(sb, pacc);
|
|
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
2008-05-14 00:14:21 +02:00
|
|
|
if (dump_mchbar) {
|
2015-10-10 13:20:32 +02:00
|
|
|
print_mchbar(nb, pacc, dump_spd_file);
|
2008-05-14 00:14:21 +02:00
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dump_epbar) {
|
|
|
|
|
print_epbar(nb);
|
|
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dump_dmibar) {
|
|
|
|
|
print_dmibar(nb);
|
|
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dump_pciexbar) {
|
|
|
|
|
print_pciexbar(nb);
|
|
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dump_coremsrs) {
|
2019-10-09 17:35:23 +02:00
|
|
|
print_intel_msrs(cores_range_start, cores_range_end);
|
2008-05-14 00:14:21 +02:00
|
|
|
printf("\n\n");
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-25 20:16:55 +02:00
|
|
|
if (dump_ambs)
|
2012-01-08 15:27:18 +01:00
|
|
|
print_ambs(nb, pacc);
|
2015-01-03 02:52:10 +01:00
|
|
|
|
2017-07-25 20:16:55 +02:00
|
|
|
if (dump_spi)
|
2015-01-03 02:52:10 +01:00
|
|
|
print_spi(sb);
|
2015-05-20 14:04:41 +02:00
|
|
|
|
2017-07-25 20:16:55 +02:00
|
|
|
if (dump_gfx)
|
2015-05-20 14:04:41 +02:00
|
|
|
print_gfx(gfx);
|
|
|
|
|
|
2017-07-25 20:16:55 +02:00
|
|
|
if (dump_ahci)
|
2016-06-08 16:39:22 +02:00
|
|
|
print_ahci(ahci);
|
|
|
|
|
|
2017-07-24 22:53:26 +02:00
|
|
|
if (dump_sgx)
|
|
|
|
|
print_sgx();
|
|
|
|
|
|
2020-09-03 20:28:19 +02:00
|
|
|
if (dump_tme)
|
|
|
|
|
print_tme();
|
|
|
|
|
|
2022-12-19 18:52:34 +01:00
|
|
|
if (dump_keylocker)
|
|
|
|
|
print_keylocker();
|
|
|
|
|
|
2018-03-13 21:58:52 +01:00
|
|
|
if (pcr_count)
|
|
|
|
|
print_pcr_ports(sb, dump_pcr, pcr_count);
|
|
|
|
|
|
2008-05-14 00:14:21 +02:00
|
|
|
/* Clean up */
|
2017-04-05 17:39:57 +02:00
|
|
|
pcr_cleanup();
|
2017-04-05 17:33:46 +02:00
|
|
|
if (ahci)
|
|
|
|
|
pci_free_dev(ahci);
|
|
|
|
|
if (gfx)
|
|
|
|
|
pci_free_dev(gfx);
|
2008-05-14 00:14:21 +02:00
|
|
|
pci_free_dev(nb);
|
2017-04-05 17:33:46 +02:00
|
|
|
/* `sb` wasn't allocated by pci_get_dev() */
|
2008-05-14 00:14:21 +02:00
|
|
|
pci_cleanup(pacc);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|